CN1408126A - 具有金属－绝缘体－金属电容器的集成元件 - Google Patents
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Abstract
一种制造具有集成金属－绝缘体－金属电容器(7)的集成元件的方法。首先，将层间电介层(11)和上部电极(12)沉积在由铜制成的下部电极(6)的整个表面上。然后，金属－绝缘体－金属电容器(7)图案形成，并且蚀刻过程中止于层间电介层(11)。这样可以避免上部电极(12)和下部电极(6)之间发生短路。
Description
技术领域
本发明涉及一种集成元件，其内连导线由含铜的合金和一个金属-绝缘体-金属电容器制成。
背景技术
用于双极型(BIPOLAR-)、双极型互补金属氧化物半导体(BICMOS)和互补金属氧化物半导体(CMOS)技术的高频电路要求其集成电容器具有高电压线性，使电容、特别是低寄生电容(low parasiticcapacitancc)能够被精确的设置。电压引起的空间电荷区意味着迄今为止使用的普通金属氧化物半导体(MOS)电容器的电压线性不足。此外，与基体之间距离过短必须要求具有大量的寄生电容。这些问题可以通过使用金属-绝缘体-金属电容器(MIM电容器)来避免。这些金属-绝缘体-金属电容器应尽量按现有的多层金属化(multilayermetalization)概念进行集成，从而避免改变和影响相邻的内连导线(interconnect)。
目前，没有任何已知方法可以用来将金属-绝缘体-金属电容器集成于具有含铜内连导线的集成电路中。
发明内容
在现有技术的基础之上，本发明的目的是提出一种集成元件，其内连导线由含铜合金和一个集成的金属-绝缘体-金属电容器组成，以及该集成元件的制造方法。
该目的的实现方式是权利要求1中提出的一种集成元件和权利要求10中提出的一种制造方法。
金属-绝缘体-金属电容器具有一个电极，位于内连导线的一个金属面内。由于层间介电层(dielectric interlayer)和金属化层很薄，因此金属-绝缘体-金属电容器可按现有概念进行集成，并且在用于制造具有无源组件(passive component)的集成元件时不会有太大的困难。
在金属-绝缘体-金属电容器的制造过程中，层间介电层可顺便发挥蚀刻中止层(etching stop)的作用，这确保了下面的含铜电极不受蚀刻的侵蚀。此外，由于发挥蚀刻中止层作用的层间介电层不会被完全去除，因而还可以避免金属化层和下面的电极之间发生短路。
一种较为便利的制造金属-绝缘体-金属电容器的方法是，首先沉积层间介电层，使其发挥蚀刻中止层的作用，然后在位于内连导线的金属面内的电极上覆盖金属化层，将其表面完全覆盖。在随后的金属化层图案形成作业中，层间介电层发挥蚀刻中止层的作用，保留并将表面完全覆盖，从而可以有效地抑制金属-绝缘体-金属电容器的边缘发生短路。
本发明的进步构造将在从属权利要求书中逐一说明。
以下将通过附图具体说明本发明的实施例，附图内容为：
附图说明
图1为一个具有集成的金属-绝缘体-金属电容器的集成元件的剖面图局部。
具体实施方式
在如图1的剖面图所示的层面中通常包含集成电路的无源组件。在第一金属面1内。内连导线3被布置在不导电的扩散障碍层(diffusionbarrier)2之间。内连导线3与下部电极6相连，并通过通孔4布置在金属-绝缘体-金属电容器7的第二金属面5内。如图1所示，除了下部电极6之外，金属面5内还有内连导线8。内连导线8与下部电极6被植入层电介层9。其材料与金属面1内的隔离电介层10的材料相同，用于将内连导线3与其他导线绝缘。层间电介层11用于下部电极6，并且在层间电介层11上具有一个金属化层，组成了上部电极12。在金属-绝缘体-金属电容器电容器7区中，层间电介层11的厚度比金属-绝缘体-金属电容器7外部的厚度更大，并且延伸覆盖层间电介层9的整个表面。
金属-绝缘体-金属电容器7的上部电极和内连导线3通过通孔13与第三金属面15内的内连导线14相连。上部电极12、通孔13，以及第三金属面内5的内连导线14位于层间电介层16内。最后，第三金属面15的上方是另外的不导电扩散障碍区17和另外的覆盖层18。
内连导线3、8和14，下部电极6，以及通孔4和13由含铜合金，最好是纯铜制成。内连导线3、8和14，下部电极6，以及通孔4和13的制造方法采用已知的镶嵌流程(Damascene process)技术。
制造内连导线8和14，下部电极6，以及通孔4和13时特别采用双镶嵌流程(dual Damascene process)。
在镶嵌流程中，首先使分开的电介层10完全覆盖位于基体上的扩散障碍层2。在本文中，术语“基体”既指同质基体，也指采用分层结构的基体。然后，将内连导线3所提供的沟槽(trench)蚀刻成分开的电介层10。最后，以保形沉积(conformal deposition)方式将沟渠沿着导电障碍层19排列。在随后的电解步骤中，障碍层19发挥电极的作用，用于内连导线3的铜的沉积。
如上文所述，内连导线8，下部电极6和通孔4采用双镶嵌流程进行制造。首先将层间电介层沉积于扩散障碍层2的整个表面。然后将内连导线8和下部电极6的沟渠自层间电介层9蚀刻出来。在另外的蚀刻操作中，这些沟渠被另外隐藏于通孔4的位置。然后，将所形成凹口通过保形沉积的方式覆盖上障碍层20。随后，沉积下来的铜在障碍层19积聚，并在随后的电解步骤中发挥电极的作用。
最后，将用于上部电极12的层间电介层11和金属化层沉积在整个平面化表面(planarized surface)上。用于上部电极12的金属化层既可以是合金构成的均质层，也可以是金属层和导电障碍层的层叠。然后，金属-绝缘体-金属电容器7形成图案，并且层间电介层11包括一个蚀刻中止层。因此，层间电介层11甚至保留在金属-绝缘体-金属电容器7的外部。上部电极12和下部电极6的广泛电气隔离(extensive electrical scparation)意味着下部电极6和上部电极12之间没有短路的风险。本发明的另一优点在于层间电介层11和上部电极12可用于平面化表面。这确保层间电介层11和上部电极12的平面性。
金属-绝缘体-金属电容器7构成之后，沉积层间电介层16。然后，利用双镶嵌流程构造内连导线14和通孔13。发挥电极作用的障碍区21需要沉积铜。当用于通孔13的沟渠蚀刻出来之后，蚀刻过程将在金属-绝缘体-金属电容器7的上部电极12和内连导线14同时停止。
可用于制造层间电介层11的适当材料为Si3N4或SiO2。此外，还可采用其他高介电常数的材料来制造层间电介层11，比如：Ta2O5或Bi2Sr3TiO3和BaxSr1-xTiO3，其中0≤x≤1。本发明的优点尤其在于，无须个别了解材料的蚀刻特征，因为在层间电介层11中存在蚀刻中止层。可用于制造上部电极12的适当材料包括钽(Ta)，氮化钽(TaN)，硅化物，以及钛(Ti)，氮化钛(TiN)，钨化钛(TiW)，钨(W)和WNx等材料，其中0≤x≤2。此外，一些导电材料，如：硅(Si)，钨(W)，铜(Cu)，金(Au)，银(Ag)，钛(Ti)和铂(Pt)，及其合金也可用来制造上部电极12。
在附图中没有显示的本发明的一个修正实施例中，上部电极12和层间电介层11被一层氮化硅(SiN)保护层所覆盖。该保护层作为通孔13的蚀刻中止层，并能保护上部电极12免受通孔13蚀刻的影响。此外，上部电极12被封装在元件的一侧，从而进一步确保了与下部电极6之间的绝缘。
最后，应当指出的是，本发明书推荐的集成元件尤其适用于高频技术。
Claims (12)
1.具有含铜合金的内连导线(3，8，14)和一个金属-绝缘体-金属电容器(7)的集成元件，其特征在于，
该电容器(7)由一在一用于内连导线的金属平面(5)的第一电极(6)、一首先用作蚀刻中止层的层间电介层(11)和一金属化层(12)构成。
2.根据权利要求1所述的集成元件，其特征在于，层间电介层(11)额外用作扩散障碍层。
3.根据权利要求1或2所述的集成元件，其特征在于，金属化层(12)为金属层和导电障碍层的层叠。
4.根据权利要求1-3中任一项所述的集成元件，其特征在于，金属化层(12)至少包括以下金属所组成的群组中的一种金属：铝(Al)，硅(Si)，钨(W)，铜(Cu)，金(Au)，银(Ag)，钛(Ti)和铂(Pt)。
5.根据权利要求1-4中任一项所述的集成元件，其特征在于，内连导线(3，8，14)和第一电极(6)相对于层间电介层(9，16)由障碍区(19，20，21)界定。
6.根据权利要求3或5所述的集成元件，其特征在于，障碍区(19，20，21)用以下元素所组成的群组中的元素制造：钽(Ta)，氮化钽(TaN)，钨化钛(TiW)，钨(W)，WNx，钛(Ti)，氮化钛(TiN)或硅化物，其中0≤x≤2。
7.根据权利要求1-6中任一项所述的集成元件，其特征在于，层间电介层(11)由SiO2或Si3N4制成。
8.根据权利要求1-6中任一项所述的集成元件，其特征在于，层间电介层(11)由介电常数＞80的电介质材料构成。
9.根据权利要求8所述的集成元件，其特征在于，层间电介层(11)由以下材料所组成的群组中的材料制成：Ta2O5，Bi2Sr3TiO3和BaxSr1-xTiO3，其中0≤x≤1。
10.一种制造集成元件的方法，该元件具有含铜合金的内连导线(3，8，14)和一个金属-绝缘体-金属电容器(7)，其中首先在层间电介层(16)内嵌入一第一电极(6)，其特征在于，
将层间电介层(11)和金属化层(12)先后沉积在第一电极(6)的整个表面上，以及
使金属化层(12)形成图案。
11.根据权利要求10所述的方法，其特征在于，层间电介层(11)被用作蚀刻中止层。
12.根据权利要求10或11所述的方法，其特征在于，第一电极(16)在镶嵌工艺中制成。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP00104264.7 | 2000-03-01 | ||
| EP00104264A EP1130654A1 (de) | 2000-03-01 | 2000-03-01 | Integriertes Bauelement mit Metall-Isolator-Metall-Kondensator |
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| CN1408126A true CN1408126A (zh) | 2003-04-02 |
| CN1194418C CN1194418C (zh) | 2005-03-23 |
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| CNB018059805A Expired - Fee Related CN1194418C (zh) | 2000-03-01 | 2001-02-19 | 一种集成元件的制造方法 |
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| US (1) | US20030040161A1 (zh) |
| EP (2) | EP1130654A1 (zh) |
| JP (1) | JP2003526211A (zh) |
| KR (1) | KR20020077923A (zh) |
| CN (1) | CN1194418C (zh) |
| TW (1) | TW504832B (zh) |
| WO (1) | WO2001065610A1 (zh) |
Cited By (3)
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| CN100359664C (zh) * | 2004-11-26 | 2008-01-02 | 上海华虹Nec电子有限公司 | 一种金属电容的刻蚀方法 |
| CN100378987C (zh) * | 2005-04-28 | 2008-04-02 | 台湾积体电路制造股份有限公司 | 多层金属层半导体元件及其制造方法 |
| CN104395721A (zh) * | 2012-03-16 | 2015-03-04 | 维塔尔传感器控股有限公司 | 介电常数屏蔽 |
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| KR100429877B1 (ko) * | 2001-08-04 | 2004-05-04 | 삼성전자주식회사 | 금속-절연체-금속 커패시터 및 비아 컨택을 갖는 반도체소자의 제조 방법 |
| KR100428789B1 (ko) * | 2001-12-05 | 2004-04-28 | 삼성전자주식회사 | 금속/절연막/금속 캐퍼시터 구조를 가지는 반도체 장치 및그 형성 방법 |
| DE10161285A1 (de) | 2001-12-13 | 2003-07-03 | Infineon Technologies Ag | Integriertes Halbleiterprodukt mit Metall-Isolator-Metall-Kondensator |
| US6593185B1 (en) * | 2002-05-17 | 2003-07-15 | United Microelectronics Corp. | Method of forming embedded capacitor structure applied to logic integrated circuit |
| US6784478B2 (en) * | 2002-09-30 | 2004-08-31 | Agere Systems Inc. | Junction capacitor structure and fabrication method therefor in a dual damascene process |
| US6709918B1 (en) * | 2002-12-02 | 2004-03-23 | Chartered Semiconductor Manufacturing Ltd. | Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology |
| KR100505658B1 (ko) * | 2002-12-11 | 2005-08-03 | 삼성전자주식회사 | ＭＩＭ(Ｍｅｔａｌ-Ｉｎｓｕｌａｔｏｒ-Ｍｅｔａｌ)커패시터를 갖는 반도체 소자 |
| US6999298B2 (en) | 2003-09-18 | 2006-02-14 | American Semiconductor, Inc. | MIM multilayer capacitor |
| DE10350752A1 (de) * | 2003-10-30 | 2005-06-09 | Infineon Technologies Ag | Verfahren zum Ausbilden eines Dielektrikums auf einer kupferhaltigen Metallisierung und Kondensatoranordnung |
| US7029972B2 (en) * | 2004-07-20 | 2006-04-18 | Texas Instruments Incorporated | Method of manufacturing a metal-insulator-metal capacitor |
| US7485968B2 (en) * | 2005-08-11 | 2009-02-03 | Ziptronix, Inc. | 3D IC method and device |
| US8169014B2 (en) * | 2006-01-09 | 2012-05-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interdigitated capacitive structure for an integrated circuit |
| JP4524680B2 (ja) * | 2006-05-11 | 2010-08-18 | セイコーエプソン株式会社 | 半導体装置の製造方法、電子機器の製造方法、半導体装置および電子機器 |
| US7439151B2 (en) * | 2006-09-13 | 2008-10-21 | International Business Machines Corporation | Method and structure for integrating MIM capacitors within dual damascene processing techniques |
| DE102008006962B4 (de) * | 2008-01-31 | 2013-03-21 | Advanced Micro Devices, Inc. | Verfahren zur Herstellung von Halbleiterbauelementen mit einem Kondensator im Metallisierungssystem |
| US7879681B2 (en) * | 2008-10-06 | 2011-02-01 | Samsung Electronics Co., Ltd. | Methods of fabricating three-dimensional capacitor structures having planar metal-insulator-metal and vertical capacitors therein |
| US8766417B2 (en) | 2009-05-04 | 2014-07-01 | Mediatek Inc. | Integrated circuit chip with reduced IR drop |
| US8476745B2 (en) * | 2009-05-04 | 2013-07-02 | Mediatek Inc. | Integrated circuit chip with reduced IR drop |
| CN101807517B (zh) * | 2010-02-25 | 2011-09-21 | 中国科学院上海微系统与信息技术研究所 | 形成铜互连mim电容器结构的方法 |
| US8598593B2 (en) * | 2011-07-15 | 2013-12-03 | Infineon Technologies Ag | Chip comprising an integrated circuit, fabrication method and method for locally rendering a carbonic layer conductive |
| FR2994019B1 (fr) * | 2012-07-25 | 2016-05-06 | Commissariat Energie Atomique | Procede pour la realisation d'une capacite |
| JP6356536B2 (ja) * | 2014-08-25 | 2018-07-11 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US9953941B2 (en) | 2015-08-25 | 2018-04-24 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
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| US5583359A (en) * | 1995-03-03 | 1996-12-10 | Northern Telecom Limited | Capacitor structure for an integrated circuit |
| US5708559A (en) * | 1995-10-27 | 1998-01-13 | International Business Machines Corporation | Precision analog metal-metal capacitor |
| US5926359A (en) * | 1996-04-01 | 1999-07-20 | International Business Machines Corporation | Metal-insulator-metal capacitor |
| US5969422A (en) * | 1997-05-15 | 1999-10-19 | Advanced Micro Devices, Inc. | Plated copper interconnect structure |
| US6025226A (en) * | 1998-01-15 | 2000-02-15 | International Business Machines Corporation | Method of forming a capacitor and a capacitor formed using the method |
| US5946567A (en) * | 1998-03-20 | 1999-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for making metal capacitors for deep submicrometer processes for semiconductor integrated circuits |
| US6016000A (en) * | 1998-04-22 | 2000-01-18 | Cvc, Inc. | Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics |
-
2000
- 2000-03-01 EP EP00104264A patent/EP1130654A1/de not_active Withdrawn
-
2001
- 2001-02-19 WO PCT/EP2001/001853 patent/WO2001065610A1/de not_active Application Discontinuation
- 2001-02-19 EP EP01919307A patent/EP1264351A1/de not_active Withdrawn
- 2001-02-19 KR KR1020027011177A patent/KR20020077923A/ko not_active Application Discontinuation
- 2001-02-19 CN CNB018059805A patent/CN1194418C/zh not_active Expired - Fee Related
- 2001-02-19 JP JP2001564400A patent/JP2003526211A/ja not_active Abandoned
- 2001-03-15 TW TW090106055A patent/TW504832B/zh not_active IP Right Cessation
-
2002
- 2002-09-03 US US10/237,230 patent/US20030040161A1/en not_active Abandoned
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100359664C (zh) * | 2004-11-26 | 2008-01-02 | 上海华虹Nec电子有限公司 | 一种金属电容的刻蚀方法 |
| CN100378987C (zh) * | 2005-04-28 | 2008-04-02 | 台湾积体电路制造股份有限公司 | 多层金属层半导体元件及其制造方法 |
| CN104395721A (zh) * | 2012-03-16 | 2015-03-04 | 维塔尔传感器控股有限公司 | 介电常数屏蔽 |
Also Published As
| Publication number | Publication date |
|---|---|
| TW504832B (en) | 2002-10-01 |
| JP2003526211A (ja) | 2003-09-02 |
| CN1194418C (zh) | 2005-03-23 |
| KR20020077923A (ko) | 2002-10-14 |
| US20030040161A1 (en) | 2003-02-27 |
| WO2001065610A1 (de) | 2001-09-07 |
| EP1264351A1 (de) | 2002-12-11 |
| EP1130654A1 (de) | 2001-09-05 |
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