TW504832B - Integrated component with metal-isolator-metal-capacitor and its manufacturing method - Google Patents
Integrated component with metal-isolator-metal-capacitor and its manufacturing method Download PDFInfo
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- TW504832B TW504832B TW090106055A TW90106055A TW504832B TW 504832 B TW504832 B TW 504832B TW 090106055 A TW090106055 A TW 090106055A TW 90106055 A TW90106055 A TW 90106055A TW 504832 B TW504832 B TW 504832B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910052802 copper Inorganic materials 0.000 claims abstract description 14
- 239000010949 copper Substances 0.000 claims abstract description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 230000004888 barrier function Effects 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 11
- 229910045601 alloy Inorganic materials 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 230000009977 dual effect Effects 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- 239000002131 composite material Substances 0.000 claims 1
- 239000003989 dielectric material Substances 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 34
- 239000011229 interlayer Substances 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
504832
五、發明説明（1 ) 本發明涉及一種具有導電軌之積體元件，其具有：由 含有銅之合金所構成之導電軌；及金屬-隔離體-金屬-電 容器所構成。 以BIPOLAR^BICMOS-和CMOS技術製成之高頻電路 需要積體電容器，其須具有較高之電壓線性，準確可調 之電容値及較低之寄生電容。目前所用之傳統式MOS 電容器由於電壓感應之空間電荷區而使電壓線性不足 夠。此外，至基板之較小距離造成很多寄生電容。這些 因難性可藉由使用所謂金屬-隔離體-金屬-電容器（MIM 電容器）來克服。此種MIM電容器在現有之多層金屬 之槪念中在積體化時應儘可能不受相鄰導電軌之影響 且不會因此而改變。 目前尙未有任何槪念可使MIM電容器積體化於此種 具有含銅導電軌之積體元件中。 由先前技藝開始，本發明之目的是提供一種積體元件， 其具有導電軌（由含銅之合金所構成）及積體式MI Μ電 容器，本發明亦涉及此種元件之製造方法。 此目的以申請專利範圍第1項之積體元件及第1 〇項 之方法來達成。 Μ ΙΜ電容器具有一個形成在導電軌用之金屬平面中 之電極。由於介電質中間層及金屬層可保持很薄，則 ΜΙΜ電容器不需很大之困難性即能以現有之槪念進行 積體化以製成一種具有被動元件之積體元件。 在ΜΙΜ電容器製造時，介電質中間層用作蝕刻停止 504832 五、發明説明（2 ) 層。這樣可確保：其下方之含銅之電極不會受到鈾刻介 質所侵蝕。此外，由於該作爲蝕刻停止層用之介電質中 間層未完全去除，則在金屬層及其下方之電極之間不會 形成短路。 Μ IM電容器以下述方式適當地製成：在導電軌用之金 屬平面中在裸露之電極上首先在整面上沈積一種作爲 飩刻停止層用之介電質中間層，然後整面上沈積一種金 屬層。在隨後對此金屬層進行結構化時，則介電質中間 層作爲飩刻停止層甩而保留在整面上。因此可使MI Μ 電容器之各邊緣上之短路現象被有效地抑制。 本發明之實施例以下將依據附圖來描述。圖式簡單 說明： 第1圖具有積體式ΜΙΜ電容器之積體元件之橫切 面之一部份。 第1圖是含有積體電路之被動元件之這些層之橫切 面。在第一金屬平面1中在非導電性之擴散位障2之 間配置導電軌3。導電軌3經由穿孔4而與ΜΙΜ電容 器7之配置在第二金屬平面5中之下（under)電極6相 連。在第1圖中，在金屬平面5中除了下電極6之外亦 存在其它之導電軌8。導電軌8和下電極6埋入中間 介電質9中。金屬平面1中以相同之材料作爲隔離介 電質10使各導電軌3互相隔離。在下電極6上施加一 種介電質中間層11，其上存在一種金屬層，此金屬層形 成上電極12。介電質中間層11在MIM電容器7之區 -4- 504832 五、發明説明（3 ) 域中所具有之厚度較MIM電容器7外部者還大且在整 面上延伸於中間介電質9上。 ΜIM電容器7之上電極12及導電軌3經由穿孔13 而與第三金屬平面15中之導電軌14相連。第三金屬 平面15中之上電極12,穿孔13及導電軌14存在於中 間介電質16中。最後，在第三金屬平面15上方存在另 一非導電之擴散位障1 7及另一覆蓋層1 8。 各導電軌3，8, 14,下電極5以及穿孔4,13是由含銅 之合金（較佳是純銅）所構成。爲了製成各導電軌 3，8, 14,下電極5以及穿孔4,13,須使用所謂鑲嵌 (Damascene)方法。 特別是爲了製成各導電軌8,14,下電極6以及各穿孔 4,13時須使用雙鑲嵌方法。 在鑲嵌方法中，例如首先在擴散位障2(其位於基板上) 上整面沈積該隔離介電質1〇。在此種方式中此基板是 一種均勻之基體且是一種具有層結構之基體。在隔離 介電質1 0中蝕刻出一些溝渠，其用作導電軌3。最後， 藉由共形（conform)之沈積導電位障19施加在溝渠 上。此位障19在隨後之電解中用作電極以沈積各導電 軌3用之銅。 如上所述，導電軌8,下電極6及穿孔4以雙鑲嵌方法 製成。首先在擴散位障2之整面上沈積中間介電質 9。然後由中間介電質9中蝕刻出各導電軌8所需之溝 渠及下電極6。在下一蝕刻步驟中在這些位置（其上設
504832_______— 五、發明説明（4 ) 有各穿孔4)上使這些溝渠加深。這樣所形成之各凹口 中然後以共形之沈積方式設置一種位障2 0。在隨後之 電解中在用作電極之此種位障20上累積該已沈積之 銅。 最後，在已整平之表面上整面沈積該介電質中間層 1 1及金屬層（其用作上電極1 2)。此種作爲上電極1 2 用之金屬層可以是一種由合金構成之均勻之層或一種 由金屬層及導電位障所構成之堆疊。然後利用介電質 中間層1 1中之蝕刻停止層來對MIM電容器7進行結 構化。此介電質中間層11因此保持在MIM電容器7 之外部。由於上電極1 2及下電極6在空間上已廣泛地 被電性地隔離，則在上電極1 2和下電極6之間不會發 生短路之危險性。其它優點是：介電質中間層11和上 電極12可施加在已整平之表面上。這樣可確保介電質 中間層1 1和上電極1 2之平坦性。 在形成MIM電容器7之後進行中間介電質16之沈 積。然後以雙鑲嵌方法形成導電軌1 4及穿孔1 3。此 時位障2 1用作銅沈積時所需之電極。在對各穿孔1 3 用之溝渠進行蝕刻時在MIM電容器7之上電極丨2上 及導電軌1 4上同時停止。 例如，Si3N4或Si02適合用作介電質中間層1 1之材 料。此外，介電常數較大之材料（例如，Ta2 0 5或 Bi2Sr3Ti03以及BaxSrHTiOhOSXSl)亦適合用作介電 質中間層1 1。特別有利的是：這些材料之蝕刻特性之細 504832 五、發明説明（5 ) 節不必已爲人所知，這是因爲蝕刻是停止於介電質中間 層1 1之中央。Ta，TaN以及矽化物及材料（例 如，1^，1^1^，1^\¥，\¥及\\^乂，0$\$2)適合用作上電極12。 此外，導電性材料Si，W，Cu，Au，Ag，Ti及Pt和其合金都 可用作上電極1 2。 在圖式中未顯示之其它形式之實施例中，上電極12 及介電質中間層1 1由SiN所構成之保護層所覆蓋。此 保護層作爲穿孔1 3之蝕刻用之停止層且可防止：穿孔 1 3被蝕刻時上電極1 2受到侵蝕。此外，上電極1 2向著 一側而被包封，因此可另外對該下電魎6形成隔離作 用。 最後須指出：所建議之積體元件特別適用於高頻技術 中〇 符號說明 1 ··.弟一*金屬平面 2…擴散位障 3.. .導電軌 4…穿孔 5.. .第二金屬平面 6 ...下電極 7…金屬-隔離體-金屬-電容器 8 ...導電軌 9.. .中間介電質 10.. .隔離介電質 504832 五、發明説明（6 ) 11·· .中間層 1 2 .. .上電極 13. .穿孔 14. .導電軌 15. .第三金屬平面 1 6 . .中間介電質 1 7 . ..擴散位障 1 8 . ..覆蓋層 19. ..導電位障 20,21…位障 -8-
Claims (1)
- 504832六、申請專利範圍 第90106055號「具有導電軌之積體元件及其製造方法」專利 案 （91年7月修正） Λ申請專利範圍 1· 一種具有導電軌（3,8，14)之積體元件，其由含銅之合金及 ΜΙΜ電容器（7)所構成，其特徵爲：電容器（7)由：導電軌用之 金屬平面（5)中之第一電極（6)，作爲蝕刻停止層用之介電 質中間層（11)，及金屬層（12)所構成。 2·如申請專利範圍第1項之積體元件，其中該介電質中間層 (11)另作爲擴散位障用。 3. 如申請專利範圍第1或第2項之積體元件，其中金屬層（12) 是由各金屬層及導電位障所形成之堆疊。 4. 如申請專利範圍第1項之積體元件，其中金屬層（12)含有 至少一種由一群Al，Si，W，Cu，Au，Ag，Ti和Pt所形成之金 屬。 5. 如申請專利範圍第1項之積體元件，其中各導電軌（3,8，14) 及第一電極（6)藉由位障（19,20,21)而與中間介電質（9，16) 相隔開。 6. 如申請專利範圍第5項之積體元件，其中該位障（19,20,21) 由一群Ta，TaN，TiW，W，WNx，Ti，TiN或矽化物所形成之元件 所形成，其中0SXS2。 7. 如申請專利範圍第1項之積體元件，其中介電質中間層（11) 由3丨02或Si3N4所製成。 8. 如申請專利範圍第1項之積體元件，其中介電質中間層（11) 由介電常數>80之介電質材料所形成。 504832六、申請專利範圍 9. 如申請專利範圍第8項之積體元件，其中介電質中間層（11) 由一群Ta205，Bi2Si:3Ti03及BaxSr^TiOs所形成之材料所 製成，其中0SXS1 〇 10. —種具有導電軌（3,8,14)之積體元件之製造方法，此積體元 件由含有銅之合金及MIM電容器（7)所構成，首先形成一 種埋置於中間介電質（16)中之第一電極（6)，其特徵爲：在第 一電極（6)上方首先在整面上沈積一種介電質中間層（11) 及金屬層（12)，然後對此金屬層（12)進行結構化。 11. 如申請專利範圍第10項之方法，其中此介電質中間層（11) 用作蝕刻停止層。 12·如申請專利範圍第1〇或第11項之方法，其中第一電極（6) 以雙鑲嵌法製成。 -2-
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP00104264A EP1130654A1 (de) | 2000-03-01 | 2000-03-01 | Integriertes Bauelement mit Metall-Isolator-Metall-Kondensator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW504832B true TW504832B (en) | 2002-10-01 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW090106055A TW504832B (en) | 2000-03-01 | 2001-03-15 | Integrated component with metal-isolator-metal-capacitor and its manufacturing method |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20030040161A1 (zh) |
| EP (2) | EP1130654A1 (zh) |
| JP (1) | JP2003526211A (zh) |
| KR (1) | KR20020077923A (zh) |
| CN (1) | CN1194418C (zh) |
| TW (1) | TW504832B (zh) |
| WO (1) | WO2001065610A1 (zh) |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100429877B1 (ko) * | 2001-08-04 | 2004-05-04 | 삼성전자주식회사 | 금속-절연체-금속 커패시터 및 비아 컨택을 갖는 반도체소자의 제조 방법 |
| KR100428789B1 (ko) * | 2001-12-05 | 2004-04-28 | 삼성전자주식회사 | 금속/절연막/금속 캐퍼시터 구조를 가지는 반도체 장치 및그 형성 방법 |
| DE10161285A1 (de) | 2001-12-13 | 2003-07-03 | Infineon Technologies Ag | Integriertes Halbleiterprodukt mit Metall-Isolator-Metall-Kondensator |
| US6593185B1 (en) * | 2002-05-17 | 2003-07-15 | United Microelectronics Corp. | Method of forming embedded capacitor structure applied to logic integrated circuit |
| US6784478B2 (en) * | 2002-09-30 | 2004-08-31 | Agere Systems Inc. | Junction capacitor structure and fabrication method therefor in a dual damascene process |
| US6709918B1 (en) * | 2002-12-02 | 2004-03-23 | Chartered Semiconductor Manufacturing Ltd. | Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology |
| KR100505658B1 (ko) * | 2002-12-11 | 2005-08-03 | 삼성전자주식회사 | ＭＩＭ(Ｍｅｔａｌ-Ｉｎｓｕｌａｔｏｒ-Ｍｅｔａｌ)커패시터를 갖는 반도체 소자 |
| US6999298B2 (en) | 2003-09-18 | 2006-02-14 | American Semiconductor, Inc. | MIM multilayer capacitor |
| DE10350752A1 (de) * | 2003-10-30 | 2005-06-09 | Infineon Technologies Ag | Verfahren zum Ausbilden eines Dielektrikums auf einer kupferhaltigen Metallisierung und Kondensatoranordnung |
| US7029972B2 (en) * | 2004-07-20 | 2006-04-18 | Texas Instruments Incorporated | Method of manufacturing a metal-insulator-metal capacitor |
| CN100359664C (zh) * | 2004-11-26 | 2008-01-02 | 上海华虹Nec电子有限公司 | 一种金属电容的刻蚀方法 |
| US7151052B2 (en) * | 2005-04-28 | 2006-12-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple etch-stop layer deposition scheme and materials |
| US7485968B2 (en) | 2005-08-11 | 2009-02-03 | Ziptronix, Inc. | 3D IC method and device |
| US8169014B2 (en) * | 2006-01-09 | 2012-05-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interdigitated capacitive structure for an integrated circuit |
| JP4524680B2 (ja) * | 2006-05-11 | 2010-08-18 | セイコーエプソン株式会社 | 半導体装置の製造方法、電子機器の製造方法、半導体装置および電子機器 |
| US7439151B2 (en) * | 2006-09-13 | 2008-10-21 | International Business Machines Corporation | Method and structure for integrating MIM capacitors within dual damascene processing techniques |
| DE102008006962B4 (de) * | 2008-01-31 | 2013-03-21 | Advanced Micro Devices, Inc. | Verfahren zur Herstellung von Halbleiterbauelementen mit einem Kondensator im Metallisierungssystem |
| US7879681B2 (en) * | 2008-10-06 | 2011-02-01 | Samsung Electronics Co., Ltd. | Methods of fabricating three-dimensional capacitor structures having planar metal-insulator-metal and vertical capacitors therein |
| US8766417B2 (en) | 2009-05-04 | 2014-07-01 | Mediatek Inc. | Integrated circuit chip with reduced IR drop |
| US8476745B2 (en) * | 2009-05-04 | 2013-07-02 | Mediatek Inc. | Integrated circuit chip with reduced IR drop |
| CN101807517B (zh) * | 2010-02-25 | 2011-09-21 | 中国科学院上海微系统与信息技术研究所 | 形成铜互连mim电容器结构的方法 |
| US8598593B2 (en) * | 2011-07-15 | 2013-12-03 | Infineon Technologies Ag | Chip comprising an integrated circuit, fabrication method and method for locally rendering a carbonic layer conductive |
| KR20150016214A (ko) * | 2012-03-16 | 2015-02-11 | 바이탈 센서즈 홀딩 컴퍼니 인코포레이티드 | 유전율 차폐 |
| FR2994019B1 (fr) * | 2012-07-25 | 2016-05-06 | Commissariat Energie Atomique | Procede pour la realisation d'une capacite |
| JP6356536B2 (ja) * | 2014-08-25 | 2018-07-11 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US9953941B2 (en) | 2015-08-25 | 2018-04-24 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
| US11227872B2 (en) * | 2019-04-25 | 2022-01-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | FeRAM MFM structure with selective electrode etch |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5583359A (en) * | 1995-03-03 | 1996-12-10 | Northern Telecom Limited | Capacitor structure for an integrated circuit |
| US5708559A (en) * | 1995-10-27 | 1998-01-13 | International Business Machines Corporation | Precision analog metal-metal capacitor |
| US5926359A (en) * | 1996-04-01 | 1999-07-20 | International Business Machines Corporation | Metal-insulator-metal capacitor |
| US5969422A (en) * | 1997-05-15 | 1999-10-19 | Advanced Micro Devices, Inc. | Plated copper interconnect structure |
| US6025226A (en) * | 1998-01-15 | 2000-02-15 | International Business Machines Corporation | Method of forming a capacitor and a capacitor formed using the method |
| US5946567A (en) * | 1998-03-20 | 1999-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for making metal capacitors for deep submicrometer processes for semiconductor integrated circuits |
| US6016000A (en) * | 1998-04-22 | 2000-01-18 | Cvc, Inc. | Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics |
-
2000
- 2000-03-01 EP EP00104264A patent/EP1130654A1/de not_active Withdrawn
-
2001
- 2001-02-19 WO PCT/EP2001/001853 patent/WO2001065610A1/de not_active Application Discontinuation
- 2001-02-19 KR KR1020027011177A patent/KR20020077923A/ko not_active Application Discontinuation
- 2001-02-19 JP JP2001564400A patent/JP2003526211A/ja not_active Abandoned
- 2001-02-19 EP EP01919307A patent/EP1264351A1/de not_active Withdrawn
- 2001-02-19 CN CNB018059805A patent/CN1194418C/zh not_active Expired - Fee Related
- 2001-03-15 TW TW090106055A patent/TW504832B/zh not_active IP Right Cessation
-
2002
- 2002-09-03 US US10/237,230 patent/US20030040161A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP1264351A1 (de) | 2002-12-11 |
| US20030040161A1 (en) | 2003-02-27 |
| CN1408126A (zh) | 2003-04-02 |
| JP2003526211A (ja) | 2003-09-02 |
| EP1130654A1 (de) | 2001-09-05 |
| KR20020077923A (ko) | 2002-10-14 |
| WO2001065610A1 (de) | 2001-09-07 |
| CN1194418C (zh) | 2005-03-23 |
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