CN1398000A - 单片ic封装 - Google Patents

单片ic封装 Download PDF

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CN1398000A
CN1398000A CN02101714A CN02101714A CN1398000A CN 1398000 A CN1398000 A CN 1398000A CN 02101714 A CN02101714 A CN 02101714A CN 02101714 A CN02101714 A CN 02101714A CN 1398000 A CN1398000 A CN 1398000A
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monolithic
encapsulation
wiring
esd
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寺田幸弘
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Mitsumi Electric Co Ltd
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Mitsumi Electric Co Ltd
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Abstract

本发明涉及具有保护单片IC免遭静电放电破坏的保护装置的单片IC封装，可以以简单的结构实现提高抗ESD量及抗ESD电压。在单片IC封装中具有单片IC11，封装单片IC11等的树脂封装13，设置在该树脂封装13中，同时通过布线18、19等同单片IC11电气连接的突起以及保护单片IC11免遭静电放电(ESD)破坏的保护装置，其结构是：通过用高阻抗材料形成突起而得到高阻抗突起14，使用该高阻抗突起14作为保护装置。

Description

单片IC封装
技术领域
本发明涉及单片IC封装，尤其涉及具有对单片IC进行静电放电保护的保护装置的单片IC封装。
背景技术
近年来，内设单片IC的单片IC封装(以下简称IC封装)的高密度及小型化正日新月异地发展。因此，导致使IC封装的尺寸接近IC芯片尺寸的所谓CSP(芯片尺寸封装)等小型封装被开发并被使用。
至今，这些小型封装中，作为构成同外部连接用端子的突起及插入物的内部布线材料，通常使用铜(Cu)等低阻抗金属。尤其是作为单片IC使用高频对应IC或大功率IC时，通过将低阻抗金属材料用作外部连接用端子材料及内部布线材料有利于实现信号速度的高速化及降低传输损失。
然而，就作为如上所述的外部连接端子材料及内部布线材料使用低阻抗金属材料的IC封装(以下，将这种IC封装称为低阻抗封装)而言，存在静电放电问题。
即，低阻抗封装的制造工序或者组装工序中，带静电的操作人员或处理机械同低阻抗封装的外部连接端子(突起或引线)接触时，存在由于所带静电的放电，单片IC有遭静电损坏的危险这类问题。
作为防止这种ESD的措施，现有的这种低阻抗封装采用的结构是将保护单片IC免遭ESD破坏的保护电路(为提高抗ESD量及抗ESD电压的电路)设置在单片IC内。
然而，采用将保护电路设置在单片IC内的结构，单片IC必大型化，与之相应存在低阻抗封装也大型化的问题。另外，就在经薄膜形成工序及超细加工工序而形成的单片IC中设置保护电路而言，由于单片IC的设计及制造工序均复杂化，还存在单片IC的制造成本提高的问题。
发明内容
本发明鉴于存在如上所述的问题，其目的在于提供一种单片IC封装，它能以简单的结构实现提高抗ESD量和抗ESD电压。
本发明为了实现上述任务，采用了下述各种技术方案。
本发明的第一技术方案是，在单片IC封装中具有以下各部分：单片IC，容纳该单片IC的封装，设置于该封装中的同时，以布线同上述单片IC实现电连接的外部连接端子，保护上述单片IC免遭静电放电破坏的保护装置，其结构特征是；将上述连接端子用作上述保护装置。
根据上述发明，可通过将外部端子用作保护装置的结构，实现以简单的结构提高抗SED量及抗SED电压，从而可防止静电对单片IC及布线的破坏。
另外，本发明的第二技术方案是在上述第一方案的单片IC封装中，其特征是：上述外部连接端子是其阻抗值为10Ω---100KΩ的突起或引线。
根据上述发明，仅仅通过将作为外部接线端子的突起或引线的阻抗值设定在10Ω---100KΩ的范围内，可实现抗ESD量及抗ESD电压的提高。
本发明的第三技术是在单片IC封装中具有以下各部分：单片IC，容纳该单片IC的封装，设置在该封装的同时，以布线同上述单片IC实现电连接的外部连接端子，保护上述单片IC免遭静电放电破坏的保护装置，其特征是：其结构是将上述布线用作上述保护装置。
根据上述发明，通过采用布线作为保护装置的结构，可以简单的结构实现抗ESD量及抗ESD电压的提高，从而可防止单片IC及布线被静电破坏。
另外，本发明的第四技术方案是在上述第三技术方案的单片IC的封装中，其特征是：上述布线是阻抗为10Ω---100KΩ焊接线或布线图布线。
根据上述发明，仅仅通过将作为布线的焊接线或布线图布线的阻抗值设定为10Ω---100KΩ，就可实现提高抗ESD量及抗ESD电压。
附图说明
图1是为说明本发明的第一实施例的IC封装的示意图，
(A)是剖面图，(B)是将树脂封装去除后状态的俯视图，(C)是仰视图。
图2是关于本发明的IC封装由电极焊片至突起的等值电路图。
图3是为说明第一实施例的变型的IC封装的示意图。
(A)是剖面图，(B)是将树脂封装去除后状态的俯视图，(C)是仰视图。
图4是为说明本发明的第二施例的IC封装的示意图，
(A)是剖面图，(B)是将树脂封装去除后状态的俯视图，(C)是仰视图。
图5是为说明本发明的第二施例的变型的IC封装的示意图，
(A)是剖面图，(B)是将树脂封装去除后状态的俯视图，(C)是仰视图。
其中，10A----10D，IC封装，
  1112131415   单片IC插入物树脂封装高阻抗突起电极焊片   1617181920   导线焊点布线通孔低阻抗突起
具体实施方式
下面同附图一起说明本发明的实施方式。
IC封装10A大致由单片IC11，插入物12，树脂封装13及高阻抗突起14等构成。另外，在本实施例中，作为IC封装10A举例说明了BGA型(球型能头陈列)的封装，然而适用于本发明者不限于BGA，其它的如CSP等IC封装也可广泛适用。
单片IC11是经薄膜形成工序及超细加工工序等形成的，在一个IC芯片内是由有源元件和无源元件组成的许多电路元件组合成一体或构成的，在这一点上单片IC同将不能与IC芯片一起形成在IC芯片上的电容等有源零件组装在基板上构成的混合IC的结构是不同的。
另外，在本实施例中所使用的单片IC11中，不设置防止由于ESD(静电放电)而遭静电破坏的保护电路(提高抗ESD量及抗ESD电压的电路)。或者，即使设置保护电路，与现有技术相比，保护电路在单片IC11中所占的比例也能非常小。(约为现有技术的1/2以下左右)。
插入物12是电路的基板，在其表面放置了单片IC11同时，在其背面设置了作为外部连接端子的高阻抗突起14。在插入物的表面上，如图1(B)所示，将焊点17及布线18做成一体。
焊点17通过导线16同单片IC11的电极焊片15进行电连接。布线18的一端同该焊点17连接。另外，布线18的另一端同通孔19连接。
该通孔19做成使插入物12正反两面贯通的形式。其内部充填如铜等导电金属。而且，在该通孔中的下部设置高阻抗突起14。
另外，在本实施例中，在通孔中的正下方设置高阻抗突起14，而通过在插入物12的背面形成布线，可以形成通孔19的形成位置和高阻抗突起14的设置位置不同的结构。
树脂封装13做成使其覆盖上述单片IC11，导线16，焊点17及布线18等。这样，上述后各结构单元11、16、17、18均用树脂封装13保护。该树脂封装13为例如环氧树脂，可用模压法形成。
此处，需注意从IC11至高阻抗突起14之间的电连接线路。图2是表示从单片IC至高阻抗突起14的电连接线路的等值电路图。
如同图所示，在从单片IC11的电极焊片15至高阻抗突起14之间，连接有导线16，布线18和通孔19。现在，将导线16的阻抗设为Rw(Ω)，将布线18和通孔19的合成阻抗设为RL，而将高阻抗突起14的阻抗设为RB。
导线16的阻抗RW通常约为0.1Ω左右。而布线18和通孔19的合成阻抗RL通常也约为0.1Ω左右。与此相反，有关本实施例的IC封装10A中，高阻抗突起14的阻抗RB则设定为10Ω----100KΩ的高阻抗。
这样，作为将突起的阻抗值提高的高阻抗突起14可以通过适当选择高阻抗突起14的材质很容易地进行。而至今一般使用的突起的阻抗值则约为0.1Ω左右。如上所述，通过将高阻抗突起14的阻抗值RB做成高阻抗，则可将高阻抗突起14用作保护单片IC11免遭ESD破坏的保护装置(使抗ESD量及抗ESD电压提高的电路)。
现在假想在单片IC封装10A的制造工序或组装工序中。带静电的操作者或处理机器(以下称为带电物)同IC封装10A的高阻抗突起14接触时的情况。这时，高阻抗突起14如上所述由于具有高阻抗，即使带电物同高阻抗突起14接触而产生ESD，通过将静电的能量在高阻抗突起14中转换为热能(焦耳热)等而消耗。因此，即使带电物同高阻抗突起14接触而产生ESD，也可以防止单片IC11，导线16，布线18及通孔19发生损伤。这样，在有关本实施例的IC封装10A中，高阻抗突起14具有作为保护单片IC11免遭ESD破坏的保护装置的功能。即，将高阻抗突起14(外部连接端子)和保护装置做成了一体。
通过这样的结构，以简单的结构就能实现提高抗ESD量及抗ESD电压，从而可防止单片IC11及各种布线16、18、19免遭ESD破坏。另外，由于未在单片IC中设置提高抗ESD量及抗ESD电压的电路，可实现单片IC11的小型化，从而可实现IC封装10A的小型化。
图3表示的是上述实施例1的IC封装10A的变型例IC封装10B。另外，在图3中，对于同图1所示的结构相同，使用相同标号的部分的说明予以省略。
有关实施例1的IC封装10A表示其结构做成全部突起(实施例中为6个)均为高阻抗突起14。然而，根据单片IC11的规格的不同，则不必全部电极焊片15都采用防ESD措施。
因此，在本变型例中，如图3(C)所示，将必须采用防ESD措施的电极焊片15所连接的二个突起做成高阻抗突起14(图中，用斑点所示)，而其余的4个突起均做成同现有的相同的阻抗值约为0.1Ω左右的突起20(以下，称为低阻抗突起)。这样，没有必要将在IC封装中所设置的全部突起均设置成高阻抗突起14，也可以仅对那些需要采用防静电措施者设置高阻抗突起14。
另外，对于上述实施例1及本变型例而言，已对用作外部接线端子的高阻抗突起14，20予以说明，然而，本发明对于使用引线作为外部接线端子的IC封装(例如，DIP、QFP等封装)也都是能使用的。
接着对本发明的第二实施例予以说明。
图4是表示作为第二实施例的IC封装10C的示意图。图4(A)是在便于说明的最佳位置剖切IC封装10C的剖面图，图4(B)是去除树脂封装13时的俯视图，图4(C)是IC封装10C的仰视图。另外在图4中，在于与所示图1的实施例1的IC封装10A结构相同，使用相同标号的部分的说明予以省略。
在上述实施例1的IC封装10A中，为了提高抗ESD量及抗ESD电压而使单片IC11等免遭ESD破坏，将作为外部界限端子的突起做成高阻抗突起14。
与此相对，在本实施例的IC封装中，是将连接焊点17和通孔19的布线21的阻抗RL做成10Ω的----100KΩ高阻抗(参照图2)，从而将它作为保护单片IC免遭ESD破坏的保护装置(提高抗ESD量及抗ESD电压的电路)。
这样，提高布线的阻抗值使其成为高阻抗布线21，可以通过适当选择高阻抗布线21的材质很容易地实现。另外，在将焊点17同高阻抗布线21做成一体的情况下，焊点17也同高阻抗布线21一样可用高阻抗材料形成。进而，通孔19也可用高阻抗材料充填。这时，除了高阻抗布线21之外，用高阻抗材料形成的焊点17及通孔19也具有保护单片IC11免遭ESD破坏的保护装置的功能。
这样，在本实施例的IC封装10C中，将高阻抗布线21和保护装置做成一体，将高阻抗布线21做成保护单片IC11免遭ESD[哦坏的结构，通过采用这样的结构，以简单的结构就能实现提高抗ESD量及抗ESD电压。从而可防止单片IC11等免遭ESD破坏。
另外，即使在本实施例中，由于不在单片IC11中设置能提高其抗ESD量及抗ESD电压的电路，可实现单片IC11的小型化，从而可实现IC封装10C的小型化。
图5表示的是上述实施例2的IC封装10C的变型例IC封装10D。另外在图5中，对于同图4所示的结构相同的，使用相同标号的部分的说明予以省略。
第二实施例的IC封装10C表示将全部布线(本实施例中为6条)均做成高阻抗布线21的结构。然而，根据单片IC的规格的不同，在全部高阻抗布线21中也有不必采用防ESD措施者。
因此，在本变型例中，如图5(B)所示，将必须采用防ESD措施的电极焊片1 5连接的3条布线做成高阻抗布线21(图中，用斑点表示)，其余3条布线做成通常的阻抗值约为0.1Ω左右的布线18，这样，没有必要将在IC封装中所设置的全部布线都设置成高阻抗布线21，也可以仅将必须采用防ESD措施的布线设置成高阻抗布线21。
进而在本实施例中，也可以对同高阻抗布线21连接的突起采用高阻抗突起14的结构。这样，高阻抗突起14和高阻抗布线21既可以做成两者同时设置的结构，也可以做成有选择地设置一种的结构。
另外，在上述实施例1及实施例2中，将保护电路做成同本来就设置在IC封装中的结构单元的突起或布线作为一体的结构。然而，将该保护电路作为芯片阻抗等另一零件，还要像混合IC那样考虑在插入物上设置的结构。但是，在做成这种结构情况下，也不希望增加零件个数，不希望各外部接线端子上产生设置芯片阻抗等的需要，不希望使IC封装大型化从而使制造成本提高。
使用如上所述的本发明，由于可以简单的结构实现提高抗ESD量及抗ESD电压，可防止单片IC及布线免遭静电破坏，从而可提高单片IC封装的可靠性。

Claims (4)

1.一种单片IC封装，在该封装中，具有单片IC，封装该单片IC的封装，设置在该封装中，同时通过布线同上述单片IC实现电连接的外部接线端子，保护上述单片IC免遭静电放电破坏的保护装置，其特征在于：其结构是使用上述外部接线端子作为上述保护装置。
2.根据权利要求1记载的一种单片IC封装，其特征在于：在上述单片IC封装中，上述外部接线端子是其阻抗值为10Ω----100KΩ的突起或引线。
3.一种单片IC封装，在该封装中，具有单片IC，封装单片IC的封装，设置在该封装中，同时通过布线同上述单片IC实现电连接的外部接线端子，保护上述单片IC免遭静电破坏的保护装置，其特征在于：其结构是使用上述布线作为上述保护装置。
4.根据权利要求3记载的一种单片IC封装，其特征在于：在上述单片IC封装中，上述布线是其阻抗值为10Ω----100KΩ的焊接线或布线图布线。
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