CN1354512A - Semiconductor package with heat dissipation structure - Google Patents
Semiconductor package with heat dissipation structure Download PDFInfo
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- CN1354512A CN1354512A CN 00132439 CN00132439A CN1354512A CN 1354512 A CN1354512 A CN 1354512A CN 00132439 CN00132439 CN 00132439 CN 00132439 A CN00132439 A CN 00132439A CN 1354512 A CN1354512 A CN 1354512A
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- semiconductor chip
- semiconductor package
- semiconductor
- heat sink
- substrate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 230000017525 heat dissipation Effects 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229920005989 resin Polymers 0.000 claims abstract description 19
- 239000011347 resin Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000004806 packaging method and process Methods 0.000 claims abstract description 8
- 238000000465 moulding Methods 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 239000008393 encapsulating agent Substances 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
一种具散热结构的半导体封装件,包括一黏接至一基板上的半导体芯片,该半导体芯片具有一作用表面,以供多个的焊线焊接其上而将该半导体芯片与基板电性连接;该作用表面上是藉一胶黏层黏接有一由热膨胀系个与该半导体芯片相近的材料制成的盖片,以降低热应力对半导体芯片的影响而有效避免半导体芯片裂损的发生,且藉以提升半导体芯片的作用表面所产生热量的逸散效率,及避免外界入侵的水气凝聚于该半导体芯片的作用表面上;该基板上并接设有一散热片,该散热片具有一顶面以外露出用以包覆该半导体芯片与盖片的封装胶体,且该散热片与该盖片的顶面间相隔一适当距离,以避免散热片触压该半导体芯片,但同时能有效缩减位于散热片与半导体芯片间的封装树脂的厚度,而可提升散热效率。
A semiconductor package with a heat dissipation structure comprises a semiconductor chip bonded to a substrate, the semiconductor chip having an active surface for a plurality of welding wires to be welded thereon so as to electrically connect the semiconductor chip to the substrate; a cover plate made of a material having a thermal expansion coefficient similar to that of the semiconductor chip is bonded to the active surface by an adhesive layer so as to reduce the influence of thermal stress on the semiconductor chip and effectively avoid the occurrence of cracking of the semiconductor chip, thereby improving the efficiency of heat dissipation generated by the active surface of the semiconductor chip and preventing the moisture invading from the outside from condensing on the active surface of the semiconductor chip; a heat sink is connected to the substrate, the heat sink having a top surface exposed to cover the packaging colloid of the semiconductor chip and the cover plate, and an appropriate distance is spaced between the heat sink and the top surface of the cover plate so as to avoid the heat sink from contacting the semiconductor chip, but at the same time effectively reducing the thickness of the packaging resin between the heat sink and the semiconductor chip, thereby improving the heat dissipation efficiency.
Description
The invention relates to a kind of semiconductor package part, refer to that especially a kind of end face with fin and this fin exposes outside packing colloid to promote the semiconductor package part of radiating efficiency.
Ball bar array (BGA) semiconductor package part (Ball Grid Array SemiconductorPackage) thus the main flow that becomes encapsulating products, be the demand that it can provide the semiconductor chip of the fully input of an amount/go out connecting end (I/O Connections) to meet highdensity electronic building brick of tool (ElectronicComponents) and electronic circuit (Electrical Circuits).Yet the electronic building brick on the semiconductor chip and the density of electronic circuit are high more, and the heat that is produced during its running is just many more; But, will influence performance and useful life to semiconductor chip if not with the effective loss of the heat that semiconductor chip produced.Again and, traditionally, the high-performance semiconductor chips of BGA semiconductor package part is coated by packing colloid (Encapsulant orResin Body), and the thermal conductance that constitutes the potting resin of packing colloid is that a K only is about 0.8w/m.K, heat conductivity is very poor, so the heat that the action face (Active Surface) that often makes semiconductor chip be laid with electronic building brick and electronic circuit go up to produce effectively the transmission of mat packing colloid and loss to atmosphere.
In addition, the material coefficient of thermal expansion of semiconductor chip is (Coefficient of a ThermalExpansion, CTE) be about 3ppm/ ℃, the CTE of potting resin that generally forms packing colloid is then up to about 20ppm/ ℃, so after packing colloid coats semiconductor chip, in baking operation (Curing) in order to the cure package colloid, the semiconductor package part weldering is located on the printed circuit board (PCB)? the bigger amplitude of expanding with heat and contract with cold of packing colloid tends to semiconductor chip is produced suitable thermal stress (ThermalStress) effect under weldering operation (Solder Reflow) and the significantly variations in temperature of semiconductor package part in temperature cycles (Temperature Cycle) reliability demonstration operation, and easily cause semiconductor chip rhegma (Crack), the packing colloid that coats semiconductor chip is healed thick or semiconductor chip is thinner or very little heals when big, and the thermal stress effects that semiconductor chip is produced is more remarkable.It is the shortcoming that on making, has yield effectively to promote all the time with, the known semiconductor package part of this kind.
For solving the deficiency of known BGA semiconductor package part on thermal diffusivity, have then in the BGA semiconductor package part the gelled structure of installing in response to and give birth to.This kind is coated on mode in the packing colloid with fin, though help the lifting of radiating efficiency, the heat transferred that thought semiconductor chip action face is produced is to the path of atmosphere, and still having sizable part is the not extremely gratifying degree of Cui of process thermal diffusivity.
At the shortcoming of the BGA semiconductor package part of above-mentioned tool fin, United States Patent (USP) the 5th, 216, the end face that proposes a kind of fin for No. 278 then exposes outside the semiconductor package part of packing colloid.As shown in Figure 5, the fin 10 of this kind semiconductor package part 1 be mat one thermal conductivity gluing layer 11 gluing to the end face of chip 12, and the upper surface 100 of this fin 10 is the packing colloids 13 that expose outside in order to coating chip 12.This kind structure makes heat radiation approach (Thermally Conductive Path) loss that heat that chip 12 produced can be directly be made of this thermal conductivity gluing layer 11 and fin 10 to atmosphere, the not packing colloid 13 of Cui of thermal diffusivity that needn't stimulate the menstrual flow is so radiating efficiency is effectively promoted.Yet, fin 10 is directly to be adhered on the end face of chip 12, when there are tolerance on the thickness in fin 10 and chip 12, when carrying out the matched moulds injecting glue of molding operation (Molding), tend to make fin 10 to be subjected to the pressure of encapsulating mould (not icon), this pressure just is passed on the chip 12 via fin 10, causes chip 12 thereby rhegma (Crack), just has the problem that acceptance rate can't promote so plant fin gluing to the semiconductor package part on the chip on making; Again and, as previously mentioned, the material coefficient of thermal expansion of semiconductor chip is to be about 3ppm/ ℃, so, generally the thermal expansion with the metal fin 10 of copper is individual then up to about 18ppm/ ℃, in the temperature cycles of different processing procedures, fin 10 promptly can cause the rhegma of chip 12 to chip 12 generation significant thermal stress effects, so similarly influence the acceptance rate to manufactured goods.
The problems that produced for avoiding fin directly to be adhered on the chip surface, the semiconductor package part of a kind of tool fin of proposition in No. 87116851 patent application case in Taiwan that the applicant of this case is convenient to propose on October 12nd, 1998.As shown in Figure 6, the structural similarity of the fin of this kind semiconductor package part 2 20 and aforesaid United States Patent (USP) all is that the end face 200 with fin 20 exposes outside packing colloid 23, make end face 200 directly the contact atmosphere to promote the efficient of fin 20 loss heats; Simultaneously, the bottom surface 201 of this fin 20 is and chip 22 distance of being separated by, contact chip 22 to avoid fin 20 can press when the matched moulds injecting glue, yet 22 of the bottom surface 201 of this fin 20 and chips are to be filled with the potting resin that forms packing colloid 23, the chip that makes aforementioned known semiconductor packages part is that the shortcoming that the packing colloid coating is produced still can occur in this kind semiconductor package part 2, be that the heat that chip 22 produces still must must be passed to fin 20 via packing colloid 23, to the radiating efficiency of fin 20 be affected, and the distance H that normally is positioned at 20 of chip 22 and fin is big more, the thermal resistance value θ j-a that potting resin produces is big more, θ j-a is big more, and the chip surface temperature (Tj) that then can cause is high more, and the surface temperature of chip is got over Gao Zeyue and is unfavorable for keeping of chip performance and useful life; Again and, packing colloid 23 is direct coating chip 22 still, the thermal stress effects that makes chip 22 be subjected to is still remarkable, and chip 22 impaired possibilities can't effectively be reduced.
The object of the present invention is to provide a kind of at glutinous sheet on the semiconductor chip and make cover plate and end face exposes outside the semiconductor package part that maintains a suitable distance between the fin of packing colloid, with engaging of this cover plate of mat and semiconductor chip, avoid aqueous vapor on the action face of semiconductor chip, to condense, and can effectively reduce the influence that the thermal stress between material produces semiconductor chip, and avoid semiconductor chip that rhegma takes place in temperature cycles, to promote the acceptance rate of manufactured goods, and and then reduction heat radiation approach in the shared part of packing colloid, with effective lifting radiating efficiency, simultaneously, fin does not contact with semiconductor chip, does not touch semiconductor chip and makes its impaired worry so there is pressure.
Semiconductor package part provided by the present invention comprises: a substrate has an end face and an opposed bottom surface; Semiconductor chip on the one glutinous end face of being located at this substrate, it has an action face and one and the end face of the substrate non-action face of joining; The first a plurality of conductive components is in order to electrically connect this semiconductor chip and substrate; The cover plate of one gluing to the action face of this semiconductor chip, it is a made person of material who is comparable to this semiconductor chip for thermal expansion; One is arranged in the fin on the end face of this substrate, and it has an end face and an opposed bottom surface, and is formed with a gap between the bottom surface of this fin and this cover plate; A plurality of second conductive components that plant on this substrate bottom surface are in order to this semiconductor chip and extraneous electrically connect; And one in order to coating the packing colloid of this semiconductor chip, cover plate, first conductive component and fin, but make the end face of this fin expose outside this packing colloid.
In another embodiment of the present invention, this semiconductor chip is that mat solder bump (SloderBump) is to cover action face and the substrate electric connection of crystalline substance (Flip Chip) mode with semiconductor chip, so this cover plate is that gluing is on the non-action face of this semiconductor chip.
The material that is applicable to this cover plate is a close person for the thermal expansion with semiconductor chip, there is no specific limited, only still can effectively conduct the heat person who is come by the semiconductor chip that joins with this cover plate with semi-conducting material or metal material etc. is advisable, so be bad wafer (Wafer) person of being cut down who eliminates after tested than Cui person, so, it is individual that this cover plate promptly has identical thermal expansion with semiconductor chip, and the action face to semiconductor chip produces minimum thermal stress in temperature cycles.
Gap between this cover plate and fin is unsuitable excessive, to avoid filling packing colloid thickness wherein excessive and influence radiating efficiency, but it is also unsuitable too small, when avoiding molding operation to carry out, the potting resin that injects can diminish because of resistance becomes big flow velocity in this gap, cause gas hole (Void) be formed at this cover plate and fin between; And in the packing colloid if there is the gas hole to form, in temperature cycles, trust reliability demonstration test or actual operation gas explosion (Popcorn) takes place easily, cause manufactured goods to have the problem of reliability, and the formation in gas hole also can increase thermal resistance (because of the heat conductivity of gas than packing colloid for poor), and can reduce that heat radiation is imitated thereby, influence under the considering of radiating efficiency avoiding generation of gas hole and excesssive gap, the size in this gap should be between 0.03mm to 0.45mm, and with between 0.05mm to 0.30mm for more suitable.
Simultaneously, for further dwindling the gap with the whole height after reducing semiconductor package part and making but be unlikely under the situation of the generation that causes the gas hole, can when being formed with on the end face of cover plate, flow a plurality of grooves that flow direction is offered by the potting resin mould along injecting glue, or be formed with a plurality of protruding grains, to be formed with the forward runner of water conservancy diversion potting resin mould stream by protruding intergranular; In like manner, also can be formed with on the position above the bottom surface of this fin is positioned at this cover plate and carry over a plurality of grooves that potting resin mould stream flow direction is offered, or the runner that becomes by a plurality of protruding particle shapes.Simultaneously, the end face of the bottom surface of this fin and the cover plate runner that can be formed with aforesaid groove simultaneously or constitute by protruding grain.
Below cooperate appended graphic characteristics of the present invention and the effect of further describing with specific embodiment now.
Fig. 1 is the cutaway view of the semiconductor package part of first embodiment of the invention;
Fig. 2 is the cutaway view of the semiconductor package part of second embodiment of the invention;
Fig. 3 A is the stereogram that the part of the semiconductor package part of third embodiment of the invention is cut open;
Fig. 3 B is the cutaway view of 3A figure along the 3B-3B line;
Fig. 4 is the stereogram that the part of the semiconductor package part of fourth embodiment of the invention is cut open;
Fig. 5 is the cutaway view of known semiconductor packages part; And
Fig. 6 is the cutaway view of another known semiconductor packages part.Element numbers 1,2,3,4,5,6 semiconductor package parts 10,20,34,54,64 fin 11 thermal conductivity gluing layers 12,22 chip 13,23,35 packing colloids 100 upper surfaces 200,300,340a end face 201,301,340b bottom surface 630 protruding H of 30,40 substrates, 31,41,411 semiconductor chip 32 gold threads, 33,43,53,63 cover plate 36 soldered balls, 37,38 adhesive 310,410 action face, 311 non-action face 340 lamellar bodies, 341 spike 42 solder bumps, 530 grooves are apart from the S gap
First embodiment
Figure 1 shows that the cutaway view of the semiconductor package part of first embodiment of the invention.
As shown in the figure, the semiconductor package part 3 of this first embodiment is to comprise a substrate 30, the semiconductor chip 31 of one gluing to this substrate 30, the many gold threads 32 that semiconductor chip 31 are electrically connected to this substrate 30, the cover plate 33 of one gluing to this semiconductor chip 31, connect the fin 34 that places on the substrate 30, and the packing colloid 35 that coats the fin 34 of this semiconductor chip 31, gold thread 32, cover plate 33 and part.
This substrate 30 has one and is laid with a plurality of conductive traces (this is for public technology, former not icon) an end face 300 and a relative bottom surface 301 that also is laid with a plurality of conductive traces (not icon), it also offers a plurality of conduction perforation (Vias, not icon) so that the conductive trace on conductive trace on the end face 300 and the bottom surface 301 electrically connects; Also plant on the bottom surface 301 of this substrate 30 and be connected to a plurality of soldered balls 36, after electrically connecting for this semiconductor chip 31 and substrate 30, this soldered ball 36 of mat is electrically connected to as external devices such as printed circuit board (PCB) (External Device).The material of making usefulness for this substrate 30 can be general epoxy resin, poly-sulfurous ammonia resin, triazine resin etc. or ceramic material, glass material etc., just wherein, again with BT (Bismaleimidetriazine) resin for more suitable.
31 of this semiconductor chips have an action face 310 and a relative non-action face 311 that is laid with a plurality of electronic building bricks and electronic circuit, its promptly be this non-action face 311 of mat with commonly used as adhesives such as elargol 37 gluings to the end face 300 of this substrate 30.
This cover plate 33 is to use the chip (Defective Die) of classifying defective products as so that its thermal expansion is the individual semiconductor chip 31 that is same as, in order to do behind these packing colloid 35 curing moldings, this cover plate 33 can provide the mechanical strength of semiconductor chip 31 than Cui with the combination of semiconductor chip 31, and effectively reduce packing colloid 35 in the variations in temperature of the successive process (thermal stress that in the temperature cycles of Temperature Variation and reliability demonstration (Temperature Cycle) action face 310 of semiconductor chip 31 is produced, so can reduce the generation of semiconductor chip 31 rhegmas, make the acceptance rate of manufactured goods and the impact resistance that reliability has improved and strengthened semiconductor chip 31 for it.This cover plate 33 should be with adhesive 38 gluings of thermal conductance to the action face 310 of semiconductor chip 31, and this adhesive 38 of mat is passed to this cover plate 33 so that the heat that action face 310 is produced gets effectively.The size of this cover plate 33 is less than semiconductor chip 31, to touch the weld pad (not icon) on the action face 310 after avoiding its gluing to this semiconductor chip 31 or to influence to the carrying out of the bonding wire operation of gold thread 32; Right when gold thread be mode with reverse welding (ReverseBondiy) when being welded in 31 of substrate 30 and semiconductor chips, this cover plate 33 can be the same big or small with semiconductor chip 31, or even be slightly larger than semiconductor chip 31.
This fin 34 is by a lamellar body 340 and in order to this lamellar body 340 is supported to 341 constitutors of spike of the height that is positioned at these semiconductor chip 31 tops and does not contact with cover plate 33 and gold thread 32.This lamellar body 340 has an end face 340a and an opposed bottom surface 340b who exposes outside this packing colloid 35, this bottom surface 340b must and the upper surface (not giving label) of the cover plate 33 suitable distance and make 33 formation of fin 34 and cover plate, one gap S of being separated by.The size of this gap S can not be too small and cause packing colloid 35 and be formed with the gas hole in the position of 33 of fin 34 and cover plates, but also needn't be excessive and make packing colloid 35 be arranged in the too high and influence of the thickness at position of gap S to whole radiating efficiency; Thereby gap S should be between the scope of 0.03mm to 0.45mm, and with the scope of 0.05mm to 0.30mm for more suitable.Fin 34 unlikely touching to the situation of cover plate 33, the accumulation because of the thickness deviation of each assembly in the time of can avoiding molding operation causes semiconductor chip 31 pressurized rhegmas, and can significantly reduce the thermal stress that semiconductor chip 31 is born; But because of and 33 of cover plates only separate very small distance, fin 34 still can be effectively with its end face 340a loss that exposes of heat mat of coming by semiconductor chip 31 to atmosphere, and the heat radiation approach that does not have a known semiconductor packages part sizable part is arranged is the not shortcoming of the potting resin of Cui of latus rectum thermal conductance.
Be the lifting of the heat dissipation that proves above-mentioned semiconductor package part 3, now itself and other known person carried out the heat dissipation experiment, it the results are shown in table one to table three.Table one: the packaging part pattern of experimental subjects
Table two: other specification of the packaging part of each pattern
Table three: experimental result (under the heat energy of 6w and still air state, testing)
Second embodiment
| The packaging part specification | 336-pin?BGA |
| Package size (L * W * H) | 27×27×2.33mm |
| Chip size | 7.77×7.77mm 2 |
| Space between solder balls | 1.27mm |
| Substrate thickness | 0.56mm |
| Heat transmission soldered | 36 |
| The copper number of plies of substrate | 4 layers |
| Packaging part | ????Q j-a(℃/w) |
| ??I | ????9.6 |
| ??II | ????9.0 |
| III (the present invention) | ????8.4 |
Figure 2 shows that the cutaway view of the semiconductor package part of the second embodiment of the present invention.As shown in the figure, the structure of the semiconductor package part 4 of this second embodiment roughly is same as aforesaid first embodiment, and it is to be electrically connected on the substrate 40 to cover crystalline substance (Flip Chip) mode that its difference is in this semiconductor chip 41.The action face 410 of this semiconductor chip 41 be down a plurality of solder bump (Solder Bumps) 42 gluings of mat to substrate 40, because the non-action face 411 of this semiconductor chip 41 is to establish for the glutinous of cover plate 43 up, so the size of cover plate 43 can be identical with semiconductor chip 41, and there is not the worry of the electric connection operation that influences 40 of semiconductor chip 41 and substrates.The 3rd embodiment
Fig. 3 A and Fig. 3 B are depicted as stereogram and the cutaway view thereof that the part of the semiconductor package part of third embodiment of the invention is cut open.As shown in the figure, the structure of the semiconductor package part 5 of this second embodiment roughly is same as aforesaid first embodiment, it is to be formed with a plurality of groove 530 that its difference is on the cover plate 53 of this semiconductor package part 5, each groove 530 is that the injecting glue direction that carries over potting resin forms, flow to influence to reduce the potting resin mould, make the probability of effective minimizing gas hole formation into the flow velocity of 53 of fin 54 and cover plates.In like manner, the bottom surface that this kind groove can relatively be located at fin 54 is positioned at the place, top of cover plate 53, also can produce identical effect.The 4th embodiment
Figure 4 shows that the stereogram that the part of the semiconductor package part of fourth embodiment of the invention is cut open.As shown in the figure, the structure of the semiconductor package part 6 of the 4th embodiment roughly is same as aforesaid first embodiment, it is to be formed with the protruding grain 630 that a plurality of one-tenth array way are arranged that its difference is on the cover plate 63 of this semiconductor package part 6, make by protruding intergranular and form the runner that passes through for potting resin mould stream, and making potting resin mould stream when flowing through 63 of fin 64 and cover plates, the unlikely change of its flow velocity causes the formation in gas hole too much.In like manner, the protruding grain of this kind also can be arranged on the bottom surface of fin 64, still can produce identical effect.The above only is specific embodiments of the invention, and other is any not to deviate from the equivalence of being done under spirit of the present invention and the technology and change or modify, and all should still be included within the protection range of this patent.
Claims (16)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB00132439XA CN1174484C (en) | 2000-11-17 | 2000-11-17 | Semiconductor package with heat dissipation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB00132439XA CN1174484C (en) | 2000-11-17 | 2000-11-17 | Semiconductor package with heat dissipation structure |
Publications (2)
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| CN1354512A true CN1354512A (en) | 2002-06-19 |
| CN1174484C CN1174484C (en) | 2004-11-03 |
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| CNB00132439XA Expired - Lifetime CN1174484C (en) | 2000-11-17 | 2000-11-17 | Semiconductor package with heat dissipation structure |
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Cited By (16)
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| CN100369243C (en) * | 2003-08-22 | 2008-02-13 | 矽品精密工业股份有限公司 | Semiconductor package with heat dissipation structure |
| US7605456B2 (en) | 2004-06-03 | 2009-10-20 | Kabushiki Kaisha Toshiba | Inverter unit |
| CN101228627B (en) * | 2005-06-20 | 2010-05-19 | 诺基亚公司 | Electronic module assemblies, portable electronic communication devices and printed circuit boards with heat sinks |
| CN101459147B (en) * | 2007-12-14 | 2011-04-20 | 三星电子株式会社 | Heat radiation fin, encapsulation piece comprising the heat radiation fin and encapsulation method |
| CN102044503A (en) * | 2010-01-27 | 2011-05-04 | 江苏长电科技股份有限公司 | Packaging structure with printed circuit board, chip and upright heat dissipation block with locking hole |
| CN102054798A (en) * | 2010-01-30 | 2011-05-11 | 江苏长电科技股份有限公司 | External heat radiator packaging structure of upright heat radiating block of chip in resin circuit board |
| CN102074525A (en) * | 2010-01-30 | 2011-05-25 | 江苏长电科技股份有限公司 | Upright packaging structure for radiating-block external radiator of printed circuit board chip |
| CN102074522A (en) * | 2010-01-30 | 2011-05-25 | 江苏长电科技股份有限公司 | Package structure with printed circuit boards (PCBs), chip, inverted locking hole, radiating block, convex column and external radiator |
| CN102074526A (en) * | 2010-01-30 | 2011-05-25 | 江苏长电科技股份有限公司 | Encapsulation structure of resin circuit board, positive chip, lock hole, radiating block and external radiator |
| CN102082134A (en) * | 2010-01-29 | 2011-06-01 | 江苏长电科技股份有限公司 | Packaging structure of base island-embedded chip upright heat dissipation block external radiator |
| CN102088006A (en) * | 2010-01-29 | 2011-06-08 | 江苏长电科技股份有限公司 | Packaging structure with resin circuit board, chip and inverted radiating block with locking hole |
| CN101752327B (en) * | 2008-12-01 | 2011-11-16 | 矽品精密工业股份有限公司 | Semiconductor package with heat dissipation structure |
| CN102272920B (en) * | 2008-12-12 | 2014-05-21 | 费查尔德半导体有限公司 | Semiconductor die package including low stress configuration |
| CN103887263A (en) * | 2012-12-21 | 2014-06-25 | 宏启胜精密电子(秦皇岛)有限公司 | Package structure and manufacturing method thereof |
| CN111384000A (en) * | 2018-12-29 | 2020-07-07 | 中兴通讯股份有限公司 | Chip package |
| CN111584346A (en) * | 2020-05-28 | 2020-08-25 | 浙江大学 | GaN device with heat sink structure and preparation method thereof |
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| CN100362639C (en) * | 2005-02-07 | 2008-01-16 | 矽品精密工业股份有限公司 | Semiconductor package of stack chip and manufacturing method thereof |
| CN100466210C (en) * | 2005-07-15 | 2009-03-04 | 矽品精密工业股份有限公司 | Heat dissipation type semiconductor package and manufacturing method thereof |
| CN102097398A (en) * | 2010-01-28 | 2011-06-15 | 江苏长电科技股份有限公司 | Packaging structure with resin circuit boards, normally assembled chip and radiating block |
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2000
- 2000-11-17 CN CNB00132439XA patent/CN1174484C/en not_active Expired - Lifetime
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100369243C (en) * | 2003-08-22 | 2008-02-13 | 矽品精密工业股份有限公司 | Semiconductor package with heat dissipation structure |
| US7605456B2 (en) | 2004-06-03 | 2009-10-20 | Kabushiki Kaisha Toshiba | Inverter unit |
| CN1961474B (en) * | 2004-06-03 | 2010-05-05 | 株式会社东芝 | Convertor device |
| CN101228627B (en) * | 2005-06-20 | 2010-05-19 | 诺基亚公司 | Electronic module assemblies, portable electronic communication devices and printed circuit boards with heat sinks |
| CN101459147B (en) * | 2007-12-14 | 2011-04-20 | 三星电子株式会社 | Heat radiation fin, encapsulation piece comprising the heat radiation fin and encapsulation method |
| CN101752327B (en) * | 2008-12-01 | 2011-11-16 | 矽品精密工业股份有限公司 | Semiconductor package with heat dissipation structure |
| CN102272920B (en) * | 2008-12-12 | 2014-05-21 | 费查尔德半导体有限公司 | Semiconductor die package including low stress configuration |
| CN102044503A (en) * | 2010-01-27 | 2011-05-04 | 江苏长电科技股份有限公司 | Packaging structure with printed circuit board, chip and upright heat dissipation block with locking hole |
| CN102082134A (en) * | 2010-01-29 | 2011-06-01 | 江苏长电科技股份有限公司 | Packaging structure of base island-embedded chip upright heat dissipation block external radiator |
| CN102088006A (en) * | 2010-01-29 | 2011-06-08 | 江苏长电科技股份有限公司 | Packaging structure with resin circuit board, chip and inverted radiating block with locking hole |
| CN102054798A (en) * | 2010-01-30 | 2011-05-11 | 江苏长电科技股份有限公司 | External heat radiator packaging structure of upright heat radiating block of chip in resin circuit board |
| CN102074525A (en) * | 2010-01-30 | 2011-05-25 | 江苏长电科技股份有限公司 | Upright packaging structure for radiating-block external radiator of printed circuit board chip |
| CN102074522A (en) * | 2010-01-30 | 2011-05-25 | 江苏长电科技股份有限公司 | Package structure with printed circuit boards (PCBs), chip, inverted locking hole, radiating block, convex column and external radiator |
| CN102074526A (en) * | 2010-01-30 | 2011-05-25 | 江苏长电科技股份有限公司 | Encapsulation structure of resin circuit board, positive chip, lock hole, radiating block and external radiator |
| CN103887263A (en) * | 2012-12-21 | 2014-06-25 | 宏启胜精密电子(秦皇岛)有限公司 | Package structure and manufacturing method thereof |
| CN103887263B (en) * | 2012-12-21 | 2016-12-28 | 碁鼎科技秦皇岛有限公司 | Encapsulating structure and preparation method thereof |
| CN111384000A (en) * | 2018-12-29 | 2020-07-07 | 中兴通讯股份有限公司 | Chip package |
| CN111584346A (en) * | 2020-05-28 | 2020-08-25 | 浙江大学 | GaN device with heat sink structure and preparation method thereof |
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| CN1174484C (en) | 2004-11-03 |
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