CN100369243C - Semiconductor sealer with radiating structure - Google Patents
Semiconductor sealer with radiating structure Download PDFInfo
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- CN100369243C CN100369243C CNB031558178A CN03155817A CN100369243C CN 100369243 C CN100369243 C CN 100369243C CN B031558178 A CNB031558178 A CN B031558178A CN 03155817 A CN03155817 A CN 03155817A CN 100369243 C CN100369243 C CN 100369243C
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- fin
- semiconductor package
- package part
- radiator structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The present invention relates to a semiconductor package piece with a heat radiating structure, which comprises a basal plate provided with a first surface and an opposite second surface, at least one chip electrically connected with the basal plate, a plurality of solder balls connected to the second surface of the basal plate, and a heat radiation structure comprising a first heat radiating fin provided with at least one first positioning part and at least one second heat radiating fin provided with at least one second positioning part and an engraving part, wherein the second heat radiating fin is connected to the surface where the basal plate and the chip are connected, the first heat radiating fin is connected to the second positioning part of the second heat radiating fin by the first positioning part, and the chip is covered in the space formed by being surrounded by the first heat radiating fin, the engraving part of the second heat radiating fin and the basal plate. Accordingly, the semiconductor package piece having the advantages of low cost, thin property and good heat radiation is formed by the heat radiating structure formed by stacking the heat radiating fins.
Description
Technical field
The invention relates to a kind of semiconductor package part, particularly about a kind of semiconductor package part that reduces cost with the packaging part height with radiator structure with radiator structure.
Background technology
Flip chip ball grid array (Flip-Chip Ball Grid Array, FCBGA) semiconductor package part is a kind of encapsulating structure that has flip-chip and ball grid array simultaneously, Figure 17 is exactly existing Flip-Chip Using part cutaway view with fin, as shown in the figure, this packaging part is that the action face (Active Surface) that makes at least one chip can be electrically connected on the surface of substrate (Substrate) by a plurality of solder joints (Solder Bumps), and plants a plurality of soldered balls (Solder Ball) as I/O (I/O) end on another surface of this substrate; This encapsulating structure can make volume significantly reduce, and also deducts the design of existing bonding wire (Wire) simultaneously, can reduce impedance, promote electrical quality, avoids the decay of signal in transmission course, has therefore become the main flow encapsulation technology of chip and electronic building brick.
Because the advantageous characteristic of this flip chip ball grid array encapsulation, make in its multicore chip package that is used for high integration (Integration) more, with volume and the computing demand that satisfies this electronic building brick, but this electron-like assembly is because its high-frequency computation performance, make it be higher than general packaging part at the heat that running produces, therefore, the quality of its radiating effect just becomes the key that influences this class packaging part quality; For existing flip chip ball grid array packaging part, it is on the non-action face (Non-active Surface) that directly fin (Heat Sink) is covered at chip, need not transmit heat by the relatively poor packing colloid (Encapsulant) of thermal conductivity, thereby form the direct heat dissipation path in chip-adhesive-fin-external world, compare with other radiating mode, it has heat radiation function preferably.
Fin for this class encapsulating structure, prior art as shown in figure 18, directly be bonded on the substrate 62 with the support portion 60b of mucilage materials 61 with fin 60, and be bonded in the par 60a of fin 60 on the non-action face 64a of chip 64 with heat-conducting glue 63, heat by the par 60a dissipation chip 64 that exposes, for example United States Patent (USP) the 5th, 311, No. 402, the 5th, 909, No. 474, the 5th, 909, No. 057 or the 5th, 637, No. 920 prior aries such as patent, all disclosed this approximate construction, and develop the mode that other location fin gradually according to its location requirement, for example with bolt or other keeper with the support portion locking of fin on substrate, thereby the adhesive force of enhance heat sheet etc.
Yet, no matter how correlation technique develops, no matter also how it changes the locate mode of fin or how to promote its radiating efficiency, the structural design of the par of this fin and its peripheral branch support part does not but change all the time, this is because in this Flip-Chip Using part, fin is to cover on the substrate with the cover cap form, and the par by fin and its peripheral branch support part are enclosed the space that is installed with of putting out chip are coated wherein, therefore, under this structural limitations, the section shape of this fin must be designed to concave shape as shown in figure 18, and along with the raising of number of chips and integrated level, and appropriateness increases and is installed with the volume in space and the height of packaging part.
Therefore, the spatial design that is installed with of this depression becomes the restriction that this class packaging part is improved gradually, and become packaging part now to height heat radiation, low-cost and small size direction develop-big obstruction, also be that this type of technology has the obstacle that is difficult to cross in future development; Its reason is that this fin all is to make in the mode of forging (Forging), being installed with the space and forming the support portion on this fin that forges and presses out, Figure 18 A for example, square radiating plate 60 shown in Figure 18 B, earlier tabular copper or aluminum are inserted in the die material, in its forging range, apply impulsive force or pressurization, and then forge and press out this square sunk area 65, and can chip 64 be coated in this sunk area 65 connecing when putting substrate 62, this method for making is subject to the operation and the equipment cost of forging machine and forging hammer (ForgingHammer), form the load greatly of one on the output, manufacturing cost is improved along with the variation of heat sink sizes.
In addition, because the forming accuracy of forging hammer is limited, make the thickness proportion (AspectRatio of fin, t/T), as Figure 18 A, has certain upper limit shown in Figure 18 B, the gross thickness T of fin 60 is reduced near the height t that is installed with space 65, present forging method for making only can make thickness proportion t/T maximum be about about 0.5, just the gross thickness T of this fin 60 height t that is installed with space 65 that will be subjected to offer influences, be increased to 1mm if be installed with space 65 required height t, the board-like material of then making fin 60 at least also need have 2mm thick, just can carry out the processing of forging method; Therefore, when owing to connect the quantity of chip 64 thickness put or its storehouse on the substrate 62 and increase, when the height t that is installed with space 65 of fin 60 is increased, the thickness T of this fin 60 obviously also need wait doubly amplifies, make whole package size be difficult to dwindle, do not meet compact development trend, and the fin 60 of progressive additive more is unfavorable for chip 64 heat radiations along with the height increase of chip 64, has a strong impact on the heat dissipation of packaging part.
Packaging part cutaway view as shown in figure 19, when this packaging part adopts the stack architecture of twin-core sheet, compare with the packaging part of single-chip, the thickness of the chip 66 that the integral thickness of this packaging part is set up except increase, fin 60 also increases thickness simultaneously because of sheet material is subject to forging method, causes the integral thickness of packaging part significantly to rise, both increased the cost of fin, radiating efficiency is descended, simultaneously, the also difficult small size development trend that meets electronics industry.
Have again, make fin with forging method, also be subject to the kind of forging hammer and chi in, the size and shape variation of fin is lacked flexibility, be difficult to change as required its moulding and improve area of dissipation, packaging part cutaway view as shown in figure 20, be on the 60a of the par of fin, to set up fin 67 (Fin), to promote fin 60 and extraneous contact area, this design promptly is the design limit because of fin 60, make fin 67 only can be formed on par 60a directly over, and the design in other orientation can't be arranged, and then also cause the significantly increase of overall package part thickness; In addition, this packaging part also may be as shown in figure 21, on substrate 62, set up a passive component 68 (Passive Component) to improve the electrical property efficiency of this packaging part, at this moment, that offers on this fin 60 is installed with space 65 volumes and need slightly strengthens to be installed with passive component 68, yet, owing to be subjected to the restriction of the forging hammer size of forging method, this fin 60 can't change its size and shape arbitrarily according to the layout change on the substrate 62, may make it increase unnecessary zone, and need carry out the batch manufacturing of new size again, pining down on forming configuration and designing.
Simultaneously, this existing method for making is at high temperature to utilize the instantaneous stamping power of forging hammer and the space that is installed with of forging and pressing out fin, therefore, after processing procedure is finished, the spatial edge that is installed with of this fin can stress be concentrated and the generation of residual stress (Residual Stress) is arranged, make the lattice of this copper or aluminum form generation destruction, so, when connecing the packaging part that is equipped with this fin after follow-up reliability test or long-term the use, may be as shown in figure 22, the crack 69 that residual stress causes appears in the intersection at the par of this fin 60a and support portion 60b, and then fracture extension takes place and destroys the structure of this fin.
In addition, the shortcoming of existing heat sink design and its method for making also is not only these, when fin connects when putting on substrate, be to adhere on this substrate by being looped around support portion on every side, this par, and par and support portion are integrated materials, therefore, when packaging part carries out follow-up high temperature process, because thermal coefficient of expansion (the Coefficient ofThermal Expansion of fin and chip, CTE) at a distance of very big, the heat distortion amount of the par of fin will be slightly larger than chip, this moment is because the constraint that is subjected to the support portion on every side of par, to make its thermal strain be difficult to discharge and cause as shown in figure 23 distortion, make 63 of par 60a and chip 64 or heat-conducting glues produce layering 70 and reduction heat dissipation, even cause the layering (figure is mark) of 62 of the support portion 60b of fin 60 and substrates, fin 60 is come off when being shaken.
Hence one can see that, initial radiating requirements for the Flip-Chip Using part, this heat sink design be a suitable solution party really to, yet, along with electronics industry progressively towards trend developments such as high integration, high heat radiation, low-cost and small sizes, this fin is because of the restriction of its structure and method for making, become the major obstacle that further develops, simultaneously, the bottleneck that is limited to existing forging manufacturing technique, if only carry out structural improvement at this fin, also be difficult to overcome fully existing issue, this has just formed the predicament on the industrial upgrading.
In sum, how to develop a kind of semiconductor package part with radiator structure, new-type radiator structure need not be made in the forging mode, the restriction that does not simultaneously also have thickness proportion, also can improve the elasticity of radiating efficiency, increase change in size simultaneously, and can not produce stress and concentrate in forming process, be the problem that relevant research and development field need urgently be faced.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, a purpose of the present invention be to provide a kind of need not be with the fin of forging method manufacturing and the semiconductor package part with radiator structure that can reduce cost.
An also purpose of the present invention is to provide a kind of semiconductor package part with radiator structure that reduces the packaging part height.
Another object of the present invention is to provide a kind of semiconductor package part that does not have the thickness proportion restriction with radiator structure.
A further object of the present invention is to provide a kind of area of dissipation that increases to improve the semiconductor package part with radiator structure of radiating efficiency.
Another purpose of the present invention is to provide a kind of semiconductor package part with radiator structure of avoiding fin stress to concentrate.
Of the present invention and another purpose is to provide a kind of semiconductor package part with radiator structure of avoiding packaging part distortion or layering.
Of the present invention and again a purpose be to provide a kind of semiconductor package part that promotes fin adhesive force with radiator structure.
Of the present invention and another purpose is to provide a kind of flexible semiconductor package part with radiator structure of variation that increases the heat sink sizes shape.
For reaching above-mentioned and other purpose, the semiconductor package part with radiator structure provided by the invention comprises: have first surface and with the substrate of its opposing second surface; At least one chip of putting on the first surface of substrate and being electrically connected to substrate that connects; One radiator structure comprises first fin and second fin, and this first fin has first location division, and this second fin has at least one second location division and at least one hollow-out parts; Wherein, second fin connects to be put on the first surface of substrate, first fin connects by first location division and puts on second location division of second fin, and hollow-out parts and the substrate that chip is coated on this first fin, second fin enclosed in the space that is set to; And a plurality of soldered balls of planting on the second surface that is connected on substrate.
The first above-mentioned fin and second fin all are tabular fin, and first fin is a top layer fin, second fin then comprises a bottom fin and at least one interlayer fin, and storehouse is positioned on the substrate mutually by being formed at lip-deep location division; Wherein, fin and location division form with process for stamping punching out cheaply (Stamp), are respectively formed at the peripheral position of each fin, first location division and second location division be respectively can mutual chimeric location flange and the combination of shrinkage pool.
In addition, radiator structure of the present invention can have various execution modes according to the demand of packaging part, for example, this first fin can align behind storehouse mutually with the inner edge or the outer rim of second fin, also can behind storehouse, make its inner rim or outer rim mutual dislocation arrange, simultaneously, when having a plurality of interlayer fin, then the arrangement mode storehouse of also available mutual alignment of the inner edge of each interlayer fin or outer rim or mutual dislocation is on the bottom fin.
Have, the area of first fin can optionally strengthen again, to improve the heat dissipation of packaging part, and can set up a radiator fan on first fin, or storehouse is at least one increases a layer fin, and makes this position that increases corresponding chip on layer fin form at least one hollow-out parts, dispels the heat with speed-up chip.
Also available punching press method for making is offered a plurality of flutings on the surface of second fin and substrate contacts, fill for the mucilage materials on the substrate that is laid in, promote the adhesive force of second fin, the inner wall surface of this fluting can be designed to stepped surfaces or inclined surface, to increase the adhesion area of mucilage materials and fluting, come off after avoiding fin to be shaken.
Its inside in sum,, and is the tabular design, so there is no concentrating of residual stress because each fin in the radiator structure of the present invention all is that storehouse forms; Simultaneously, because each fin of this stacking-type fin all has minimum thickness, and also can optionally change the storehouse number of plies,, also can significantly reduce the height of existing packaging part so this radiator structure is not subjected to the restriction on the thickness proportion (Aspect Ratio).Therefore, by radiator structure of the present invention, can give up existing fin and its forging method for making, what fully solve existing fin is installed with space and the development restriction of forging on the method for making, has also satisfied the demand of encapsulation technology to high integration, high heat radiation, low-cost and small sizeization etc.
Description of drawings
Fig. 1 is embodiment 1 cutaway view with semiconductor package part of radiator structure of the present invention;
Fig. 2 A to Fig. 2 C is top layer fin, interlayer fin and the bottom fin schematic diagram of embodiments of the invention 1;
Fig. 3 A to Fig. 3 C is the formation making method schematic diagram of first location division, second location division and the 3rd location division of embodiments of the invention 1;
Fig. 4 is embodiment 2 cutaway views with semiconductor package part of radiator structure of the present invention;
Fig. 5 is embodiment 3 cutaway views with semiconductor package part of radiator structure of the present invention;
Fig. 6 is embodiment 4 cutaway views with semiconductor package part of radiator structure of the present invention;
Fig. 7 is embodiment 5 cutaway views with semiconductor package part of radiator structure of the present invention;
Fig. 8 A and Fig. 8 B are embodiment 6 cutaway views with semiconductor package part of radiator structure of the present invention;
Fig. 9 is embodiment 7 cutaway views with semiconductor package part of radiator structure of the present invention;
Figure 10 is embodiment 8 cutaway views with semiconductor package part of radiator structure of the present invention;
Figure 11 A is embodiment 9 cutaway views with semiconductor package part of radiator structure of the present invention;
Figure 11 B is the schematic diagram of the interlayer fin shown in Figure 11 A;
Figure 12 A is embodiment 9 cutaway views with semiconductor package part of radiator structure of the present invention;
Figure 12 B is the schematic diagram of interlayer fin shown in Figure 12 A;
Figure 13 is embodiment 10 cutaway views with semiconductor package part of radiator structure of the present invention;
Figure 14 A and Figure 14 B are embodiment 11 cutaway views with semiconductor package part of radiator structure of the present invention;
Figure 15 is the packaging part cutaway view with embodiment of another fin location division of the present invention;
Figure 16 A to Figure 16 C is the formation position view of another fin location division of the present invention;
Figure 17 is existing Flip-Chip Using part cutaway view with fin;
Figure 18 A is a square radiating plate schematic diagram shown in Figure 180;
Figure 18 B is a square radiating plate cutaway view shown in Figure 18 A;
Figure 19 is existing Flip-Chip Using part cutaway view with twin-core sheet stack architecture;
Figure 20 is existing Flip-Chip Using part cutaway view with radiating fin;
Figure 21 is the existing Flip-Chip Using part cutaway view that is equipped with passive component that connects;
Figure 22 is the schematic diagram that the crack appears in the fin of existing Flip-Chip Using part; And
Figure 23 is the schematic diagram of the fin generation layering of existing Flip-Chip Using part.
Embodiment
Embodiment 1
Fig. 1 is the preferred embodiment cutaway view with semiconductor package part of radiator structure of the present invention, it is flip chip ball grid array packaging part (FCBGA), comprise substrate 10 as chip bearing member (ChipCarrier), be electrically connected to substrate 10 and connect the chip of putting on the first surface 10a of substrate 10 12 by projection 11 (Bump), be filled in projection 11 bottom filling (Under fill) insulating material 13 on every side, connect the bottom fin of putting on the first surface 10a of substrate 10 20, the interlayer fin 25 of a plurality of storehouses on bottom fin 20, the top layer fin 30 of storehouse on the interlayer fin 25 of top layer, and plant second surface 10b that is connected on substrate 10 and a plurality of soldered balls 14 that electrically connect with a plurality of projections 11; Wherein, bottom fin 20 is to utilize the mucilage materials 16 on the substrate first surface 10a that is laid in to be bonded on the substrate 10, top layer fin 30 is then bonding with the non-action face 12a of chip 12 by heat-conducting glue 15, heat with dissipation chip 12, simultaneously, a plurality of interlayer fin 25 and bottom fin 20, as shown in Figure 1, have first hollow-out parts 26 and second hollow-out parts 21 respectively, borrow its storehouse to close to tie up to and define a space on the substrate 10, and chip 12 is coated on by top layer fin 30, first hollow-out parts 26, second hollow-out parts 21 is enclosed being installed with in the space of putting with substrate 10.
By Fig. 2 B, Fig. 2 C as can be known, this interlayer fin 25 offers one first hollow-out parts 26 and one second hollow-out parts 21 respectively with the central authorities of bottom fin 20, first, second hollow-out parts 26,21 be shaped as is square, so that the edge of each hollow-out parts can align mutually behind its mutual storehouse, put out a square space and on substrate 10, enclose, chip 12 is coated in this space, simultaneously, shown in Fig. 2 B, this interlayer fin 25 has two kinds of design sizes, insert and put sheet space storehouse with two kinds of sizes of this size when its mutual storehouse, to make its outer rim behind storehouse, be dislocation arrangement and not line up mutually in twos, and as the cutaway view of Fig. 1, increase the packaging part area of dissipation of each side on every side.
In addition, top layer fin 30, interlayer fin 25 have first location division 32, second location division 27 and the 3rd location division 22 respectively with four angle edge of bottom fin 20, wherein, this first location division 32 is flanges, second location division 27 then comprises a shrinkage pool and a flange of mutual correspondence, the 3rd location division 22 is a hole, and above-mentioned each flange, shrinkage pool are corresponding mutually with size with the position of hole, mutual chimeric location and each fin of adhering when each fin storehouse; Therefore, shown in the cutaway view of Fig. 1, this interlayer fin 25 promptly is to utilize the flange of second location division 27 to be entrenched in the hole of the 3rd location division 22 of bottom fin 20, and each interlayer fin 25 also utilizes the flange of second location division 27 and the mutual engomphosis relation of shrinkage pool to come the storehouse location respectively, at last, pass through the flange of first location division 32 of top layer fin 30 again, be entrenched in the shrinkage pool of second location division 27 of top layer interlayer fin 25 the storehouse location of promptly finishing fin of the present invention.
Fig. 3 A, Fig. 3 B, Fig. 3 C shows first location division 32 respectively, the manufacturing process of second location division 27 and the 3rd location division 22, it is to utilize punching press cheaply (Stamp) method for making, staking punch (Punch) punching out with preliminary dimension goes out required location division, shown in Fig. 3 C, on tabular bottom fin 20, stamp out the hole 22a that runs through fin 20 by horizontal staking punch 40, the size of hole 22a is decided according to the size of staking punch 40, by running through the hole 22a of fin 20, also can make mucilage materials 16 pressurizeds of be laid in 10 of bottom fin 20 and substrates and insert among the hole 22a of the 3rd location division 22, thereby strengthen the adherence of bottom fin 20; Simultaneously, Fig. 3 B is the upper surface 25a with horizontal staking punch 40 punching press interlayer fin 25, make its upper surface 25a form the shrinkage pool 27a that does not run through fin 25, the material that is subjected to punching press is then extruded and is formed the flange 27b of fin lower surface 25b, at this moment, the position of flange 27b is with the position of corresponding shrinkage pool 27a, and its size just can be entrenched among the hole 22a of bottom fin 20; In addition, Fig. 3 A is then identical with Fig. 3 B, borrow the upper surface 30a of horizontal staking punch 40 punching press top layer fin 30, can on this top layer fin 30, form one group of corresponding flange 32b and shrinkage pool 32a too, and be entrenched in by means of flange 32b on the shrinkage pool 27a of top layer interlayer fin 25; Be noted that, because this top layer fin 30, interlayer fin 25 need mutual storehouse to be positioned on the substrate 10 with bottom fin 20, so the punching out position of first location division 32, second location division 27 and the 3rd location division 22 needs certain precision, so that storehouse and chimeric, interlayer fin 25 can be alignd with second hollow-out parts, 21 inner edges really with first hollow-out parts 26 of bottom fin 20 and chip 12 is coated wherein.
By above-mentioned stacking-type heat sink design and its punching press method for making, the depression that can avoid forming integrated existing fin is installed with the space, also need not adopt the forging method for making, can directly pass through punching press method for making cheaply, make radiator structure easily with high design flexibility; Simultaneously, because each fin 20,25,30 of this stacking-type fin all has minimum thickness, and also can optionally change the storehouse number of plies (configured number that changes interlayer fin 25 gets final product), so this radiator structure does not have the restriction on the thickness proportion (Aspect Ratio), can be as shown in Figure 1, make the height T of its integral heat sink structure be installed with the thickness t in space near chip, only slightly exceed the thickness of a top layer fin 30, significantly reduce the height of existing packaging part, can reach the slimming demand of packaging part; In addition, also can change the size or the area of each fin according to the chip layout on the substrate 10 arbitrarily, bringing into play the effect of its high design flexibility, or appropriateness improves the heat dissipation of this packaging part; Moreover, each fin 20,25,30 in the radiator structure of the present invention is owing to be that storehouse forms all, and be the tabular design and do not have other processing, so its inside there is no concentrating of residual stress, and in the zone that connects that postpone does not also carry the baby and can't Free Transform, so no matter be follow-up high temperature process of experience or various reliability testing, can not be out of shape or layering because of variation of ambient temperature, fully solved all shortcomings on the prior art.
Embodiment 2
Fin arrangement of the present invention is except that the foregoing description 1, also there is other can reach the design of equal effect, the embodiment of the invention 2 cutaway views for example shown in Figure 4, identical with embodiment 1, design has the interlayer fin 25 of two kinds of sizes of size, but first hollow-out parts, 26 inner edges of a plurality of interlayer fin 25 of the foregoing description 1 align mutually, make the fin outer rim be dislocation arrangement, increase the area of dissipation of packaging part both sides, the design of present embodiment is that the outer rim 25c of a plurality of interlayer fin 25 is alignd mutually, make inner edge 25d (i.e. the edge of the first hollow-out parts 26) mutual dislocation of interlayer fin 25 arrange, though and the inner edge 25d of each interlayer fin 25 is dislocation arrangement in the present embodiment, but still can enclose the space that is installed with that is set to coating chip 12 between its each inner edge 25d, and two side surfaces that its inner rim 25d can contact chip 12 yet.
Embodiment 3
Embodiments of the invention 3 promptly are in conjunction with the foregoing description 1 and embodiment 2, shown in the cutaway view of Fig. 5, be the inside and outside edge 25d of each layer fin, the semiconductor package part that 25c all is dislocation arrangement, this design is owing to having bigger area of dissipation and more heat dissipation path, so also have better radiating efficiency.
Embodiment 4
The embodiment of the invention 4 is that above-mentioned each layer fin cutaway view is as shown in Figure 6 arranged, make each top layer fin 30, interlayer fin 25 all have identical size with bottom fin 20, and its inside and outside edge 25d, 25c behind storehouse is trimmed fully, and become the smooth semiconductor package part of a periphery, equally also can bring into play effect of the present invention.
Embodiment 5
Shown in Figure 7 is embodiments of the invention 5 cutaway views, it increases the size of top layer fin 30, make its area much larger than bottom, interlayer fin 20,25 area, to strengthen heat-delivery surface, and improve the heat dissipation of chip 12 by the heat transfer of heat-conducting glue 15, the size of this top layer fin 30 or shape there is no the restriction in the design, be enough to fully satisfy the greatest requirements in the heat radiation, unlike prior art, be subject to processing procedure and can't change the area of fin surface, need not set up the existing radiating fin that is unfavorable for thinness encapsulation trend yet, give full play to high design flexibility effect of the present invention.
Embodiment 6
The fin kind of storehouse of the present invention is except that above-mentioned bottom, interlayer, top layer fin 20,25,30, and also can be on the top layer fin 30 extra a plurality of layer fin 45 that increase of storehouse are with further raising heat dissipation.Embodiment 6 is shown in Fig. 8 A, and this increases layer fin 45 plate-shaped fin for not having hollow-out parts, and it also arranges in the mode of dislocation, to increase area of dissipation; In addition, a plurality of layer fin 45 that increase also can be offered a hollow-out parts 46 respectively in the central shown in the cutaway view of Fig. 8 B, so that the middle position 30c of corresponding heat-conducting glue 15 (chip 12) on the top layer fin 30, expose outside the hollow-out parts 46 that increases layer fin 45, with the speed of speed-up chip 12 heat radiations.
Embodiment 7
When radiator structure of the present invention was used to have the packaging part of stack chip, its effect more was better than prior art.The cutaway view of the embodiment of the invention 7 as shown in Figure 9, it is the packaging part with double-deck stack chip, this moment is not because this stacking-type radiator structure has the restriction of thickness proportion, so the thickness of top layer fin 30 can not thickeied because of the chip stack number, simultaneously, interlayer fin 25 also can cooperate the size of stack chip and change the design of its hollow-out parts 26, changes as shown in the figure to be installed with the shape in space, thus the heat transferred path of shortening top layer chip 120.
Embodiment 8
In addition, when except that chip, setting up other passive component in addition on the substrate, also can utilize the design flexibility of radiator structure of the present invention, reach minimum material cost and best heat radiation function.Shown in Figure 10 is the embodiment of the invention 8, it changes the size of the hollow-out parts 26 of interlayer fin 25, make the side area of radiator structure can also can fully not shorten the heat dissipation path of passive component 17 simultaneously, fully solve the problem of existing fin because of passive component 17 increases too much.
Embodiment 9
For packaging part with multicore sheet (Multi-Chip) design, also can utilize radiator structure design of the present invention, make a plurality of chips all be installed with and enclose being installed with in the space of being set in hollow-out parts, the embodiment of the invention shown in Figure 11 A 9 for example, promptly be by the interlayer fin 25 shown in Figure 11 B, utilize its large-area hollow-out parts 26 designs to coat these two chips 12, but the design of this hollow-out parts 26 is not limited only to one, also can be as Figure 12 A, Figure 12 B, on each interlayer fin 25 and bottom fin 20, offer two hollow-out parts 26a respectively, 26b, to be installed with two chips 12 on the substrate 10 respectively, the bang path that increases chip 12 heats is selected, and reaches the effect of further raising radiating rate.
In addition, the present invention also can design by embodiment 10 as shown in figure 13, prolong the side edge length of bottom fin 20, interlayer fin 25 and top layer fin 30, and on the 30d of the prolongation zone of top layer fin 30, set up a compulsory type (Forced) radiator fan 50, borrow this heat that fan 50 pump drainage chips 12 produce, and the multi-path that can utilize multilayer interlayer fin 25 to form quickens heat radiation.
Radiator structure of the present invention is not with existing forging method manufacturing, so except that above-mentioned each effect, also can on the bottom fin, offer other detent mechanism, to solve the problem that comes off easily after existing fin is shaken, embodiment 11 is exactly on bottom fin 20 and surface that substrate 10 contacts, utilize the staking punch punching out to go out a fluting 51, make mucilage materials 16 pressurizeds of 10a on the substrate first surface and insert the fluting 51 in, fluting 51 can be shown in the cutaway view of Figure 14 A, form stair-stepping inner wall surface 51a, to increase the adhesion area of mucilage materials 16 and bottom fin 20, improve the adhesive force of fin 20, this fluting 51 also can form the tilt internal wall surface 51b of taper as the cutaway view of Figure 14 B, has the effect of enhance heat sheet 20 adhesions too.
The various embodiments described above all are the designs by each layer tabular fin, utilize the mutual storehouse in its location division, reach the effect requirement of different packaging parts, but mutually the location division of storehouse is only with the example that is illustrated as of embodiment 1, it is not unique execution mode of the present invention, semiconductor package part cutaway view as shown in figure 15 (structure with embodiment 1 is an example), the pressing direction of its location division is promptly opposite with the various embodiments described above, but can be used in the various embodiments of the present invention equally, wherein, first location division 52 that is formed at 30 jiaos of edge of top layer fin is a hole 52a, second location division 47 that is formed at interlayer fin 25 comprises a flange 47a and a shrinkage pool 47b of mutual correspondence, 42 of the 3rd location divisions that are formed at bottom fin 20 are a flange 42a, so that corresponding mutually, can carry out chimeric location when each fin storehouse; Except the equivalent embodiment of this location division, other need not use the various detent mechanism that forges method for making and be formed on the fin also all to be applicable in the radiator structure of the present invention.
In addition, the location division of the various embodiments described above all is formed at the edge position, angle of each fin, this Position Design is except that the hollow-out parts 26,21 that cooperates bottom fin 20 with interlayer fin 25 designs, also can make the detent force of fin more even firm, but the also non-unique design of the present invention in this position, shown in Figure 16 A, Figure 16 B, Figure 16 C, be formed at the location division 22,27,32 on each fin 20,25,30 edge, also can bring into play approximate positioning function, can be used among the present invention equally.
In sum, the semiconductor package part with radiator structure of the present invention really provides a kind of new-type radiator structure, need not use the forging method manufacturing, can reduce cost, and also not be subjected to the restriction of thickness proportion, fully meets the slimming requirement of encapsulation technology; Simultaneously, this radiator structure also can change fin shape as required or increase its area of dissipation, also can avoid distortion and layering, and fully takes into account its adhesion steadiness, overcomes above-mentioned existing all technical bottlenecks fully.
Claims (22)
1. the semiconductor package part with radiator structure is characterized in that, this semiconductor package part comprises:
Substrate has a first surface and an opposing second surface;
At least one chip connects to put on the first surface of substrate and with substrate and electrically connects;
Radiator structure, comprise first fin and second fin, this first fin has at least one first location division, and this second fin has at least one second location division and at least one hollow-out parts, this first fin is a top layer fin, this second fin then comprises a bottom fin and at least one interlayer fin, wherein, second fin connects to be put on the first surface of substrate, first fin is borrowed first location division to connect and is put on second location division of second fin, and this chip is coated on this first fin, the hollow-out parts of second fin and substrate enclose in the space that is set to; And
A plurality of soldered balls connect and put on the second surface of substrate.
2. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first fin and second fin are the tabular fin.
3. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first location division is a flange, and second location division comprises a shrinkage pool and a flange.
4. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first location division is a shrinkage pool, and second keeper comprises a flange and a shrinkage pool.
5. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first location division and second location division form with the staking punch punching out respectively.
6. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first location division and second location division are formed at the peripheral position of first fin and second fin respectively.
7. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first fin aligns mutually with the edge of second fin.
8. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, the edge of this first fin and second fin is arranged in the dislocation mode.
9. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, when having a plurality of interlayer fin, it is that the mode storehouse that aligns mutually with the edge is on the bottom fin.
10. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, when having a plurality of interlayer fin, it is that mode storehouse with mutual dislocation is on the bottom fin.
11. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that the area of this first fin is greater than the area of second fin.
12. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this first fin not with surface that second fin contacts on, going back storehouse has at least one layer fin that increase.
13. the semiconductor package part with radiator structure as claimed in claim 12 is characterized in that, this increases on layer fin position that should chip is had at least one hollow-out parts.
14. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this radiator structure comprises that also one connects the radiator fan of putting on first fin surface.
15. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, has a plurality of flutings on the surface of this second fin and substrate contacts.
16. the semiconductor package part with radiator structure as claimed in claim 15 is characterized in that, the inner wall surface of this fluting is a ladder surface.
17. the semiconductor package part with radiator structure as claimed in claim 15 is characterized in that, the inner wall surface of this fluting is an inclined surface.
18. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this chip is the first surface electric connection by conductive projection and substrate.
19. the semiconductor package part with radiator structure as claimed in claim 18 is characterized in that, this semiconductor package part also comprises the insulating material that is filled in around this conductive projection.
20. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this semiconductor package part also comprises the heat-conducting glue of bonding first fin and chip.
21. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that this semiconductor package part also comprises the mucilage materials between the first surface that is filled in second fin and substrate.
22. the semiconductor package part with radiator structure as claimed in claim 1 is characterized in that, this semiconductor package part is the flip chip ball grid array semiconductor package part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031558178A CN100369243C (en) | 2003-08-22 | 2003-08-22 | Semiconductor sealer with radiating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031558178A CN100369243C (en) | 2003-08-22 | 2003-08-22 | Semiconductor sealer with radiating structure |
Publications (2)
| Publication Number | Publication Date |
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| CN1585115A CN1585115A (en) | 2005-02-23 |
| CN100369243C true CN100369243C (en) | 2008-02-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB031558178A Expired - Fee Related CN100369243C (en) | 2003-08-22 | 2003-08-22 | Semiconductor sealer with radiating structure |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100447989C (en) * | 2005-05-18 | 2008-12-31 | 新灯源科技有限公司 | Integrated circuit packaging and manufacturing method |
| CN101466244B (en) * | 2007-12-21 | 2012-06-20 | 鸿富锦精密工业（深圳）有限公司 | Radiator |
| CN102881667A (en) * | 2012-10-08 | 2013-01-16 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure |
| CN104733405A (en) * | 2015-04-15 | 2015-06-24 | 江苏晟芯微电子有限公司 | Pin-type heat-radiating semiconductor packaging structure |
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|---|---|---|---|---|
| US5600541A (en) * | 1993-12-08 | 1997-02-04 | Hughes Aircraft Company | Vertical IC chip stack with discrete chip carriers formed from dielectric tape |
| US5773886A (en) * | 1993-07-15 | 1998-06-30 | Lsi Logic Corporation | System having stackable heat sink structures |
| US5956226A (en) * | 1997-10-01 | 1999-09-21 | Motorola, Inc. | Electrochemical capacitor used for thermal management |
| US6060778A (en) * | 1997-05-17 | 2000-05-09 | Hyundai Electronics Industries Co. Ltd. | Ball grid array package |
| US6359341B1 (en) * | 1999-01-21 | 2002-03-19 | Siliconware Precision Industries, Co., Ltd. | Ball grid array integrated circuit package structure |
| CN1354512A (en) * | 2000-11-17 | 2002-06-19 | 矽品精密工业股份有限公司 | Semiconductor package with radiating structure |
| US6552266B2 (en) * | 1998-03-11 | 2003-04-22 | International Business Machines Corporation | High performance chip packaging and method |
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2003
- 2003-08-22 CN CNB031558178A patent/CN100369243C/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5773886A (en) * | 1993-07-15 | 1998-06-30 | Lsi Logic Corporation | System having stackable heat sink structures |
| US5600541A (en) * | 1993-12-08 | 1997-02-04 | Hughes Aircraft Company | Vertical IC chip stack with discrete chip carriers formed from dielectric tape |
| US6060778A (en) * | 1997-05-17 | 2000-05-09 | Hyundai Electronics Industries Co. Ltd. | Ball grid array package |
| US5956226A (en) * | 1997-10-01 | 1999-09-21 | Motorola, Inc. | Electrochemical capacitor used for thermal management |
| US6552266B2 (en) * | 1998-03-11 | 2003-04-22 | International Business Machines Corporation | High performance chip packaging and method |
| US6359341B1 (en) * | 1999-01-21 | 2002-03-19 | Siliconware Precision Industries, Co., Ltd. | Ball grid array integrated circuit package structure |
| CN1354512A (en) * | 2000-11-17 | 2002-06-19 | 矽品精密工业股份有限公司 | Semiconductor package with radiating structure |
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| CN1585115A (en) | 2005-02-23 |
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