JP2002170847A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method that enables to conduct not through a contact but through a junction and can correspond to narrow pitch, many pin devices with high reliability in connection. method. SOLUTION: This semiconductor device with a single chip package is constituted of a multi-wiring layer structured board 1, a chip 2 mounted on the board 1, a sealant 3 sealing the joining part between the board 1 and the chip 2, external terminals and so on. The sealant 3 is made of a heat-hardening insulative resin 8 and fine microscopic particles 9 of Sn or Sn alloy, a metal with a low melting point, which are evenly dispersed in a film or a liquid of the resin 8 so that the particles do not touch each other. The particles 9 of Sn or Sn alloy are molten by pressure heating of two steps to form an alloy layer 10 in a joining part between a metal bump 7 of the chip 2 and a connecting metal pad 5 of the board 1 so as to bond both.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing technique thereof, for example, in a single-chip package or a multi-chip module, in particular, which corresponds to a narrow pitch and a large number of pins and has high connection reliability in flip-chip connection. The present invention relates to a technique that is effective when applied to a method for manufacturing a semiconductor device suitable for a connection method.

[0002]

2. Description of the Related Art As a technique studied by the present inventor, for example, for narrow-pitch, multi-pin flip-chip connection corresponding to a multi-chip module, an ACF (Anstropic Conductor) in which fine conductive particles are dispersed in an insulating resin is used.
A technique that applies the “Two Film” method is conceivable.

In this ACF method, an ACF is attached to a chip mounting area on a Ni (nickel) / Au (gold) plated connection metal pad on a substrate, and a chip with an Au bump is mounted face down. In this method, the Au bumps on the chip and the connection metal pads on the substrate are electrically connected by conductive particles in the insulating resin. The insulating resin of the ACF functions as a sealing material for the purpose of reducing the difference in thermal expansion coefficient between the substrate and the chip and the warpage.

[0004] Such a technique related to the ACF method is described, for example, in “Electronic Packaging Encyclopedia”, pages 653 and 654, edited by the Japan Institute of Electronics Packaging on July 28, 2000. Technology.

[0005]

The inventors of the present invention have studied the technique of the ACF method as described above, and have found the following. For example, in the above-mentioned ACF method, since only the contact between the Au bump on the chip and the connection metal pad on the substrate is conducted, there is a problem that the connection resistance sharply increases due to resin expansion during high-temperature operation. That is, since the connection state is only contact, there may be a problem that the connection resistance is unstable and an open failure is likely to occur due to resin expansion or the like in a high-temperature environment.

Accordingly, an object of the present invention is to disperse fine particles of a low-melting-point metal in an insulating resin material of a sealing material, thereby enabling conduction not by contact but by bonding to achieve narrow pitch, high pin count. And a method of manufacturing a semiconductor device capable of realizing a connection method with high connection reliability.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the method of manufacturing a semiconductor device according to the present invention, fine particles of a low-melting-point metal are dispersed inside a thermosetting insulating resin material on a surface of a substrate on which connection metal pads are provided. The chip with the metal bumps provided on the front surface is mounted face down from the top of the sealing material supplied on the substrate, and heated and pressurized from the back of the chip. The method includes the steps of joining the bump and the connection metal pad on the substrate via the fine particles of the low-melting-point metal of the sealing material to establish conduction between the chip and the substrate.

Further, in the method of manufacturing a semiconductor device, when heating and pressurizing from the back surface of the chip, the encapsulant is cured at a temperature equal to or lower than the melting point of the low-melting-point metal fine particles, and is heated to the melting point of the low-melting-point metal fine particles. At this temperature, the fine particles of the low melting point metal are melted to join the metal bump and the connection metal pad.

Further, in the method of manufacturing a semiconductor device, when the sealing material is cured, a load is applied from the back surface of the chip to thinly and flatten the fine particles of the low melting point metal sandwiched between the metal bump and the connection metal pad. When the metal bump and the connection metal pad are joined together, the thin and flat deformed fine particles of the low melting point metal are melted to form a thin and uniform alloy layer.

Further, in the method of manufacturing a semiconductor device, a plurality of chips are mounted face-down on the same substrate when the chips are mounted on the sealing material on the substrate.

Further, a semiconductor device according to the present invention comprises a substrate having connection metal pads provided on a surface thereof, and one or a plurality of semiconductor devices mounted face-down on the surface of the substrate and having metal bumps provided on the surface. And fine particles of Sn (tin) or a Sn alloy for joining the metal bumps on the one or more chips and the connection metal pads on the substrate are uniformly dispersed in the thermosetting insulating resin material. And a sealing material.

In detail, the present invention does not allow fine Sn or Sn alloy particles, which are low melting point metals, to come into contact with a chip mounting area on a connection metal pad on a substrate such as a resin substrate, a tape, or a ceramic substrate. The thermosetting insulating resin encapsulating material is uniformly dispersed as described above. From above,
A chip with metal bumps is mounted face down,
S between the metal bump of the chip and the connection metal pad of the substrate
While n or Sn alloy particles are sandwiched, heat and pressure are applied from the back surface of the chip at a temperature equal to or lower than the melting point of Sn or Sn alloy,
The particles are thinly and flatly deformed, and the insulating resin is cured. Then, the metal bumps on the chip and the connection metal pads on the substrate are heated and pressed from the back surface of the chip to the melting point temperature of Sn or Sn alloy to melt thin and flat deformed Sn or Sn alloy particles. And the connection metal pad, so that the chip and the substrate can be conducted.

In particular, in the present invention, by uniformly dispersing Sn or Sn alloy particles in an insulating resin sealing material, the chip and the substrate are not electrically connected by the conventional contact,
Conduction by bonding with high connection reliability can be enabled.

Therefore, according to the method of manufacturing a semiconductor device and the semiconductor device, a metal alloy is generated at the bonding interface, and unlike the conduction due to contact, conduction failure in a high-temperature environment is less likely to occur. Also, the connection resistance can be stabilized. Further, by supplying the sealing material to the substrate before the joining, it is possible to suppress the generation of voids which is a problem when supplying the sealing material after the joining. In addition, long-term bondability is improved by deforming the Sn or Sn alloy particles thinly and flat before melting. As a result, in the flip-chip connection for a narrow pitch and a large number of pins, stable bonding reliability can be ensured even in a high-temperature environment as compared with the conventional method.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1 is a sectional view showing a semiconductor device (single chip package) according to an embodiment of the present invention, FIG. 2 is a plan view, FIG. 3 is a bottom view, FIG. 4 is a sectional view showing a sealing material, FIG. 6 is a flowchart showing a method for manufacturing a semiconductor device, FIG. 7 is a sectional view showing another semiconductor device (multi-chip module), FIG. 8 is a plan view, FIG.
FIG. 10 is a sectional view showing a modification of the sealing material.

First, the configuration of an example of the semiconductor device of the present embodiment will be described with reference to FIGS. The semiconductor device of the present embodiment is, for example, a semiconductor device of a single chip package, and has an insulating substrate 1 (hereinafter, referred to as a substrate 1) having a multilayer wiring layer structure, and a semiconductor chip 2 (hereinafter, a chip) mounted on the substrate 1. 2), substrate 1 and chip 2
And an external terminal 4 and the like.

The substrate 1 is, for example, a resin substrate having a multilayer structure,
It is made of a tape, a ceramic substrate, or the like, and has a connection metal pad 5 (for example, a square
m) is provided on the front surface, and a connection metal land 6 (for example, about 50 μm in diameter) such as Au is provided on the back surface. From the connection metal pad 5 on the front surface, a through hole between each layer, a metal of each layer is provided. It is electrically connected to the connection metal land 6 on the back surface through the wiring pattern.

The chip 2 is composed of, for example, a microcomputer, a memory, or the like. For example, a metal bump 7 (for example, about 50 μm in diameter) of Au or the like is provided on the surface, and a predetermined integrated circuit such as a microcomputer, a memory, and the like is provided inside. It is formed and is electrically connected from each terminal of the internal integrated circuit to the metal bump 7 on the surface.

As shown in FIG. 4, the sealing material 3 is provided inside a thermosetting insulating resin material 8 such as an epoxy-based material.
It is formed in a film form (a) or a liquid form (b) in which fine low melting point metal Sn (tin) or Sn alloy particles 9 (for example, having a diameter of about 5 μm or less) are uniformly dispersed so as not to contact each other. . The Sn or Sn alloy particles 9 are melted by two-stage heating and pressing to form an alloy layer 10 at a joint between the metal bump 7 of the chip 2 and the connection metal pad 5 of the substrate 1, and are joined. Further, by making the diameter of the Sn or Sn alloy particles 9 fine, a narrow pitch,
Short-circuiting is less likely to occur even with multiple pins. The diameter of the alloy particles 9 is smaller than the distance between the connection metal pads 5 on the substrate 1 and the distance between the metal bumps 7 on the chip 2.

The external terminal 4 is, for example, Pb (lead) / Sn
(Tin) or lead-free solder balls, which are joined to the connection metal lands 6 on the back surface of the substrate 1 and are arranged on the back surface of the substrate 1 in one or two rows or in an array (FIGS. 1, 3).
Shows an example of one peripheral row, and the number may be different from the actual one in order to clarify the figure).

Next, a method of manufacturing a single-chip package semiconductor device according to the present embodiment will be described with reference to FIGS. In FIGS. 5 and 6, the drawings on the left are flowcharts showing respective manufacturing steps of the manufacturing method, and the drawings on the right are cross-sectional views showing semiconductor devices corresponding to the respective manufacturing steps.

Prior to the manufacture of the semiconductor device, first, as a preparatory step, the above-mentioned substrate 1, chip 2, sealing material 3, solder balls serving as external terminals 4, etc. necessary for manufacturing a semiconductor device of a single-chip package are provided. Prepare

(1) In the encapsulant supply step (step S1), Sn or S in the thermosetting insulating resin material 8 is provided in the chip mounting area on the connection metal pad 5 on the substrate 1.
The film-form (or liquid-form) sealing material 3 in which the n-alloy particles 9 are uniformly dispersed is supplied.

(2) In the chip mounting step (step S2), the chip 2 provided with the metal bumps 7 is mounted face down on the connection metal pads 5 from above the sealing material 3 supplied onto the substrate 1. I do.

(3) A state in which Sn or Sn alloy particles 9 of the sealing material 3 are sandwiched between the metal bumps 7 of the chip 2 and the connection metal pads 5 of the substrate 1 in the sealing material curing step (step S3). Then, heat and pressure are applied from the back surface of the chip 2 at a temperature equal to or lower than the melting point of the Sn or Sn alloy particles 9 to deform the Sn or Sn alloy particles 9 thinly and flatly, and the thermosetting insulating resin material of the sealing material 3 8 is cured.

(4) In the fusion bonding step (step S4), the metal bumps 7 on the chip 2 and the connection metal pads 5 on the substrate 1 are heated from the back surface of the chip 2 to the melting point of the Sn or Sn alloy particles 9. Is pressed to melt the thin or flat Sn or Sn alloy particles 9 that are sandwiched and melted to form a uniform Au.
An alloy layer 10 made of a -Sn alloy is formed, and the metal bumps 7 on the chip 2 and the connection metal pads 5 on the substrate 1 are joined.

(5) In the bumping step (step S5), after the metal bumps 7 on the chip 2 and the connection metal pads 5 on the substrate 1 are made conductive, external terminals are placed on the connection metal lands 6 on the back surface of the substrate 1. Attach the solder ball No. 4.

Thus, a single-chip package semiconductor device is completed. In this semiconductor device, the terminals of the integrated circuit inside the chip 2 are passed through the metal bumps 7 on the surface, the connection metal pads 5 on the surface of the substrate 1, the through holes between the layers, the metal wiring patterns of the layers, Are electrically conducted to the external terminals 4 through the connection metal lands 6.

Next, an example of a semiconductor device of a multi-chip module manufactured by applying the method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS.

The semiconductor device of the multi-chip module according to the present embodiment is different from the structure shown in FIGS. 1 to 3 in that a plurality of chips are mounted on the semiconductor device. A microcomputer chip 2a mounted on the substrate 1a, a plurality of (here, four) chips 2b of an SDRAM, and a sealing material 3a for sealing a joint portion between the substrate 1a and the plurality of chips 2a, 2b. When,
It is composed of an external terminal 4a and the like. Further, it is possible to adhere the heat radiating plate 11 to the back surface of the chips 2a and 2b in consideration of the heat radiating property, and it is also applicable to a case where a chip of another memory such as an SRAM or a chip such as an ASIC is mounted. It is.

The substrate 1a, the microcomputer chip 2a, the SDRAM chip 2b, the sealing material 3a, and the external terminals 4a have the same structure as that of the single chip package. The external terminals 4a are arranged, for example, in an array.

The microcomputer chip 2a controls the input / output operation of input / output data to / from a multichip module, and controls the data write / read operation to / from the SDRAM chip 2b.
This is for controlling and processing the entire multichip module.

The SDRAM chip 2b has, for example, a memory matrix in which a plurality of memory cells are arranged in a lattice, and enables data writing / reading for each memory cell under the control of the microcomputer chip 2a. Things.

Also in the semiconductor device of this multi-chip module, a sealing material supply step of supplying the sealing material 3a to the chip mounting area on the substrate 1a in accordance with the respective manufacturing steps as shown in FIGS. A chip mounting step of mounting the chips 2a and 2b from above the sealing material 3a on 1a, and encapsulation for curing the thermosetting insulating resin material 8a of the sealing material 3a by applying heat and pressure from the back surface of the chips 2a and 2b. Material curing process,
Heat and pressure are applied from the back surfaces of the chips 2a and 2b to the metal bumps 7
Bonding step of forming an alloy layer 10a by melting Sn or Sn alloy particles 9a and bonding the connection metal pad 5 to the external metal terminal 5 on the connection metal land 6 on the back surface of the substrate 1a.
The semiconductor device of the multi-chip module is completed by performing a bumping step of attaching a solder ball as “a”.

Therefore, according to the semiconductor device of the present embodiment, the metal bump 7 (7a) on the chip 2 (2a, 2b)
Since an alloy layer 10 (10a) made of an Au-Sn alloy is generated at the joint interface between the substrate and the connection metal pad 5 (5a) on the substrate 1 (1a), the conduction is different from the contact, and the conduction is due to the junction. Insufficient conduction in a high-temperature environment is unlikely to occur. Further, the connection resistance can be stabilized. That is, since a metal alloy is generated at the bonding interface,
Strong bonding strength can be obtained. In addition, only the pressurized portion captures the Sn or Sn alloy particles 9 (9a) and deforms it flat, and further, the Sn or Sn alloy particles 9 (9a) are trapped.
By heating to a temperature equal to or higher than the melting point of a), the alloy layer 10 (10a) for bonding is formed only in a portion where conduction is required, so that insulation between the metal bumps 7 can be ensured even in the case of a narrow pitch. it can.

Before joining, the sealing material 3 (3a) is
By supplying to (1a), after joining, the sealing material 3 (3a)
The generation of voids, which is a problem when supplying the gas, can be suppressed.

Further, Sn or Sn alloy particles 9 (9
By deforming a) thinly and flat before melting, long-term bondability is improved. That is, since the Sn or Sn alloy particles 9 (9a) are thinned and flattened by pressing before melting, excess Sn is discharged, and the amount of Sn supplied to the joint surface can be controlled and uniformized. In addition, a uniform alloy layer 10 (10a) can be formed at the time of melting, and the growth of an intermetallic compound that causes deterioration of the bonding interface strength can be suppressed even in a high-temperature environment, so that long-term bonding can be improved.

As a result, a narrow pitch in a semiconductor device of a single chip package and a multi chip module,
In flip-chip connection for multiple pins, stable bonding reliability can be ensured even in a high-temperature environment as compared with the conventional method.

In the semiconductor device of the present embodiment, the sealing material 3 (3a) is dispersed inside the thermosetting insulating resin material 8 (8a), for example, as shown in FIG. It is also possible to coat the Sn or Sn alloy particles 9 (9a) with the insulating resin material 12. For example,
When the distribution of the Sn or Sn alloy particles 9 (9a) is biased, if there is no material for coating the Sn or Sn alloy particles 9 (9a) as shown in FIG. Although it can be considered as a factor, by coating as shown in FIG. 10A, the particles do not directly contact each other even when the dispersion of the Sn or Sn alloy particles 9 (9a) is biased. Can prevent the particle size from increasing due to contact with the particles.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above-described embodiment, a case has been described in which the present invention is applied to a single chip package such as a microcomputer or a memory, or to a multichip module in which a microcomputer and an SDRAM are mixedly mounted. Flip chip bonding with pins has become an indispensable technology, and it can be widely applied to all products that require high connection reliability. In addition, products to be flip-chip bonded to purchased chips (in the case of purchased chips, WPP (Wafer Process Pa
Cage) is not possible, and high reliability bonding using metal bumps is essential.
Further, the present invention can be applied to a memory package requiring high-speed operation (a low junction resistance can be realized in a wide temperature range).

The connection metal pad of the substrate is made of Cu
(Copper) or Ni (nickel).

[0045]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) By joining the metal bumps on the chip and the connection metal pads on the substrate via the fine particles of the low-melting-point metal of the sealing material by applying heat and pressure from the back surface of the chip, Since a metal alloy is formed, unlike the conduction by contact, the conduction is by bonding, so that a strong bonding strength can be obtained, and an alloy layer for bonding is formed only in the areas where conduction is required by heating and pressing. Therefore, insulation between the metal bumps can be ensured even in the case of a narrow pitch, and it is possible to make it difficult to cause poor conduction in a high-temperature environment. Further, the connection resistance can be stabilized.

(2) By supplying the sealing material onto the substrate before joining the metal bumps on the chip and the connection metal pads on the substrate, voids that may cause problems when supplying the sealing material after joining are provided. Generation can be suppressed.

(3) The fine particles of the low-melting-point metal of the sealing material are thinly and flatly deformed before melting, so that excess low-melting-point metal is discharged and the amount of the low-melting-point metal supplied to the joint surface is controlled. In addition, since it can be uniform, a uniform alloy layer can be formed at the time of melting, and even in a high-temperature environment, the growth of an intermetallic compound that causes deterioration of the bonding interface strength can be suppressed,
It is possible to improve long-term bonding.

(4) By coating the fine particles of the low-melting-point metal of the sealing material with an insulating resin material, the particles do not directly contact each other even when the dispersion of the fine particles of the low-melting-point metal is uneven. It is possible to prevent the particle size from increasing due to the contact between the particles.

(5) According to the above (1) to (4), the present invention is applied to a semiconductor device such as a single-chip package or a multi-chip module, and can conduct not by contact but by bonding. In the corresponding flip-chip connection, stable bonding reliability can be ensured even in a high-temperature environment.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device (single-chip package) according to an embodiment of the present invention.

FIG. 2 is a plan view showing a semiconductor device (single chip package) according to one embodiment of the present invention;

FIG. 3 is a bottom view showing the semiconductor device (single chip package) according to one embodiment of the present invention;

FIGS. 4A and 4B are cross-sectional views showing a sealing material in the semiconductor device (single-chip package) according to one embodiment of the present invention;

FIG. 5 is a flowchart showing a method for manufacturing a semiconductor device (single chip package) according to one embodiment of the present invention;

FIG. 6 is a flowchart showing a method of manufacturing the semiconductor device (single chip package) according to the embodiment of the present invention (following FIG. 5).

FIG. 7 is a sectional view showing another semiconductor device (multi-chip module) according to one embodiment of the present invention;

FIG. 8 is a plan view showing another semiconductor device (multi-chip module) according to one embodiment of the present invention;

FIG. 9 is a bottom view showing another semiconductor device (multi-chip module) according to one embodiment of the present invention;

FIGS. 10A and 10B are cross-sectional views showing a modification of the sealing material in the semiconductor device according to the embodiment of the present invention;

[Explanation of symbols]

 1, 1a substrate 2, 2a, 2b chip 3, 3a sealing material 4, 4a external terminal 5, 5a connecting metal pad 6, 6a connecting metal land 7, 7a metal bump 8, 8a thermosetting insulating resin material 9, 9a Sn or Sn alloy particles 10, 10a alloy layer 11 radiator plate 12 insulating resin material

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Makoto Araki 3-3-2 Fujibashi, Ome-shi, Tokyo F-term in Hitachi Tokyo Electronics Co., Ltd. 5F044 LL01 LL04 LL09 RR17 RR19 RR19

Claims (5)

[Claims] A step of supplying a sealing material in which fine particles of a low-melting metal are dispersed inside a thermosetting insulating resin material, on a surface of a substrate provided with connection metal pads on the surface; From the top of the sealing material supplied on the substrate, a step of mounting a chip having metal bumps provided on the front face down, and applying heat and pressure from the back surface of the chip to the metal bumps on the chip. Bonding the connecting metal pad on the substrate to the chip via the fine particles of the low-melting-point metal of the encapsulant to establish conduction between the chip and the substrate. . 2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of curing the sealing material at a temperature equal to or lower than the melting point of the fine particles of the low melting point metal when heating and pressing from the back surface of the chip. And melting the low-melting-point metal fine particles at a temperature equal to or higher than the melting point of the low-melting-point metal fine particles to join the metal bumps and the connection metal pads. Production method. 3. The method of manufacturing a semiconductor device according to claim 2, wherein, when the sealing material is cured, a load is applied from a back surface of the chip to be sandwiched between the metal bump and the connection metal pad. The step of deforming the fine particles of the low melting point metal thin and flat, when joining the metal bump and the connection metal pad,
A method for producing a thin and uniform alloy layer by melting the fine particles of the low-melting-point metal deformed thinly and flatly. 4. The method of manufacturing a semiconductor device according to claim 1, wherein when mounting the chip from above the sealing material on the substrate, a plurality of chips are mounted face down on the same substrate. A method for manufacturing a semiconductor device, comprising: 5. A substrate having connection metal pads provided on a surface thereof; one or more chips mounted face-down on the surface of the substrate and having metal bumps provided on the surface; Or a sealing material in which fine particles of Sn or Sn alloy for bonding metal bumps on a plurality of chips and connection metal pads on the substrate are uniformly dispersed in a thermosetting insulating resin material. Characteristic semiconductor device.