JP2000150697A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To significantly reduce manufacturing costs by generalizing a printed wiring board wherein flip chips are mounted without decreasing the connection reliability of bumps. SOLUTION: A carrier board 6 which is provided at a semiconductor device 1 of a CSP(chip size package) i.e., a surface-mounting package comprises a base board 7 such as epoxy resin and lead wires 8 such as copper which has anisotropy in the depthwise direction of the base board 7 and are formed at established intervals, and both ends of the lead wire 8 are exposed at the top and bottom surfaces. A semiconductor chip 2 is mounted on the carrier board 6 through a conductive paste 5 to bond metallic bumps 4 with the lead wires 8. A wiring pattern 11 which electrically connects an electrode portion 10 with an electrode pad 3 is formed on the back of the carrier board 6. The wiring pattern 11 is formed by irradiating the back of the carrier board 6 with laser light to melt the lead wires 8 formed on the base board 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor device, and more particularly to a technique which is effective when applied to cost reduction of flip-chip connection.

[0002]

2. Description of the Related Art According to studies made by the present inventors, it has been found that a BGA (Ball Grid) which is a surface mount package is used.
Array) and CSP (Chip Size Pac)
In a semiconductor device such as kage), a semiconductor chip is mounted by flip-chip connection.

[0003] The flip-chip connection is a technique for mounting a semiconductor chip with its active surface facing down. A metal bump made of solder or the like is provided on an electrode pad formed on the semiconductor chip. It is pressed and connected to the electrode part formed on the substrate.

In flip-chip connection, a joining technique using an anisotropic conductive film or the like instead of a metal bump is also used. The anisotropic conductive film is, for example, an electrical connection material in which conductive particles such as carbon black, nickel fine particles, and ball solder are dispersed in a resin. Electrical connection between the electrodes in the thickness direction is performed while maintaining insulation in the surface direction by pressing and holding.

[0005] As an example describing this type of semiconductor device in detail, see Nikkei B on May 31, 1993.
Published by Company P, Susumu Kayama, Kunihiko Naruse (supervised), "Practical Course VLSI Packaging Technology (2)" P175, P1
In this document, the configuration of flip chip connection and the like are described.

[0006]

However, the present inventor has found that the flip chip connection technology in the semiconductor device as described above has the following problems.

That is, it is necessary that the positions of the electrode pads of the semiconductor chip and the electrode portions of the printed wiring board on which the semiconductor chip is mounted correspond to each other on a one-to-one basis. Therefore, there is a problem that the cost of the semiconductor device is increased.

An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can greatly reduce the manufacturing cost by generalizing a printed wiring board for flip-chip connection without impairing the connection reliability of the bumps. To provide.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor device according to the present invention, an anisotropic conductive substrate in which conductive lines having anisotropy in the thickness direction are formed at predetermined intervals and both ends of the conductive lines are exposed from the front and back surfaces. Provided with a carrier substrate.

Further, a method of manufacturing a semiconductor device according to the present invention
A step of preparing a carrier substrate made of an anisotropic conductive substrate in which conductive lines having anisotropy in a thickness direction are formed at predetermined intervals and both ends of the conductive line are exposed from the front and back surfaces, A step of mounting a semiconductor chip on the substrate, forming a wiring pattern on the back side of the carrier substrate, and electrically connecting a chip electrode of the semiconductor chip and an external terminal connection electrode formed on the carrier substrate; Attaching a bump serving as an external terminal to the external terminal connection electrode.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the step of forming the wiring pattern, the step of moving the laser beam along the shape of the wiring pattern and melting the conductive lines of the carrier substrate to form the semiconductor chip Are electrically connected to the external terminal connection electrodes of the carrier substrate.

Further, a method of manufacturing a semiconductor device according to the present invention
The step of forming the wiring pattern includes a step of masking the back surface of the carrier substrate with a mask on which the wiring pattern is drawn, and irradiating the entire masked carrier substrate with a laser beam to collectively form the carrier into a wiring pattern shape. Melting the conductive wires of the substrate and electrically connecting the chip electrodes of the semiconductor chip to the external terminal connection electrodes of the carrier substrate.

As described above, even if semiconductor chips having different shapes and types can be mounted on one carrier substrate, the carrier substrate can be used in common even if the semiconductor device types are different. The manufacturing cost of the device can be significantly reduced.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a partially cutaway explanatory view of a semiconductor device according to one embodiment of the present invention, and FIG. 2A is a front side of a carrier substrate used in the semiconductor device according to one embodiment of the present invention. 3B is an explanatory view of the back side of the carrier substrate. FIGS. 3 to 5 are explanatory views of a manufacturing process in the semiconductor device according to the embodiment of the present invention.
FIG. 7 is an explanatory view of forming a wiring pattern on a carrier substrate according to an embodiment of the present invention. FIG. 7 is a flowchart of a manufacturing process in a semiconductor device according to an embodiment of the present invention.

In the present embodiment, the semiconductor device 1
As shown in FIG. 1, C, which is a type of surface mount package,
It is composed of SP. The semiconductor device 1 includes a semiconductor chip 2. On the main surface of the semiconductor chip 2, a semiconductor element constituting a logic circuit or the like is formed.

On the main surface of the semiconductor chip 2, a plurality of electrode pads (chip electrodes) arranged along the vicinity of each side are provided.
The electrode pads 3 are electrically connected to a logic circuit or the like constituted by the above-described semiconductor elements.

A spherical metal bump 4 made of gold (Au) or the like is formed on the electrode pad 3 of the semiconductor chip 2. The metal bumps 4 are formed on the electrode pads 3 of the semiconductor chip 2 by so-called stud bump bonding in which bumps are formed from bonding wires such as gold wires using a wire bonding technique. Further, the metal bumps 4 are connected to the surface of the carrier substrate 6 via the conductive paste 5.

The carrier substrate 6 is composed of, for example, a base substrate 7 made of an epoxy resin material and a conductive wire (conductive wire) 8 made of copper (Cu) or the like. The conducting wires 8 are formed at predetermined intervals with anisotropy in the thickness direction of the base substrate 7, and both ends of the conducting wire 8 are exposed from the front and back surfaces of the base substrate 7. The density of the conductive wires 8 formed on the base substrate 7 is set to have a sufficient conductivity in consideration of the electrode pad size of the semiconductor chip 2 and the like.

Therefore, the electrode pads 3 of the semiconductor chip 2
Are electrically connected to the conductive wires 8 on the back surface of the carrier substrate 6 through the metal bumps 4, the conductive paste 5, and the conductive wires 8 on the main surface of the carrier substrate 6. Further, a gap between the semiconductor chip 2 and the carrier substrate 6 is filled with an underfill 9.

The underfill 9 is an insulating resin in which a filler such as quartz particles is mixed into an epoxy resin or the like. The underfill 9 integrates the semiconductor chip 2 and the carrier substrate 6 to reduce the concentration of stress applied to the metal bumps 4. Preventing.

In the vicinity of the peripheral portion on the back surface of the carrier substrate 6, electrode portions (external terminal connection electrodes) 10 serving as external connection terminals are formed at predetermined intervals. The conductive wires 8 are electrically connected to the metal bumps 4 via the wiring patterns 11 formed on the back surface.

Then, connection bumps 12 made of solder or the like are attached to the electrode portions 10 of the carrier substrate 6,
The bump is formed by connecting the bump formed on the electrode section 10 to an electrode section provided on a printed wiring board on which electronic components such as a semiconductor device are mounted.

Next, the manufacturing process of the semiconductor device 1 will be described.
This will be described with reference to FIGS. 1, 2 to 6 and the manufacturing process flowchart of FIG. 7.

First, as shown in FIGS. 2A and 2B,
The carrier substrate 6 is prepared in which the conductive wires 8 are formed on the base substrate 7 with a predetermined density and anisotropy in the thickness direction of the base substrate 7 (step S101).

As described above, this carrier substrate 6
Both ends of the conductive wire 8 are exposed from the front and back surfaces of the base substrate 7, and the electrode portion 1 on which a bump 12 serving as an external connection terminal is attached is provided near a peripheral portion on the back surface of the base substrate 7.
Zeros are formed at predetermined intervals.

The conductive paste 5 is applied to the surface of the carrier substrate 6, and the semiconductor chip 2 is mounted on the carrier substrate 7 so that the conductive paste 5 and the metal bumps 4 of the semiconductor chip 2 are superimposed (Step S102). ), The metal bumps 4 are heated by a curing device or the like to join the conductive wires 8 of the carrier substrate 6 and the metal bumps 4.

Then, as shown in FIG. 3, the gap between the semiconductor chip 2 and the carrier substrate 6 is filled with the underfill 9, and the underfill 9 is cured by heating again with a curing device or the like (step S103).

As shown in FIG. 4, the electrode pads 3 of the semiconductor chip 2 are electrically connected to the back side of the carrier substrate 6 by the conductive wires 8 of the carrier substrate 6 with which the electrode pads 3 are in contact via the conductive paste 5. State.

As shown in FIG. 5, an electrode portion 10 provided on the back surface of the carrier substrate 6 and the electrode pads 3 of the semiconductor chip 2 are electrically connected to the carrier substrate 6 on which the semiconductor chip 2 is mounted. Therefore, the wiring pattern 11 is formed (Step S104).

The wiring pattern 11 is, for example, as shown in FIG.
As shown in FIG. 5, the back surface of the carrier substrate 6 is formed by irradiating a laser beam to melt the conductive wires 8 formed on the base substrate 7. At this time, the output of the laser light to be irradiated is adjusted by adjusting the density and thickness of the conductive wire 8 to control the melting depth of the rear surface of the carrier substrate 6.

Here, semiconductor chips 2a of different sizes
Is mounted on the carrier substrate 6.

For example, as shown in FIG. 8, a semiconductor chip 2 smaller than the semiconductor chip 2 in the present embodiment
Even if a is mounted, the wiring pattern 11 may be formed on the rear surface of the carrier substrate 6 by irradiating the laser light similarly to the process of step S104.

When the wiring pattern 11 is formed on the carrier substrate 6, bumps such as solder balls are attached to the electrode portions of the carrier substrate 6 (step S105), and the semiconductor device 1 shown in FIG. 1 is obtained.

Thus, according to the present embodiment, since the wiring pattern 11 is formed on the carrier substrate 6 in accordance with the position of the electrode pad 3 of the semiconductor chip 2, regardless of the type and size of the semiconductor chip 2, The carrier substrate 6 can be used as a general-purpose product, a plurality of types of carrier substrates are not required, and the manufacturing cost of the semiconductor device 1 can be significantly reduced.

In this embodiment, the CSP type semiconductor device has been described.
(Land Grid Array) such as a flip-chip connected semiconductor device in which a semiconductor chip and a carrier substrate are connected by metal bumps.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the individual wiring patterns are formed by irradiating the carrier substrate with laser light. However, as shown in FIG. 9, the wiring patterns are drawn on the rear surface of the carrier substrate. The wiring pattern may be formed collectively by performing masking using the mask 12 and irradiating the entire back surface of the carrier substrate with laser light. Thereby, the efficiency of forming the wiring pattern can be improved.

A conductive pattern is formed by applying a conductive paste on an anisotropically conductive carrier substrate and pressing the conductive paste, or by punching a copper foil or the like into a wiring pattern. The wiring pattern may be formed by attaching the copper foil with a conductive paste.

[0042]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, since the wiring pattern is formed on the carrier substrate in accordance with the position of the chip electrode of the semiconductor chip, the carrier substrate is commonly used regardless of the type and size of the semiconductor chip. And a plurality of types of carrier substrates can be eliminated.

(2) Further, according to the present invention, since a wiring pattern can be collectively formed by masking with a mask on which a wiring pattern is drawn and irradiating a laser beam, a semiconductor chip having a different shape can be efficiently used. A carrier substrate can be manufactured.

(3) Further, in the present invention, according to the above (1) and (2), the manufacturing cost and material cost of the semiconductor device can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a partially cutaway explanatory view of a semiconductor device according to an embodiment of the present invention.

FIG. 2A is an explanatory diagram of a front surface side of a carrier substrate used in a semiconductor device according to an embodiment of the present invention, and FIG. 2B is an explanatory diagram of a back surface side of the carrier substrate.

FIG. 3 is an explanatory diagram of a manufacturing process in the semiconductor device according to one embodiment of the present invention;

FIG. 4 is an explanatory view of the manufacturing process in the semiconductor device following FIG. 3;

FIG. 5 is an explanatory view of the manufacturing process in the semiconductor device, following FIG. 4;

FIG. 6 is an explanatory diagram of wiring pattern formation on a carrier substrate according to one embodiment of the present invention.

FIG. 7 is a manufacturing process flowchart in the semiconductor device according to the embodiment of the present invention;

FIG. 8 is an explanatory diagram of a wiring pattern in a semiconductor device according to another embodiment of the present invention.

FIG. 9 is an explanatory diagram of forming a wiring pattern on a carrier substrate according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 semiconductor device 2, 2a semiconductor chip 3 electrode pad (chip electrode) 4 metal bump 5 conductive paste 6 carrier substrate 7 base substrate 8 conductive wire (conductive wire) 9 underfill 10 electrode portion (electrode for external terminal connection) 11 wiring pattern 12 mask

Claims (4)

[Claims] 1. A semiconductor chip is mounted on a front surface of a carrier substrate, and a plurality of external connection terminals electrically connected to chip electrodes provided on the semiconductor chip are provided on a back surface, and the external connection terminals are provided on the external connection terminals. In a semiconductor device having bumps formed thereon, the carrier substrate is formed with conductive lines having anisotropy in a thickness direction of the carrier substrate at predetermined intervals, and both ends of the conductive lines are A semiconductor device comprising an anisotropic conductive substrate exposed from the front and back surfaces of the carrier substrate. 2. A carrier substrate comprising an anisotropic conductive substrate in which conductive lines having anisotropy in a thickness direction are formed at predetermined intervals, and front ends of both sides of the conductive line are exposed from front and back surfaces, is prepared. A step of mounting a semiconductor chip on the carrier substrate; forming a wiring pattern on the back side of the carrier substrate; and electrically connecting the chip electrodes of the semiconductor chip and the external terminal connection electrodes formed on the carrier substrate. A method of manufacturing a semiconductor device, comprising: a step of electrically connecting; and a step of attaching a bump serving as an external terminal to the external terminal connection electrode. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the wiring pattern includes moving a laser beam along the wiring pattern to melt the conductive lines of the carrier substrate. And electrically connecting the chip electrodes to the external terminal connection electrodes of the carrier substrate. 4. The method for manufacturing a semiconductor device according to claim 2, wherein the step of forming the wiring pattern includes: a step of masking a back surface of the carrier substrate with a mask on which a wiring pattern is drawn; Irradiating the entire surface with a laser beam, melting the wiring pattern at a time, and electrically connecting the chip electrodes of the semiconductor chip and the external terminal connection electrodes of the carrier substrate. Device manufacturing method.