CN1354509A - Film spherical grid array type semiconductor package structure and its making method - Google Patents
Film spherical grid array type semiconductor package structure and its making method Download PDFInfo
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- CN1354509A CN1354509A CN 00132440 CN00132440A CN1354509A CN 1354509 A CN1354509 A CN 1354509A CN 00132440 CN00132440 CN 00132440 CN 00132440 A CN00132440 A CN 00132440A CN 1354509 A CN1354509 A CN 1354509A
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- film
- radiating block
- weld pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
The invention relates to a semiconductor encapsulation structure with array type of sheeting glue and spherical grid as well as its preparing mehtod. The characteristics are that the structure of heat-sinking block is of integrative figuration and a plated palladium layer is formed on the block. The palladium layer makes the heat-sinking block included into ground circuit, thus floating ground will not occur so as to guarantee the operating performance of encapsulated wafer. Moreover the palladium layer reinforces the bonding strength between the heat-sinking block and the glue. In the invented method, the spherical grid array is connected to the heat-sinking block electrically by using welding pad instead of traditional closure, so making encapsulating procedure more simplified.
Description
The present invention relates to a kind of semiconductor packaging, particularly relevant a kind of film spherical grid array type of what (Tape Ball Grid Array, TBGA) semiconductor package and preparation method thereof.
Ball grid array (Ball Grid Array, BGA) be a kind of advanced person's semiconductor packaging, its characteristics adopt a substrate to settle semiconductor wafer at what, and this substrate back of what plants and puts a plurality of soldered balls, with by these soldered balls with whole mounting structure weldering knot and be electrically connected to printed circuit board (PCB).
(Tape Ball Grid Array TBGA) then is a kind of BGA encapsulation technology of modified form to film spherical grid array, and its characteristics adopt a kind of slim film to be used as substrate at what, and plants on this film of what and put soldered ball.The TBGA encapsulation technology can make the overall dimensions of semiconductor package body do more compactly.
At present existing many different patented technologies can be used for making the TBGA encapsulating structure, for example comprise following listed United States Patent (USP):
United States Patent (USP) the 5th, 844, No. 168 " MULTI-LAYER INTERCONNECT BALL GRIDARRAYS ":
United States Patent (USP) the 6th, 020, No. 637 " BALL GRID ARRAY SEMICONDUCTORPACKAGE ".
United States Patent (USP) the 5th, 583, No. 378 " BALL GRID ARRAY INTEGRATED CIRCUITPACKAGE WITH THERMAL CONDUCTOR ".
United States Patent (USP) the 5th, 663, No. 530 " WIRE BOND TAPE BALL GRID ARRAYPACKAGE ".
United States Patent (USP) the 5th, 420, No. 460 " THIN CAVITY DOW BALL GRID ARRAYPACKAGE BASED ON WIREBOND TECHNOLOGY ".
Yet United States Patent (USP) the 5th, a shortcoming of 844, No. 168 in its TBGA mounting structure that is provided, exists excessive ground connection inductance and resistance at what, therefore the current characteristics in the time of can having influence on the practical operation of semiconductor wafer what makes operating characteristics become relatively poor.The Figure 1A to Figure 1B that below promptly cooperates institute's accompanying drawing, and TBGA encapsulating structure that No. the 5th, 844,168, the simple declaration United States Patent (USP) and shortcoming thereof (annotate: the accompanying drawing of Figure 1A to Figure 1B shown here for simplifying, it only shows the part relevant with the present invention; Detailed accompanying drawing asks three to read United States Patent (USP) the 5th, 844, No. 168 specification).
Shown in Figure 1A, United States Patent (USP) the 5th, 844, No. 168 disclosed TBGA encapsulating structure comprises structure-reinforced (stiffener) 310 of a pair of laminar, it by first structure-reinforced layer of 310a, mucigel 310b, and second structure-reinforced layer of 310c formed.In addition, this TBGA encapsulating structure also comprises a TAB film (TAB tape) 320, one integrated circuit (IC) wafer (integrated circuit) 315, a plurality of soldered ball (solder balls) 330,340, plural conductive plug (conductive plugs) 350 and one packing colloid (encapsulant) 365.This structure-reinforced 310 mainly is in order to strengthen the structural strength of whole mounting structure, to produce distortion to prevent it; But it also can use the heat that is produced when distributing the operation of integrated circuit (IC) wafer 315 whats simultaneously as a radiating block (heat sink).
Shown in Figure 1B, when above-mentioned TBGA mounting structure is settled when locating on what one printed circuit board (PCB) 400, wherein structure-reinforced (heat radiation. piece) the 310th, however be connected to earth point on the printed circuit board (PCB) 400 via conduction plug 350 on the periphery of position what TAB film 320 and soldered ball 340.; Packaged integrated circuit (IC) wafer 315 is then via a wafer earth current loop 500 (being the loop shown in the dashed rectangle of label 500 indications) and be connected to earth point on the printed circuit board (PCB) 400.This wafer earth current loop 500 comprises bonding wire 316 in regular turn, conductive trace (not shown) on the TAB film 320, yet and a shortcoming of the above-mentioned TBGA encapsulating structure of soldered ball 340. what structure-reinforced (radiating block) 310 wherein do not comprise what wafer earth current loop 500 in, therefore the ground connection of structure-reinforced (radiating block) 310 only is a kind of floating earth (floating ground), cause existing in this mounting structure excessive ground connection inductance and resistance (ground inductance and resistance), therefore in the time of can making the 315 what practical operations of packaged integrated circuit (IC) wafer, its current characteristics is adversely affected and makes operating characteristics become relatively poor.
A kind of solution of the problems referred to above discloses No. the 6th, 020,637, what United States Patent (USP).Fig. 2 A to Fig. 2 B that below promptly cooperates institute's accompanying drawing, and TBGA encapsulating structure that No. the 6th, 020,637, the simple declaration United States Patent (USP) and shortcoming thereof (annotate: Fig. 2 A to Fig. 2 B shown here accompanying drawing for simplifying, it only shows the part relevant with the present invention; Detailed accompanying drawing asks three to read United States Patent (USP) the 6th, 020, No. 637 original text specification).
Shown in Fig. 2 A, United States Patent (USP) the 6th, 020, No. 637 disclosed TBGA encapsulating structure also comprises the radiating block of a pair of laminar, and it is made up of 160 of a fin (heat spreader) 110, one mucigel (adhesive layer) 127 and one ground strips (ground plane).In addition, this TBGA encapsulating structure comprises semiconductor wafer 112, one bendable film type substrate (flex tape interconnect substrate) 150, plural conductive plug 119, a plurality of soldered ball 120,120a and a packing colloid 122; Wherein semiconductor wafer 112 is the conductive trace (not shown)s that are electrically connected to by one first bonding wire group 126 ' on the substrate 150, and by one second bonding wire group 126 " and be electrically connected to a formed ring earthing pad (ground ring) 164 on the ground strip 160.
It adopts conduction plug 119 and soldered ball 120a the ground strip below the fin 110 160 to be electrically connected to the earth point of printed circuit board (PCB) (not shown) to the characteristics of above-mentioned TBGA encapsulating structure at what.This ground connection connected mode can make fin 110 also comprise what semiconductor wafer 112 the earth current loop in, therefore adopt United States Patent (USP) the 6th, 020, No. 637 TBGA encapsulating structure can be avoided aforesaid floating earth problem, makes that wherein ground connection inductance and the unlikely what of resistance are excessive and influence the operating characteristics of semiconductor wafer 112.
Yet United States Patent (USP) the 6th, 020 on No. 637 the TBGA encapsulating structure what manufacture method, but still has some problems to exist.
Shown in Fig. 2 B, the radiating block that is adopted by the TBGA encapsulating structure of No. the 6th, 020,637, what United States Patent (USP) is a pair of layered structure (that is be made up of fin 110 and ground strip 160), so its assembly working is comparatively numerous and diverse.In addition, also rather idol is assorted for the production process of the ring earthing pad 164 on the ground strip 160, it must at first see through photoresistance cover curtain (photoresist mask) and carry out the gold-plated or silver-plated program of a selectivity (Au/Ag plating), forms an Au/Ag electrodeposited coating by this and is used as this ring earthing pad 164; Then carry out a melanism handling procedure (black oxidation) again, on all surface of ground strip 160, form the villous copper oxide of a black (cupric oxide by this, CuO) 165, in order to the surperficial bond intensity between enhancing ground strip 160 and packing colloid 122.Yet not only rather idol is assorted on program step for the production process of this ring earthing pad 164, and melanism processing procedure wherein can be polluted the Au/Ag electrodeposited coating of before having finished (being ring earthing pad 164) by easy what, cause ring earthing pad 164 and packing colloid 122 between bond strength Cui not, make packing colloid 122 easy whats produce delaminations (delamination).
Except above problem, United States Patent (USP) the 6th, 020, No. 637 TBGA encapsulation technology still has following several shortcomings.First shortcoming is the through hole of must giving a farfetched interpretation out earlier on the substrate, with as the electric connection path between ground connection weld pad and ground strip, can make therefore that whole encapsulation production process is comparatively numerous and diverse and wastes time and energy.Second shortcoming is that substrate is pasted to ground strip, and the ground strip on the what position what lead to the hole site of still needing gives silver-platedly, then just conducting resinl can be inserted to through hole and forms required conduction plug; But can making that whole encapsulation production process is more numerous and diverse, this step do not meet cost benefit.The Hou that the 3rd shortcoming finished for the conduction plug, the ball grid array production process of following are to adopt fabrography (screen printing) that scolder is applied on the precalculated position on the substrate; The Hou of finishing then need be carried out the reflow program again to form required soldered ball.Yet, adopt wire mark program and reflow program can make that but whole encapsulation production process is more numerous and diverse; And the required scolder cleaning procedure regular meeting of the Hou of reflow program pollutes whole substrate, and the TBGA encapsulation unit that causes Hou to be finished produces integrity problem.
The shortcoming of the above known technology of mirror what, purpose of the present invention provides a kind of TBGA encapsulation technology of novelty at what, can not have floating earth in its TBGA mounting structure of making, therefore can not have excessive ground connection inductance and resistance, make the operating characteristics of packaged semiconductor wafer can not be adversely affected.
The present invention also provides a kind of TBGA encapsulation manufacturing method of novelty, and program step is wherein more simplified than known technology and easily what enforcement.
The present invention provides a kind of TBGA encapsulating structure of novelty again, can have good binding intensity between radiating block wherein and packing colloid, is difficult for causing delamination.
Comprise following member on the encapsulating structure that the present invention's TBGA encapsulation technology is provided: (a) radiating block, it is made in integrally formed mode, has a upper surface and a lower surface, wherein is formed with on the lower surface to put brilliant depression; (b) a palladium plating layer, it forms on all surface of this radiating block of what with plating mode; (c) semiconductor wafer, it is putting in the brilliant depression of arrangement this radiating block of what; This semiconductor wafer has at least one earth point; (d) a film type substrate, it is pasted on the lower surface of this radiating block of what by a conductivity mucigel; This film type substrate comprises: (d1) film is formed with on it on a plurality of contact window whats precalculated position; (d2) a plurality of ground connection weld pads, it forms respectively on a plurality of contact windows of this film of what, and forms electrical the contact with this conductivity mucigel; (d3) the signal weld pad is gone in a plurality of outputs, and it forms respectively on the precalculated position on this film of what; (d4) a weld pad cover curtain, it covers a surface of this film, exports into the signal weld pad with these but expose these ground connection weld pads; (e) one first bonding wire group is exported into the signal weld pad in order to this semiconductor wafer is electrically connected to those; And one second bonding wire group, in order to the earth point on this semiconductor wafer is electrically connected to the palladium plating layer on this radiating block; (f) ball grid array, it comprises one first soldered ball group and one second soldered ball group; Wherein this first soldered ball group pastes respectively to those ground connection weld pads, and this second soldered ball group pastes respectively to those to export into the signal weld pad; And (g) packing colloid, it forms putting in the brilliant depression of this radiating block of what, in order to coat this semiconductor wafer and this first and second bonding wire group.
Comprise following program step on the TBGA encapsulation technology what manufacture method of the present invention: (1) precasts a radiating block, and it is made in integrally formed mode, has a upper surface and a lower surface, wherein is formed with on the lower surface to put brilliant depression; (2) carry out a plating palladium production process, use on all surface that forms this radiating block of palladium plating layer what; (3) a film type substrate is pasted on the lower surface of this radiating block of what by a conductivity mucigel; This film type substrate comprises: (3a) film is formed with on it on a plurality of contact window whats precalculated position; (3b) a plurality of ground connection weld pads, it forms respectively on a plurality of contact windows of this film of what, and forms electrical the contact with this conductivity mucigel; (3c) the signal weld pad is gone in a plurality of outputs, and it forms respectively on the precalculated position on this film of what; (3d) weld pad cover curtain, it covers a surface of this film, exports into the signal weld pad with those but expose these ground connection weld pads; (4) semiconductor wafer is settled in the brilliant depression of putting of this radiating block of what; This semiconductor wafer has at least one earth point; (5) carry out a bonding wire production process, by one first bonding wire group this semiconductor wafer is electrically connected to those and exports, and one second bonding wire group is electrically connected to palladium plating layer on this radiating block with the earth point on this semiconductor wafer into the signal weld pad; (6) carry out a packing colloid production process, use putting in the brilliant depression of formation one this radiating block of packing colloid what, in order to coat this semiconductor wafer and this first and second bonding wire group signal weld pad; And (7) carry out a ball grid array production process, and in order to form a ball grid array, it comprises one first soldered ball group and one second soldered ball group; Wherein this first soldered ball group pastes respectively to these ground connection weld pads, and this second soldered ball group pastes respectively to these to export into the signal weld pad.
The structure that the radiating block that the characteristics of TBGA encapsulation technology of the present invention are wherein adopted at what is one of the forming, and form a palladium plating layer with plating mode on it.This palladium plating layer can make packaged semiconductor wafer can be through palladium plating layer thus and radiating block is also comprised the what semiconductor wafer the earth current loop in, can not produce the floating earth phenomenon to allow in the mounting structure, therefore can guarantee the operating characteristics of packaged semiconductor wafer.In addition, this palladium plating layer also can strengthen radiating block and packing colloid between surface bonding strength, make packing colloid can not produce delamination.Moreover this film spherical grid array type semiconductor encapsulation manufacturing method adopts weld pad to replace the conduction plug that known technology adopts ball grid array is electrically connected to radiating block, can make whole encapsulation production process more simplify.
Essence technology contents of the present invention and embodiment are in detail openly drawn among this Figure of description of what with graphic mode.The content Description of these a little accompanying drawings is as follows:
Figure 1A to Figure 1B (known technology) is the structural profile schematic diagram, and it is in order to the TBGA encapsulating structure and the shortcoming thereof of No. the 5th, 844,168, United States Patent (USP) of explanation;
Fig. 2 A to Fig. 2 B (known technology) is the structural profile schematic diagram, and it is in order to the TBGA encapsulating structure and the shortcoming thereof of No. the 6th, 020,637, United States Patent (USP) of explanation;
Fig. 3 A to Fig. 3 C is the structural profile schematic diagram, wherein shows first embodiment of TBGA encapsulation technology of the present invention;
Fig. 4 A to Fig. 4 E is the structural profile schematic diagram, and it is in order to show the method for making of the film type substrate that TBGA encapsulation technology of the present invention is adopted;
Fig. 5 A to Fig., 5 C is the structural profile schematic diagram; wherein shows second embodiment of TBGA encapsulation technology of the present invention.10 ( heat sink ) 10a 1010b 1011 12 ( palladium plating ) 20 21 21a 2121b 2122 ( ) 22a 22’ 22a22b 23 ( solder mask ) 30 31 ( adhesive layer ) 40 51 52 60 60a 60b 70 ( encapsulant ) 110 ( heat spreader ) 112 119 ( vias ) 120 ( solder balls ) 120a ( solder balls ) 122 ( encapsulant ) 126’ ( bond wires ) 126" ( bond wires ) 127 ( adhesive layer ) 150 ( flex tape interconnect substrate ) 160 ( ground plane ) 164 ( ground ring ) 165 ( cupric oxide,CuO ) 310 ( stiffener ) 310a 310b 310c 315 316 320 TAB330 340 350 365 400 500
Below promptly in conjunction with the accompanying drawings, describe two different embodiment of TBGA encapsulation technology of the present invention in detail.First embodiment (Fig. 3 A to Fig. 3 C and Fig. 4 A to Fig. 4 E).
Below be Fig. 3 A to Fig. 3 C and Fig. 4 A to Fig. 4 E in the conjunction with figs., describe first embodiment of TBGA encapsulation technology of the present invention in detail.
Please three read Fig. 3 A, first step on the TBGA encapsulation technology what manufacture method of the present invention is at first precasting a radiating block (heat sink) 10, and it is to adopt a material with high-termal conductivity and hardness, for example is copper, makes in integrally formed mode.This radiating block 10 has a upper surface 10a and a lower surface 10b, and is formed with one on the lower surface 10b and downward openingly puts brilliant depression 11.
Please follow three and read Fig. 3 B, characteristics of TBGA encapsulation technology of the present invention are then carries out a plating palladium production process, in order to palladium metal (palladium) is electroplated on all surface of what radiating block 10, forms a palladium plating layer 12 by this.This palladium plating layer 12 has United States Patent (USP) the 6th, 020 simultaneously, the Au/Ag electrodeposited coating in No. 637 the TBGA encapsulation technology and the function of copper oxide; But its required plating palladium production process only needs a program step to finish, so manufacture method is more simple, and can not cause melanism handle production process the pollution problem that can cause.
Except above-mentioned radiating block 10, also must precast a film type substrate 20 and semiconductor wafer 30 simultaneously.Shown in Fig. 3 B, film type substrate 20 comprises that a film 21, a plurality of ground connection weld pad 22a, a plurality of output goes into a signal weld pad 22b and a weld pad cover curtain (solder mask) 23.The method for making of this film type substrate 20 is shown in Fig. 4 A to Fig. 4 E.
Please three read Fig. 4 A, first step in the method for making of the film type substrate 20 shown in Fig. 3 B is for providing a film 21, and its central authorities have an opening 21a, is putting brilliant depression 11 and be provided with in the radiating block 10 shown in corresponding what Fig. 3 B.This film 21 for example can be a polyimide (polyimide, PI) Zhi a film or a BT formula film or the bendable film of a single-layer type or the bendable film of a pair of stratotype.
Please follow three and read Fig. 4 B, next procedure is made equation for carrying out a contact window, (only demonstrates two contact windows among Fig. 4 B in order to form a plurality of contact window 21b on the precalculated position on film 21; But its actual number may be more).The position of these contact windows 21b is the precalculated position of the ground connection weld pad 22a shown in Fig. 3 B.
Please follow three and read Fig. 4 C, next procedure for example is a bronze medal layer (Cu), on the whole back side of what film 21 for forming a conductive layer 22.
Please follow three and read Fig. 4 D, next procedure in order to the specific part of excision conductive layer 22, makes the part that stays promptly go into signal weld pad 22b as ground connection weld pad 22a shown in Fig. 3 B and output for carrying out a selective ablation program.
Please follow three and read Fig. 4 E, next procedure is on the back side that forms a weld pad cover curtain 23 what films 21, signal weld pad 22b All Ranges is in addition gone in its back side upper what ground connection weld pad 22a and output that covers film 21, only exposes ground connection weld pad 22a and exports signal weld pad 22b.Then gold (Au) being electroplated what ground connection weld pad 22a and output goes on the exposed surface of signal weld pad 22b again.This promptly finishes the film type substrate 20 shown in Fig. 3 B.
Please follow three and read Fig. 3 C of front, it is fashionable that what carries out package group, be the lower surface 10b that at first film type substrate 20 is pasted by a conductivity mucigel 40 to radiating block 10, and make the opening 21a of film 21 wherein be aligned to the brilliant depression 11 of putting of what radiating block 10.Then semiconductor wafer 30 is pasted to the brilliant depression 11 of putting of radiating block 10 by a mucigel 31.
Settle the Hou of what location when semiconductor wafer 30, then carry out a bonding wire processing procedure this (wire-bonding process), wherein utilize one first bonding wire group 51 that semiconductor wafer 30 is electrically connected to the continuous conductive trace (not shown) that signal weld pad 22b is gone in output on the film type substrate 20; And utilize one second bonding wire group 52 that the ground connection weld pad (not shown) on the semiconductor wafer 30 is electrically connected on any point of palladium plating layer 12 simultaneously.Then carry out a packing colloid production process (encapsulation process), wherein a colloid encapsulating material is inserted to the brilliant depression 11 of putting of radiating block 10, use forming a packing colloid (encapsulant) 70, in order to coat semiconductor wafer 30 and all bonding wire groups 51,52.Hou is carried out a ball grid array production process, on the back side that forms a ball grid array 60 what film type substrates 20; This ball grid array 60 comprises one first soldered ball group 60a and one second soldered ball group 60b; Wherein the first soldered ball group 60a welds respectively and ties to ground connection weld pad 22a, and the second soldered ball group 60b then welds knot to output respectively and goes into signal weld pad 22b.This promptly finishes the production process of TBGA encapsulation technology of the present invention.
Above-mentioned connected mode can form one with the wafer earth current loop of radiating block 10 in being also included within; The starting point in this wafer earth current loop is a semiconductor wafer 30, then is connected to the earth point of printed circuit board (PCB) (not shown) in regular turn via the palladium plating layer 12 on the second bonding wire group 52, the radiating block 10 and body, conductivity mucigel 40, ground connection weld pad 22a and the first soldered ball group 60a.The body that also comprises radiating block 10 by this wafer earth current loop of what, therefore can not have the floating earth phenomenon in the encapsulating structure that TBGA encapsulation technology of the present invention is provided, also so not can cause excessive ground connection inductance and resistance, make the operating characteristics of packaged semiconductor wafer 30 can not be adversely affected.Second embodiment (Fig. 5 A to Fig. 5 C).
Below be Fig. 5 A to Fig. 5 C in the conjunction with figs., describe second embodiment of TBGA encapsulation technology of the present invention in detail.Among what Fig. 5 A to Fig. 5 C, the member identical with first embodiment is to represent with identical label.Shown in Fig. 5 A, second embodiment is different with first embodiment locates all to be formed with at least one perforation 22 ' on each ground connection weld pad 22a in the film type substrate 20 in what second embodiment only.
Then shown in Fig. 5 B, what is pasted film type substrate 20 to the process of radiating block 10, each ground connection weld pad 22a goes up formed perforation 22 ' and promptly can be used as a steam vent, in order to allow the air among the contact window 21b can be via wherein being pushed away (shown in the dotted arrow among Fig. 5 B), so that what conductivity mucigel 40 can roughly fill up whole contact window 21b fully by conductivity mucigel 40.In addition, conductivity mucigel 40 also roughly fills up whole perforation 22 ' fully.
Follow shown in Fig. 5 C, just but forming a ball grid array 60 on the back side of the ball grid array production process what film type substrate 20 that Hou continues, it comprises one first soldered ball group 60a and one second soldered ball group 60b; Wherein the first soldered ball group 60a weld respectively tie to ground connection weld pad 22a and wherein perforation 22 ', the second soldered ball group 60b then respectively weldering knot to output go into signal weld pad 22b.Other production process is all identical with first embodiment, therefore followingly will not do the explanation of heavy idol to it.
Combine, the invention provides a kind of TBGA encapsulation technology of novelty, the structure that the radiating block that its characteristics are wherein adopted at what is one of the forming, and be formed with a palladium plating layer on it.Compare with known technology, TBGA encapsulation technology of the present invention has following advantage.
The integral production method that first advantage is TBGA encapsulation technology of the present invention is more simplified.This is the needed assembly working of two-layer stratigraphic structure that is not needed known technology and adopted by the integrally formed radiating block of what; And plating palladium manufacture method only needs a program step to finish, and needn't need numerous and diverse step to finish as selectivity Au/Ag galvanizing process in the known technology and melanism handling procedure.Second advantage is that the plating palladium production process that TBGA encapsulation technology of the present invention is adopted can not pollute the surface of radiating block.The 3rd advantage is the palladium plating layer that TBGA encapsulation technology of the present invention is adopted, and the bond strength between itself and packing colloid is Cui quite, therefore can make packing colloid be difficult for producing delamination.
In addition, compare the TBGA encapsulation technology of No. the 6th, 020,637, what United States Patent (USP), TBGA encapsulation technology of the present invention does not adopt conduction plug and Hou continuous relevant wire mark program and reflow program by what, therefore can make whole encapsulation production process comparatively simplify and has more cost benefit.In addition, need not to carry out the required cleaning procedure of Hou of reflow program by what, therefore can not pollute substrate, the TBGA encapsulation unit that makes Hou finish does not have integrity problem.
Therefore TBGA encapsulation technology of the present invention has more progressive practicality than known technology.The above only is of the present invention than Cui embodiment, is not in order to limit the scope of essence technology contents of the present invention.Essence technology contents of the present invention is broadly to define in the following Patent right requirement of what.Any technology entity or method that other people are finished will be if with following Patent right requirement limited for identical or be a kind of change of equivalence, all will be regarded as containing among this scope of patent protection of what.
Claims (19)
1. film ball bar array type semiconductor package, it comprises:
(a) radiating block (10), it is made in integrally formed mode, has a upper surface (10a) and a lower surface (10b), wherein is formed with on the lower surface (10b) and puts brilliant depression (11);
(b) a palladium plating layer (12), it forms on all surface of this radiating block of what with plating mode;
(c) semiconductor wafer (30), it is putting in the brilliant depression (11) of arrangement this radiating block of what; This semiconductor wafer (30) has at least one earth point;
(d) a film type substrate (20), it is pasted on the lower surface (106) of this radiating block of what (10) by a conductivity mucigel (40); This film type substrate (20) comprising:
(d1) film (21) is formed with on it on a plurality of contact windows (216) what precalculated position;
(d2) a plurality of ground connection weld pads (22a), it forms respectively on a plurality of contact windows (21b) of this film of what (21), and electrically contacts with this conductivity mucigel (40) formation;
(d3) signal weld pad (22b) is gone in a plurality of outputs, and it forms respectively on the precalculated position on this film of what (20);
(d4) a weld pad cover curtain (23), it covers a surface of this film (21), but exposes those ground connection weld pads (22a) and those are exported into signal weld pad (22b);
(e) one first bonding wire group (51) is exported into signal weld pad (22b) in order to this semiconductor wafer (30) is electrically connected to those; And one second bonding wire group (52), in order to the earth point on this semiconductor wafer (30) is electrically connected to the palladium plating layer (12) on this radiating block;
(f) ball grid array (60), it comprises one first soldered ball group (60a) and one second soldered ball group (60b); Wherein this first soldered ball group (60a) pastes respectively to those ground connection weld pads (22a), and this second soldered ball group (60b) pastes respectively to those to export into signal weld pad (22b); And
(g) packing colloid (70), it forms putting in the brilliant depression (11) of this radiating block of what (10), in order to coat this semiconductor wafer (30) and this first and second bonding wire group (51,52).
2. semiconductor package as claimed in claim 1, wherein this film (21) is the film for a polyimide system.
3. semiconductor package as claimed in claim 1, wherein this film (21) is to be a BT formula film.
4. semiconductor package as claimed in claim 1, wherein this film (21) is to be the bendable film of a single-layer type.
5. semiconductor package as claimed in claim 1, wherein this film (21) is to be the bendable film of a pair of stratotype.
6. semiconductor package as claimed in claim 1, wherein to export into signal weld pad (22b) be to be copper for those ground connection weld pads (22a) and those.
7. film ball bar array type semiconductor packages manufacture method, it comprises following steps:
(1) precast a radiating block (10) sample, it is made in integrally formed mode, has a upper surface and a lower surface (10a), wherein is formed with on the lower surface (10b) and puts brilliant depression (11);
(2) carry out a plating palladium production process, use on all surface that forms palladium plating layer (12) this radiating block of what;
(3) a film type substrate (20) is pasted on the lower surface (10b) of this radiating block of what (10) by a conductivity mucigel (40); This film type substrate (20) comprising:
(3a) film (21) is formed with on it on a plurality of contact windows (21b) what precalculated position;
(3b) a plurality of ground connection weld pads (22a), it forms respectively on a plurality of contact windows (21b) of this film of what (21), and electrically contacts with this conductivity mucigel (40) formation;
(3c) signal weld pad (22b) is gone in a plurality of outputs, and it forms respectively on the precalculated position on this film of what (21);
(3d) weld pad cover curtain (23), it covers a surface of this film (21), but exposes those ground connection weld pads (22a) and those are exported into signal weld pad (22b);
(4) semiconductor wafer (30) is settled putting in the brilliant depression (11) of this radiating block of what (10); This semiconductor wafer (30) has at least one earth point;
(5) carry out a bonding wire production process, by one first bonding wire group (51) this semiconductor wafer (30) is electrically connected to those and exports, and one second bonding wire group (52) is electrically connected to palladium plating layer (12) on this radiating block (10) with the earth point on this semiconductor wafer (30) into signal weld pad (22b);
(6) carry out a packing colloid production process, use putting in the brilliant depression (11) of formation one packing colloid (70) this radiating block of what (10), in order to coat this semiconductor wafer (30) and this first and second bonding wire group (51,52); And
(7) carry out a ball grid array production process, in order to form a ball grid array (60), it comprises one first soldered ball group (60a) and one second soldered ball group (60b); Wherein this first soldered ball group (60a) pastes respectively to those ground connection weld pads (22a), and this second soldered ball group (60b) pastes respectively to those to export into signal weld pad (22b).
8. semiconductor packages manufacture method as claimed in claim 7, wherein the film (21) that is adopted in this step (3) is the film of a polyimide system.
9. semiconductor packages manufacture method as claimed in claim 7, wherein the film (21) that is adopted in this step (3) is a BT formula film.
10. semiconductor packages manufacture method as claimed in claim 7, wherein the film (21) that is adopted in this step (3) is the bendable film of a single-layer type.
11. semiconductor packages manufacture method as claimed in claim 7, wherein the film (21) that is adopted in this step (3) is the bendable film of a pair of stratotype.
12. semiconductor packages manufacture method as claimed in claim 7, wherein to go into signal weld pad (22b) be copper for ground connection weld pad (22a) described in this step (3) and output.
13. semiconductor packages manufacture method as claimed in claim 7, wherein be formed with at least one perforation (22 ') respectively on the ground connection weld pad (22a) described in this step (3), in order to what this film type substrate (20) is pasted to the process of this radiating block (10), as a steam vent, be filled up to those ground connection weld pads (22a) in order to this conductivity mucigel (40) of what and go up contact window (21b).
14. a film ball bar array type conductor encapsulation manufacturing method, it comprises following steps:
(1) precast a radiating block (10), it is made in integrally formed mode, has a upper surface (10a) and a lower surface (10b), wherein is formed with on the lower surface (10b) and puts brilliant depression;
(2) carry out a plating palladium production process, use on all surface that forms palladium plating layer (12) this radiating block of what;
(3) a film type substrate (20) is pasted on the lower surface (10b) of this radiating block of what (10a) by a conductivity mucigel (40); This film type substrate comprises:
(3a) film (21) is formed with on it on a plurality of contact windows (21b) what precalculated position;
(3b) a plurality of ground connection weld pads (22a), it forms respectively on a plurality of contact windows (21b) of this film of what (21), and electrically contacts with this conductivity mucigel (40) formation; Be formed with at least one perforation (22 ') respectively on those ground connection weld pads (22a), in order to what this film type substrate (20) is pasted to the process of this radiating block (10), as a steam vent, be filled up to those ground connection weld pads (22a) in order to this conductivity mucigel (40) of what and go up contact window;
(3c) signal weld pad (22b) is gone in a plurality of outputs, and it forms respectively on the precalculated position on this film of what (21);
(3d) weld pad cover curtain (23), it covers a surface of this film (21), but exposes those ground connection weld pads (22a) and those are exported into signal weld pad (22b);
(4) semiconductor wafer (30) is settled putting in the brilliant depression (11) of this radiating block of what (10); This semiconductor wafer (30) has at least one earth point;
(5) carry out a bonding wire production process, by one first bonding wire group (51) this semiconductor wafer (30) is electrically connected to those and exports, and one second bonding wire group (52) is electrically connected to palladium plating layer (12) on this radiating block (10) with the earth point on this semiconductor wafer (30) into signal weld pad (22);
(6) carry out a packing colloid production process, use putting in the brilliant depression (11) of formation one packing colloid (70) this radiating block of what (10), in order to coat this semiconductor wafer (30) and this first and second bonding wire group (51,52); And
(7) carry out a ball grid array production process, in order to form a ball grid array (60), it comprises one first soldered ball group (60a) and one second soldered ball group (60b); Wherein this first soldered ball group (60a) pastes respectively to those ground connection weld pads (22a), and this second soldered ball group (60b) pastes respectively to those to export into signal weld pad (22b).
15. semiconductor packages manufacture method as claimed in claim 14, wherein the film (21) that is adopted in this step (3) is the film for a polyimide system.
16. semiconductor packages manufacture method as claimed in claim 14, wherein the film (21) that is adopted in this step (3) is to be a BT formula film.
17. require 14 semiconductor packages manufacture method as patent, wherein the film (21) that is adopted in this step (3) is to be the bendable film of a single-layer type.
18. require 14 described semiconductor packages manufacture methods as patent, wherein the film (31) that is adopted in this step (3) is to be the bendable film of a pair of stratotype.
19. semiconductor package as claimed in claim 14, wherein to go into signal weld pad (22b) be to be copper for ground connection weld pad (22a) described in this step (3) and output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001324403A CN1156906C (en) | 2000-11-17 | 2000-11-17 | Film spherical grid array type semiconductor package structure and its making method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001324403A CN1156906C (en) | 2000-11-17 | 2000-11-17 | Film spherical grid array type semiconductor package structure and its making method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1354509A true CN1354509A (en) | 2002-06-19 |
| CN1156906C CN1156906C (en) | 2004-07-07 |
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ID=4595168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001324403A Expired - Fee Related CN1156906C (en) | 2000-11-17 | 2000-11-17 | Film spherical grid array type semiconductor package structure and its making method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1156906C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100378972C (en) * | 2005-03-08 | 2008-04-02 | 台湾积体电路制造股份有限公司 | Heat spreader and package structure utilizing the same |
| CN101483163B (en) * | 2008-01-07 | 2011-11-16 | 力成科技股份有限公司 | Window type ball grid array encapsulation construction and substrate thereof |
-
2000
- 2000-11-17 CN CNB001324403A patent/CN1156906C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100378972C (en) * | 2005-03-08 | 2008-04-02 | 台湾积体电路制造股份有限公司 | Heat spreader and package structure utilizing the same |
| CN101483163B (en) * | 2008-01-07 | 2011-11-16 | 力成科技股份有限公司 | Window type ball grid array encapsulation construction and substrate thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1156906C (en) | 2004-07-07 |
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