TW201011879A - Package substrate and fabrication method thereof - Google Patents

Package substrate and fabrication method thereof Download PDF

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Publication number
TW201011879A
TW201011879A TW097134028A TW97134028A TW201011879A TW 201011879 A TW201011879 A TW 201011879A TW 097134028 A TW097134028 A TW 097134028A TW 97134028 A TW97134028 A TW 97134028A TW 201011879 A TW201011879 A TW 201011879A
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Taiwan
Prior art keywords
substrate
layer
substrate body
package substrate
electrical contact
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TW097134028A
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Chinese (zh)
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TWI473221B (en
Inventor
Shih-Ping Hsu
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Phoenix Prec Technology Corp
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Publication of TW201011879A publication Critical patent/TW201011879A/en
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Publication of TWI473221B publication Critical patent/TWI473221B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Wire Bonding (AREA)

Abstract

The invention provides a package substrate and a method of fabricating the same, comprising providing a substrate body having electrical connecting pads formed on at least one surface thereof, wherein the electrical connecting pads are embedded in the substrate body and exposed from the substrate surface; disposing an insulating protection layer covering the substrate body and exposing the electrical connecting pads from the insulating protection layer; forming a conductive bump on each connecting pad and disposing a chemo-plating metal blocking layer on each of the bumps, thereby preventing the bonding between the pads and the bumps from decreasing and from generating copper displacement that affects reliability after long time use.

Description

201011879 九、發明說明： 【發明所屬之技術領域】 •• 本發明係有關於一種半導體結構及製法，尤指一種封 '裝基板及其製法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品之外型趨向輕薄 短小’在功能上則逐漸邁入高性能、高功能、高速度化的 研發方向。傳統上半導體封裝結構係將半導體晶片黏貼於 ❹封裝基板上’再進行打線接合（wire bonding)，或將半 導體晶片以覆晶接合（FI ip chip)電性連接至該封裝基 板，再於封裝基板之背面植以錫球以進行電性連接。 該打線接合係在一封裝基板上形成有相對應之打線 墊，將該半導體晶片以其非作用面接置於該封裝基板之置 晶區上’再以係如金線之導線以打線（wire b〇nding)電性 連接該封裝基板之打線墊及半導體晶片之電極墊，俾使該 半導體晶片電性連接至該封裝基板。 而覆晶式（Flip chip)半導體封裝技術為一種先進之 半導體封裝技術，在現行覆晶技術中，係於半導體積體電 路（Integrated Circuit ; 1C)晶片的表面上配置有電極焊 墊，並於該電極焊墊上形成有焊錫凸塊，且在一有機電路 封裝基板上形成有相對應之電性接觸墊與焊錫凸塊，俾提 供該晶片以電性接觸面朝下的方式設置於該封裝基板上。 請參閱第1圖，係為習知封裝基板上以打線及覆晶接 置半導體晶片之剖視圖；首先提供一基板本體1〇，該基 110889 5 201011879 板本體10具有相對應之置，晶面10 a及植球面1 〇 b，於該 置晶面10a具有複數覆晶墊101及打線墊1〇2,而該植球 •面l〇b具有複數植球墊1〇3,且該置晶面l〇a及植球面i〇b '分別設有第一絕緣保護層11a及第二絕緣保護層lib，該 第一絕緣保護層11a具有複數第一開孔ll〇a，以對應露 出各該覆晶墊101及打線墊102’而該第二絕緣保護層llb 具有複數第二開孔110 b，以對應露出各該植球塾1 〇 3，於 該打線墊102及植球墊103上形成有係為有機保焊劑 〇(organic solderability preservatives, 0SP)、化錫 (IT)、電鍍錄/金（Ni/Au)、或化鍍鎳/金（Ni/Au)之金屬層 12 ’而在該覆晶墊ιοί上形成有錫球13。 上述之覆晶墊101上的錫球13以覆晶方式對應接置 有第一半導體晶片14a，該第一半導體晶片14a具有作用 面141a及非作用面142a，於該作用面i4ia具有複數第 一電極墊143a，且在該第一電極墊14如上形成有焊錫凸 塊144a，使該焊錫凸塊144a接合該覆晶墊1〇1上之錫球 13’俾使該第一半導體晶片14a以覆晶電性連接至該基板 本體10;又於該第一半導體晶片14a之非作用面14託上 以結合材料15上接置第二半導體晶片Ub，該第二半導 體晶片14b具有作用面i4ib及非作用面142b，使該第二 半導體晶片14b以其非作用面142b藉由該結合材料15 接置於該第一半導體晶片14a之非作用面"肋上，於該 第二半導體晶片14b之作用面141b具有複數第二電極^ 143b’且該第二電極墊雇以係如金線之導線16電性連 110889 6 201011879 接至該打線墊l〇2，並y封膠材料17覆蓋於該第一絕緣 保護層11a、打線墊102、導線16、第一半導體晶片Ua 及第二半導體晶片14b上，藉以保護該打線墊1〇2、導線 16、第一半導體晶片14a及第二半導體晶片i4b。 惟’隨著電子裝置不斷朝向輕薄短小的方向推進，使 該些覆晶墊101、打線墊1〇2及植球墊1〇3之間的間距不 斷縮小’且該第一絕緣保護層丨丨a及第二絕緣保護層i ^ b 上的第一開孔1 l〇a及第二開孔丨1〇b ’亦相對縮小，使該 〇植球墊103露出之面積逐漸縮小，導致該植球墊1〇3與錫 球13之間的結合面積縮小，因而降低該植球塾1 〇 3與錫 球13之間的結合力，使該錫球丨3容易脫落而影響電性連 接之可靠度。另外，該覆晶墊101露出之面積逐漸縮小， 也使得該錫球13及覆晶墊ιοί之間結合性降低，而影響 電性連接之可靠度。 又該打線墊102及植球墊1〇3上形成之金屬層12係 ❹為化錫（it)、電鍍鎳/金（Ni/Au)、或化鍍鎳/金（Ni/Au) 等，或有機保焊劑（organic solderability preservatives, OSP) ’而該打線墊i〇2及植球墊i〇3通 常係為銅，若使用有機保焊劑或化錫，經長期使用該金屬 層12易產生銅遷移（Copper migrati〇n)效應，而產生硬 脆之介金屬化合物（Intermetallic Compound，IMC)，導 致該介金屬化合物不斷增厚或向外延伸，對於長期使用則 會造成短路或是延伸之介金屬互相干擾，而發生產品可靠 度降低。 ° 110889 7 201011879 電鍍錄/金則因電錢面積大小不同，而易造成厚度 •:生不L且金厚度較厚，不利於覆晶接合，尤其是在小開 :二之電1±連接塾上更易產生掉球，另外使用化錄/金雖無 月’J返問題，但其本身錄品質問題，而易產生掉球問題，而 不利於應用於電子產品上。 _因此’鑒於上述之問題’由於電子裝置不斷朝向輕薄 私小的方向推進’使該植球墊與錫球之間的結合力降低， 而影響電性連接之可靠度，以及形成於該打線塾及植球塾 〇上之金屬層易產生銅遷移現象，實已成目前電 者亟欲解決的課題。 業 【發明内容】 鑑於前述習知技術之缺失，本發明之主要目的係在提 供一種封裝基板及其製法，能避免絕緣保護層之開孔及電 性接觸墊縮+導致結合性降，而影響電性連接之缺失。 本發明之又一目的係在提供一種封裝基板及其製 法，能避免產生銅遷移現象，以降低封裝基板長期使用可 w靠度之影響。 本發明之另一目的係在提供一種封裝基板及其製 法’以提高植球墊與錫球之間的結合能力。 為達上述之目的，本發明之封裝基板，係包括：基板 本體，至少一表面具有複數電性接觸塾，且該電性接觸墊 嵌埋於該基板本體中，並顯露於該基板本體表面；絕緣保 ”蔓層’ k覆6又於該基板本體上’並露出該些電性接觸墊； 導電凸塊，係設於該電性接觸墊上；以及化鍍金屬阻障 110889 8 201011879 層 設於該導電凸塊上，且該化鍍金屬阻障層係為鎳 / #巴/金層。 依上述之封裝基板，該基板本體係為具有核心層之美 '板本體或無核心層之基板本體。 a 土 又依上述之封裝基板，該基板本體復包括線路，且該 線路係喪埋於該基板本體中’並顯露於該基板本體表^ 該電性接觸墊表面係低於、高於或齊平於基板本體表面； 該絕緣保護層具有一開口，以露出該些電性接觸墊； ©絕緣保護層具有複數開孔，以對應露出各該電性接觸塾二 且該絕緣保護層係為聚亞醯胺樹脂（PI，p〇ly_iroide)、介 電增層膜（ABF，Ajinomoto Build_up Film)、環 二 (Epoxy)或防焊層。 曰 ,依上述之結構，該導電凸塊係為銅；復包括焊接材 料’係形成於該化鑛金屬阻障層上。 本發明復提供一種封裝基板.製法，係包括：提供一基 板本體’該基板本體之至少-表面具有複數電性接觸^ 且該電性接觸墊嵌埋於該基板本體中，並顯露於該基板本 體表面；於該基板本體上形成有絕緣保護層，並露出咳些 電性接觸墊；於該絕緣保護層及電性接觸墊上形成有”導^ 層；於該導電層上形成有阻層，且該阻層中形成有貫穿Z 開口區，以對應露出該電性接觸墊上之部份導電層；'於該 開口區中之導電層上形成有導電凸塊；移除該阻層及』 所覆蓋之導電層；以及於該導電凸塊上形成有化鍍金屬 阻障層，該化鍍金屬阻障層係為鎳/把/金層。 110889 9 201011879 本發明再提供一種封裝基板製法，係包括：提供一基 板本體，該基板本體之至少一表面具有複數電性接觸墊， ••且該電性接觸墊嵌埋於該基板本體中，並顯露於該基板本 ，體表面；於該基板本體上形成有導電層；於該導電層上 形成有阻層，且該阻層中形成有貫穿之開口區，以對^露 出該電性接觸墊上之部份導電層；於該開口區中之導電 -層上形成有導電凸塊；移除該阻層及其所覆蓋之導電 ··層；於該基板本體上形成有絕緣保護層，並露出該些電性 0接觸墊；以及於該導電凸塊上形成有化鍍金屬阻障層，且 該化鍍金屬阻障層係為鎳/鈀/金層。 日 本發明又提供一種封裝基板製法，係包括：提供一基 板本體’該基板本體之至少一表面具有複數電性接觸塾土， 且該電性接觸墊嵌埋於該基板本體中，並顯露於該基板本 f表面，於該基板本體上形成有阻層，且該阻層中形成有 貝穿之開口區，以對應露出該電性接觸藝；於該開口區中 .電性接觸墊上化鑛方式形成有導電凸塊；移除該阻 ，於該基板本體上形成有絕緣保護層，並露出該些電性 接觸墊；以及於該導電凸境上形成有化鐘金屬阻障層，且 該化鍍金屬阻障層係為鎳/鈀/金層。 ^上奴各封裝基板製法，絲板本體係為具有核心 曰之基板本體或無核心層之基板本體。 且哕：:二各封裝基板製法’該基板本體復包括線路， :係肷埋於該基板本體中’並顯露於該基板本體表 生接觸塾表面係低於、高於或齊平於基板本體表 110889 10 201011879 面.，該緣保護層形成有—開σ，以露出該些電性接觸 墊；或該絕緣保護層形成有複數開孔，以對應露出各該電 •性接觸塾，該、絕、緣保護層係、4聚亞釀胺樹脂（π :Poly-!，）、介 t 增層膜 _，Ajin_〇 ilm)、環氧樹脂（Ep0xy)或防烊層。 • ^述之製法’該導電凸塊係為鋼；復包括於該化錢金 •屬阻障層上形成有焊接材料。 价封裝基板及其製法’係於該電性接觸墊上先 ΊΓ提導電凸塊’且該導電凸塊與電性接觸塾係為相 =免::：電性接觸塾與導電凸塊之間的結合性， 致Μ性降低、，保4層之開孔及電性接觸墊逐漸縮小導 U降低’而影響電性連接之缺失，·又該 ::有係為鎳，/金層之化鍍金屬阻障層，以避免產生銅 遷移，而影響長期使用 避免產生銅 提高植球墊上之導雷& 此糟由該化鍍金屬層 【實施方式】 塊與焊接材料的結合能力。 ❹，：:係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可 之只施方 瞭解本發明之其他優點與功效。胃所揭不之内容輕易地 [第一實施例] 晴參閱第2Α至^ 4 的剖視圖。 ，糸為本發明封裝基板及其製法 如第 2A 及 2Α，ϋΐ^ί·- 本體2。之至少=:，提供-基板本體2〇,該基板 表面具有複數係為銅之電性接觸墊 110889 11 201011879 201，且該電性接觸墊2〇1嵌埋於該基板本體2〇中，並顯 露於該基板本體20表面，如第2A圖所示；或該基板本體 .20之至少一表面具有複數電性接觸墊201及線路202,其 中該線路202係嵌埋於該基板本體2〇中，並顯露於該基 板本體20表面，如第2A，圖所示；之後以第^圖所示之 結構作說明。前述之該基板本體2〇係為具有核心層之基 •板本體或無核心層之基板本體’又該電性接觸墊2〇1表面 係低於、高於（圖未示）或齊平於該基板本體2〇表面。 ©十如第2B及2B，圖所示，於該基板本體2〇上形成絕緣 呆護層21，且該絕緣保護層21形成一開口 21 〇，以露出 該些電^接觸墊2〇1，如第2B圖所示；或該絕緣保護層 $成複數開孔210’，以對應露出各該電性接觸墊2〇 ^， 第2B圖所示，之後以第圖所示之結構作說明丨其 匕X、·巴緣保護層21可為感光性或非感光性之聚亞醯胺 = (PI’ Poly_imide)、介電增層膜（abf，幻 _ d up Fi lm)、環氧樹脂（Ep0Xy)或防焊層。 如第2C圖所示，於該絕緣保護層21及電性接觸塾 阻展上9形成有導電層22;接著，於該導電層22上形成有 庫1山3，且該阻層23中形成有貫穿之開口區230,以對 备出該些電性接觸墊2〇1上之部份導電層22。 成有：ί 2D圖所示’於該開口區230中之導電層22上形 銅之導電凸塊24;其中，該導電凸塊24之寬度 於=稭由控制該阻層23之開口區咖大小，以形成大 …小於該電性接觸墊201寬度之導電凸塊M。 110889 12 201011879 如ίΓΛ所/，移除該阻層23及其所覆蓋之導電芦 22，以露出該導電凸塊24。 守电層 •如第2F圖所示，於該導電凸塊Μ上形成有係為鋅/ 鈀/金（Ni/M/Au)層之化鍍金屬阻障層25。令係為鎳/ •如第2G圖所心於該化鍍金屬轉層25上復可 有焊接材料26;其中，該焊錫材料26係為錫與銀= -·銅、鋅或絲所組群組之一者之混合金屬。 -/ [第二實施例] ❹請參閱第3A至3E圖’係為本發明之另一實 方法，與前一實施不同處在該基彳 I扳本體之電性接觸墊上先 形成有導电凸塊，再於該基板本體 露出該導電凸塊。 &本體场成絕緣保護層，並 如弟3A圖所示，首弈据也 千夕紝姐^ 盲先鍉供一係如苐2A或2A，圖所 不之、4，並以第2A圖所示之 钱 體20上形成有導電声 於該基板本 古“ 接者’於該導電層22上形成 有阻層，且該阻層23令形 + ★ ❹對廊霞山w + 甲形成有貝牙之開口區230，以 露出該％性接觸墊201上之部份導電層22。 成有ΓΓ 3B圖所示，於該開口區230中之導電層22上形 成有係為銅之導電凸塊24。 以，==戶1示’移_且層23及其所覆蓋之導電層 路出該導電凸塊24。 緣保及3D,圖所示’於該基板本體20上形成有絕 露出=絕緣保護層2】形成有—開口210,以 电塊24 ’如第3D圖所示；或該絕緣保護層 110889 13 201011879 21形成有複數開孔210’，以對應露出各該電性接觸墊 2(Π ’如第3D’圖所示；之後以第3D圖所示之結構作說 ·.明；其中’該絕緣保護層21可為感光性或非感光性材料 '之聚亞醯胺樹脂（PI， P〇1y-imide)、介電增層膜 (ABF，Ajinomoto Build-up Film)、環氧樹脂（如〇灯）或防 焊層。 • 如帛3E圖所示，於該導電凸塊24上形成有化錢金屬 / 阻障層25。 ©[第三實施例] 請參閱第4A至4E圖，係為太路阳★ p — 货'两本發明之另一實施製造 方法，與前一實施不同處在於該導 %、吻等包凸塊24係以化學沉 請參閱第4A圖，提供一係如第2A或2A，圖所示之社 構’並以f 2A ®㈣之結構作朗；於縣板本體2°〇 上形成有阻層23,且該阻層23令形成有貫穿之開口區 230 ’以對應露出該電性接觸墊2〇1。 1如f 4B圖所示，於該開口㊣23〇中之電性接觸墊2〇1 上以化學沉積方式形成有係為銅之導電凸塊24。 如第4C圖所*，移除該阻層23,以露出該導電凸塊 24 ° 如第4D及4D’圖所示，於兮其此士她 於該基板本體20上形成有絕 緣保護層21 ’且該絕緣保護層21彡 艾屑ζ 1开> 成有一開口 21 〇，以 露出該些電性接觸墊2〇1，如第41) . # a。 $弟4D圖所不；或該絕緣保 4層21形成有複數開孔21〇,，以斟庵+ M對應路出各該電性接觸 110889 14 201011879 墊201，如第4D，圖所示；之後以第4D圖所示之結構作說 明，其中，该絕緣保護層21可為感光性或非感光性材料 •之I亞醯胺樹脂（PI，p〇ly_imide)、介電增層膜（abf -Ajinomoto Build-upFilm)、環氧樹脂（EpoXy)或防焊層。 如第4E圖所示，於該導電凸塊24上形成有化鍍金屬 阻障層25。 本發明復提供一種封裝基板，係包括：基板本體2〇， 至>、表面具有複數電性接觸塾201，且該電性接觸墊 ©201嵌埋於該基板本體2〇中，並顯露於該基板本體2〇表 面；絕緣保護層21，係覆設於該基板本體2〇上，並露出 該些電性接觸墊201;導電凸塊24,係設於該電性接觸墊 201上，以及化鍍金屬阻障層25,係覆設於該導電凸塊 24上，該化鍍金屬阻障層25係為鎳/鈀/金層。 依上述之封裝基板，該基板本體2〇係為具有核心層 之基板本體或無核心層之基板本體，又該電性接觸墊2〇1 ❹表面係低於、高於（圖未示）或齊平於基板本體2〇表面。 依上述之封裝基板，該基板本體2〇復包括線路2〇2, 且該線路202係嵌埋於該基板本體2〇中，並顯露於該基 板本體20表面；該絕緣保護層21具有一開口 21〇，以露 出該些電性接觸墊201;或該絕緣保護層21具有複數開 孔210’ ’以對應露出各該電性接觸墊2〇1;其中，該絕緣 保瘦層21可為感光性或非感光性材料之聚亞醯胺樹脂 (PI, Poly-imide)、介電增層膜（ABF，Ajin〇m〇t〇Buiid_叩201011879 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor structure and a method of manufacturing the same, and more particularly to a packaged substrate and a method of fabricating the same. [Prior Art] With the rapid development of the electronics industry, the appearance of electronic products tends to be thin and light, and the function is gradually entering the development direction of high performance, high functionality, and high speed. Conventionally, a semiconductor package structure is to adhere a semiconductor wafer to a package substrate, and then wire bonding, or electrically connecting the semiconductor wafer to the package substrate, and then to the package substrate. Tin balls are implanted on the back for electrical connection. The wire bonding is formed by forming a corresponding wire pad on a package substrate, and the semiconductor wafer is placed on the crystallographic region of the package substrate with its non-active surface, and then wire is bent by a wire such as a gold wire (wire b) The bonding pad of the package substrate and the electrode pad of the semiconductor chip are electrically connected to the package substrate. Flip chip semiconductor packaging technology is an advanced semiconductor packaging technology. In the current flip chip technology, an electrode pad is disposed on the surface of a semiconductor integrated circuit (1C) wafer. Solder bumps are formed on the electrode pads, and corresponding electrical contact pads and solder bumps are formed on an organic circuit package substrate, and the wafer is provided on the package substrate with the electrical contact surface facing downward. on. Please refer to FIG. 1 , which is a cross-sectional view of a semiconductor wafer mounted on a conventional package substrate by wire bonding and flip chip bonding. First, a substrate body 1 提供 is provided. The substrate 110889 5 201011879 has a corresponding body, the crystal face 10 a and the spherical surface 1 〇b, the crystal plane 10a has a plurality of flip pads 101 and a wire pad 1〇2, and the ball/face l〇b has a plurality of ball pads 1〇3, and the crystal plane The first insulating protective layer 11a and the second insulating protective layer 11b are respectively provided with a plurality of first openings 〇a to correspondingly expose the respective covers. The pad 101 and the wire pad 102', and the second insulating layer 11b has a plurality of second openings 110b for correspondingly exposing the ball 塾1 〇3, and the wire pad 102 and the ball pad 103 are formed on the wire pad 102 and the ball pad 103. It is an organic solderability preservatives (0SP), tin (IT), electroplated/gold (Ni/Au), or nickel/gold (Ni/Au) metal layer 12' A solder ball 13 is formed on the crystal pad ιοί. The solder ball 13 on the flip chip 101 is connected to the first semiconductor wafer 14a in a flip chip manner. The first semiconductor wafer 14a has an active surface 141a and an inactive surface 142a. The active surface i4ia has a plurality of first surfaces. The electrode pad 143a, and the solder bump 144a is formed on the first electrode pad 14 such that the solder bump 144a is bonded to the solder ball 13' on the flip chip 1?, so that the first semiconductor wafer 14a is overcoated. The second semiconductor wafer Ub is electrically connected to the substrate body 10; and the second semiconductor wafer Ub is connected to the non-active surface 14 of the first semiconductor wafer 14a. The second semiconductor wafer 14b has an active surface i4ib and a non- The active surface 142b is such that the second semiconductor wafer 14b is attached to the non-active surface of the first semiconductor wafer 14a by the bonding material 15 with its non-active surface 142b, and functions as the second semiconductor wafer 14b. The surface 141b has a plurality of second electrodes ^ 143b' and the second electrode pads are electrically connected to the wire pad 110 by a wire 16 such as a gold wire. The y sealing material 17 is covered by the surface. An insulating protective layer 11a, a wire pad 102, a guide 16, the first semiconductor wafer and second semiconductor wafer Ua 14b, so as to protect the wire bonding pads 1〇2, lead 16, first semiconductor wafer and second semiconductor wafer 14a i4b. However, as the electronic device continues to move toward a light and short direction, the spacing between the flip chip pads 101, the wire bonding pads 1〇2 and the ball pad 1〇3 is continuously reduced, and the first insulating protective layer 丨丨The first opening 1 l〇a and the second opening 丨1〇b' on the a and the second insulating protective layer i ^ b are also relatively narrowed, so that the exposed area of the implant ball pad 103 is gradually reduced, resulting in the planting The bonding area between the ball pad 1〇3 and the solder ball 13 is reduced, thereby reducing the bonding force between the ball 塾1〇3 and the solder ball 13, so that the solder ball 丨3 is easily detached and affects the reliability of the electrical connection. degree. In addition, the exposed area of the flip chip 101 is gradually reduced, which also reduces the bond between the solder ball 13 and the flip chip ιοί, and affects the reliability of the electrical connection. Further, the metal layer 12 formed on the wire pad 102 and the ball pad 1〇3 is made of tin (it), electroplated nickel/gold (Ni/Au), or nickel/gold (Ni/Au). Or organic solderability preservatives (OSP)' and the wire mat i〇2 and the ball pad i〇3 are usually copper. If an organic soldering agent or tin is used, the metal layer 12 is prone to copper when used for a long time. The migration (Copper migrati〇n) effect, resulting in a hard and brittle intermetallic compound (IMC), resulting in the thickening or outward extension of the intermetallic compound, causing short-circuit or extended intermetallics for long-term use. Interference with each other, and product reliability is reduced. ° 110889 7 201011879 Plating record / gold is different due to the size of the electricity money, and easy to cause thickness •: raw L and thick gold, is not conducive to flip chip bonding, especially in the small opening: two electric 1 ± connection 塾It is easier to produce the ball, and the use of the record/gold is not a problem, but it has a quality problem, and it is easy to cause the ball to fall, which is not conducive to electronic products. _ Therefore 'in view of the above problem 'because the electronic device continues to move toward a light and small direction, the 'the bonding force between the ball pad and the solder ball is reduced, which affects the reliability of the electrical connection, and is formed on the wire 塾And the metal layer on the ball is easy to produce copper migration phenomenon, which has become a problem that the current electrician wants to solve. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide a package substrate and a method for fabricating the same, which can avoid the opening of the insulating protective layer and the electrical contact padding + resulting in a decrease in bonding, and affecting The lack of electrical connections. Still another object of the present invention is to provide a package substrate and a method of fabricating the same, which can avoid copper migration and reduce the influence of long-term use of the package substrate. Another object of the present invention is to provide a package substrate and method thereof for improving the bonding ability between the ball pad and the solder ball. For the above purpose, the package substrate of the present invention comprises: a substrate body, at least one surface having a plurality of electrical contacts, and the electrical contact pads are embedded in the substrate body and exposed on the surface of the substrate body; Insulation protection "vine layer" k over 6 is on the substrate body 'and exposes the electrical contact pads; conductive bumps are provided on the electrical contact pads; and metallization barriers 110889 8 201011879 The metallized barrier layer is a nickel/#bar/gold layer. According to the package substrate, the substrate is a substrate body having a core layer or a core layer without a core layer. a soil according to the above package substrate, the substrate body comprises a circuit, and the circuit is buried in the substrate body 'and exposed on the substrate body surface ^ the electrical contact pad surface is lower than, higher than or Flat on the surface of the substrate; the insulating protective layer has an opening to expose the electrical contact pads; the insulating protective layer has a plurality of openings to correspondingly expose the electrical contacts and the insulating protective layer is agglomerated Aachen Resin (PI, p〇ly_iroide), dielectric build-up film (ABF, Ajinomoto Build_up Film), Epoxy or solder mask. 曰, according to the above structure, the conductive bump is copper; The material is formed on the metallized metal barrier layer. The invention further provides a package substrate. The method comprises: providing a substrate body, wherein at least a surface of the substrate body has a plurality of electrical contacts and the electrical contact The pad is embedded in the substrate body and exposed on the surface of the substrate body; an insulating protective layer is formed on the substrate body, and the electrical contact pads are exposed; and the insulating protective layer and the electrical contact pad are formed on the substrate a conductive layer is formed on the conductive layer, and a through-Z opening region is formed in the resist layer to correspondingly expose a portion of the conductive layer on the electrical contact pad; 'on the conductive layer in the open region Forming a conductive bump; removing the resist layer and the conductive layer covered by the conductive layer; and forming a metallization barrier layer on the conductive bump, the metallized barrier layer being a nickel/bar/gold layer . 110889 9 201011879 The invention further provides a method for manufacturing a package substrate, comprising: providing a substrate body, wherein at least one surface of the substrate body has a plurality of electrical contact pads, and the electrical contact pads are embedded in the substrate body, And exposing on the substrate body surface; forming a conductive layer on the substrate body; forming a resist layer on the conductive layer, and forming an opening region penetrating through the resist layer to expose the electrical contact a portion of the conductive layer on the pad; a conductive bump formed on the conductive layer in the open region; removing the resist layer and the conductive layer covered thereon; forming an insulating protective layer on the substrate body, and Exposing the electrical 0 contact pads; and forming a metallization barrier layer on the conductive bumps, and the metallization barrier layer is a nickel/palladium/gold layer. The Japanese invention further provides a method for manufacturing a package substrate, comprising: providing a substrate body, wherein at least one surface of the substrate body has a plurality of electrical contact bauxite, and the electrical contact pad is embedded in the substrate body and exposed in the a resistive layer is formed on the surface of the substrate, and an opening region of the barrier layer is formed in the resist layer to correspondingly expose the electrical contact art; in the open region, the electrochemical contact pad is on the mineralization mode Forming a conductive bump; removing the resistor, forming an insulating protective layer on the substrate body, and exposing the electrical contact pads; and forming a chemical barrier layer on the conductive bump, and forming The metallized barrier layer is a nickel/palladium/gold layer. ^The method of making each package substrate, the silk plate system is a substrate body having a core substrate or a substrate body without a core layer. And 哕:: two package substrate manufacturing method 'the substrate body includes a circuit, the system is buried in the substrate body' and is exposed on the substrate body, the surface of the contact surface is lower than, higher than or flush with the substrate body Table 110889 10 201011879, the edge protection layer is formed with - σ to expose the electrical contact pads; or the insulating protection layer is formed with a plurality of openings to correspondingly expose each of the electrical contact pads, Absolute protective layer, 4-meridene amine resin (π: Poly-!,), t-additive film _, Ajin_〇ilm), epoxy resin (Ep0xy) or anti-mite layer. • The method described in the description of the conductive bump is steel; the complex is included in the chemical gold barrier layer formed with solder material. The valence package substrate and the manufacturing method thereof are based on the electrical contact pad, and the conductive bumps are first extracted and the conductive bumps are electrically contacted with the lanthanum phase: a::: electrical contact between the 塾 and the conductive bump Bonding, reduced cariogenicity, and the opening of the 4 layers and the electrical contact pads gradually reduce the U-lowering' and affect the lack of electrical connection. · The:: The nickel plating, the gold layer plating Metal barrier layer to avoid copper migration, which affects long-term use to avoid copper to improve the lightning strike on the ball pad. This is the ability of the metallization layer to bond with the solder material. The present invention is described by way of specific embodiments, and those skilled in the art can understand the other advantages and functions of the present invention. The contents revealed by the stomach are easily [First Embodiment] See the cross-sectional views of Figs. 2 to 4. , 糸 is the package substrate of the present invention and its preparation method, such as the 2A and 2Α, 本体^ί·- body 2. At least =:, providing a substrate body 2?, the surface of the substrate has a plurality of copper-based electrical contact pads 110889 11 201011879 201, and the electrical contact pads 2〇1 are embedded in the substrate body 2〇, and The surface of the substrate body 20 is exposed as shown in FIG. 2A; or at least one surface of the substrate body 20. has a plurality of electrical contact pads 201 and a line 202, wherein the line 202 is embedded in the substrate body 2 And is exposed on the surface of the substrate body 20, as shown in FIG. 2A, and is illustrated by the structure shown in FIG. The substrate body 2 is a substrate body having a core layer or a substrate body having no core layer, and the surface of the electrical contact pad 2〇1 is lower than, higher than (not shown) or flushed with The substrate body 2 has a surface. 10, as shown in FIG. 2B and FIG. 2B, an insulating protective layer 21 is formed on the substrate body 2, and the insulating protective layer 21 forms an opening 21 以 to expose the electrical contact pads 2〇1, As shown in FIG. 2B; or the insulating protective layer $ is formed into a plurality of openings 210' to expose the respective electrical contact pads 2, as shown in FIG. 2B, and then illustrated by the structure shown in the figure. The 匕X,·Bal edge protective layer 21 may be photosensitive or non-photosensitive polyamidoamine (PI' Poly_imide), dielectric build-up film (abf, illusion d up Fi lm), epoxy resin ( Ep0Xy) or solder mask. As shown in FIG. 2C, a conductive layer 22 is formed on the insulating protective layer 21 and the electrical contact barrier 9; then, a reservoir 1 is formed on the conductive layer 22, and the resist layer 23 is formed. There is a through-opening area 230 for preparing a portion of the conductive layer 22 on the electrical contact pads 2〇1. The conductive bump 24 is formed on the conductive layer 22 in the open region 230 as shown in FIG. 2; wherein the width of the conductive bump 24 is controlled by the opening of the resist layer 23 The size is to form a conductive bump M that is larger than the width of the electrical contact pad 201. 110889 12 201011879 The resist layer 23 and the conductive reed 22 covered thereby are removed to expose the conductive bumps 24. Suppressive Layer • As shown in Fig. 2F, a metallized barrier layer 25 of a zinc/palladium/gold (Ni/M/Au) layer is formed on the conductive bump. The order is nickel / • as shown in Figure 2G, the metallized metal layer 25 may be provided with a solder material 26; wherein the solder material 26 is tin and silver = - copper, zinc or silk A mixed metal of one of the groups. - / [Second Embodiment] Please refer to FIGS. 3A to 3E as another embodiment of the present invention. Different from the previous embodiment, the conductive contact pads of the base body are first formed with conductive The bumps expose the conductive bumps on the substrate body. & Ontology field into an insulating protective layer, and as shown in the brother 3A, the first game is also a thousand 纴 纴 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The illustrated body 20 is formed with a conductive sound on the substrate. The ancient "connector" forms a resist layer on the conductive layer 22, and the resist layer 23 is shaped + ★ ❹ 廊 廊 霞 w w + + + An open area 230 of the shell tooth to expose a portion of the conductive layer 22 on the % contact pad 201. As shown in FIG. 3B, a conductive bump is formed on the conductive layer 22 in the open area 230. Block 24. The == 1 indicates the 'shift' and the layer 23 and the conductive layer covered by the layer exit the conductive bump 24. The edge and 3D, the figure shown on the substrate body 20 is exposed. The insulating protective layer 2 is formed with an opening 210, and the electric block 24' is as shown in FIG. 3D; or the insulating protective layer 110889 13 201011879 21 is formed with a plurality of openings 210' to correspondingly expose the respective electrical contact pads. 2 (Π ' as shown in Fig. 3D'; after that, the structure shown in Fig. 3D is shown; wherein 'the insulating protective layer 21 can be photosensitive or non-photosensitive material' Melamine resin (PI, P〇1y-imide), dielectric interlayer film (ABF, Ajinomoto Build-up Film), epoxy resin (such as xenon lamp) or solder mask. • As shown in Figure 3E, A chemical metal/barrier layer 25 is formed on the conductive bump 24. © [Third embodiment] Please refer to Figures 4A to 4E, which are another embodiment of the present invention. The manufacturing method differs from the previous embodiment in that the guide bumps, kisses, and the like include a chemical sink. Referring to FIG. 4A, a system such as 2A or 2A is shown, and the structure is shown as f 2A. The structure of (4) is made of Lang; a resist layer 23 is formed on the 2° plate of the plate body, and the resist layer 23 is formed with an opening region 230' penetrating to expose the electrical contact pad 2〇1. As shown in FIG. 4B, a copper-plated conductive bump 24 is formed by chemical deposition on the electrical contact pad 2〇1 in the positive 23〇 of the opening. As shown in FIG. 4C, the resist layer 23 is removed. In order to expose the conductive bump 24 ° as shown in FIGS. 4D and 4D', the insulating layer 21 ' is formed on the substrate body 20 and the insulating protective layer 21 is 彡 ζ 1 open >; to make An opening 21 〇 to expose the electrical contact pads 2〇1, such as 41). # a. $弟4D图不; or the insulation 4 layer 21 is formed with a plurality of openings 21〇, 斟庵+M corresponds to each of the electrical contacts 110889 14 201011879 pad 201, as shown in FIG. 4D, and is illustrated by the structure shown in FIG. 4D, wherein the insulating protective layer 21 may be photosensitive or non- Photosensitive material • Imine amine resin (PI, p〇ly_imide), dielectric build-up film (abf-Ajinomoto Build-up Film), epoxy resin (EpoXy) or solder mask. As shown in Fig. 4E, a metallization barrier layer 25 is formed on the conductive bumps 24. The present invention further provides a package substrate, comprising: a substrate body 2, to >, a surface having a plurality of electrical contacts 201, and the electrical contact pads © 201 are embedded in the substrate body 2 and exposed The surface of the substrate body 2; the insulating protective layer 21 is disposed on the substrate body 2, and exposes the electrical contact pads 201; the conductive bumps 24 are disposed on the electrical contact pads 201, and The metallized barrier layer 25 is coated on the conductive bumps 24, and the metallized barrier layer 25 is a nickel/palladium/gold layer. According to the above package substrate, the substrate body 2 is a substrate body having a core layer or a substrate body having no core layer, and the surface of the electrical contact pad 2低于1 is lower than or higher than (not shown) or It is flush with the surface of the substrate body 2 . According to the above package substrate, the substrate body 2 includes a line 2〇2, and the line 202 is embedded in the substrate body 2 and exposed on the surface of the substrate body 20; the insulating protection layer 21 has an opening. 21〇, to expose the electrical contact pads 201; or the insulating protective layer 21 has a plurality of openings 210 ′′ to correspondingly expose the electrical contact pads 2〇1; wherein the insulating thin layer 21 can be photosensitive Poly-imide resin (PI, Poly-imide) or dielectric build-up film (ABF, Ajin〇m〇t〇Buiid_叩)

Film)、環氧樹脂（Epoxy)或防焊層。 110889 15 201011879 又依上述之結構，該導電凸塊24係為銅；復包括焊 接材料26 ’係形成於該化鍍金屬阻障層25上。 ' 言青參閱第5圖，於該基板本體20之另一表面具有 :數植球墊203,且於該表面上形成有另一絕緣保護層 21’ ’該絕緣保護層21，並露出該些植球墊2〇3，且於該植 球勢203上形成有錫球27; $提供一半導體晶片w，該 .半導體晶片31具有複數電極墊311，於該電極墊3ιι ^ -·形成有凸塊312，令該凸塊312以覆晶方式對應電性連接 ©該基板本體20之焊接材料26。 本發明之封裝基板及其製法，係於該電性接觸墊上先 成該導電凸塊’且該導電凸塊與電性接觸塾係為相 。材二提馬該電性接觸墊與導電凸塊之間的結合性， 且該半導體晶片以其焊錫凸塊電性連接至該導電凸塊，俾 緣保護層之開孔及電性接觸墊逐漸縮小導致 二㈣響電性連接之缺失；又該導電凸塊、打 ❹避免產二墊上形成有係為鎳/鈀/金層之化鍍金屬層，以 且遷λ現象，俾能降低封裝基板長期使用可靠度 與焊接材料：=力鑛仙 用以:ΐ::明:士::本發明之較佳實施例而已’並非 内容係廣義地定義二打内容範圍’本發明之實質技術 成之技術實體或方、去下Λ之申請專利範圍中，任何他人完 ,，右是與下述之申請專利範圍所定義 ^相同’亦或為同一等效變更，均將被視為涵蓋於 110889 16 201011879 此申請專利範圍中。 【圖式簡單說明】 第1圖係為習知封裝基板上以打線及覆晶接薏 *體晶片之剖視示意圖； 半導 第2A至2G圖係為本發明之封裝基板及其製法的* 實施例剖視示意圖； 、寒〜 第2A’圖係為第2A圖之另一實施例剖視示意圖； ’第2B’圖係為第2B圖之另一實施例剖視示意圖； Ο 第34至3E圖係為本發明之封裝基板及其製法的第_ 實施例剖視示意圖； 〜 弟3 D圖係為第3 D圖之另一實施例剖視示意圖· 第4A至4E圖係為本發明之封裝基板及其製法的第= 實施例剖視示意圖； — 第4D圖係為第4D圖之另·一實施例剖視示意圖.、 及 第5圖係為本發明之封裝基板以覆晶方式接置半導 體晶片之剖視示意圖。 【主要元件符號說明】 10、20 基板本體 101 覆晶墊 102 打線塾 103 、 203 植球墊 10a 置晶面 10b 植球面 110889 17 201011879 110a 110b '11a ：lib 12 13、27 '141a、141b • 142a、142b 143a 143b 144a 14a 14b 15 16 17 ❿201 202 2 卜 21， 210 210’ 22 23 230 第一開孔 第二開孔 第一絕緣保護層 第二絕緣保護層 金屬層 錫球 作用面 非作用面 第一電極墊 第二電極墊 焊錫凸塊 第一半導體晶片 第二半導體晶片 結合材料 導線 封膠材料 電性接觸墊 線路 絕緣保護層 開口 開孔 導電層 阻層 開口區 18 110889 201011879 24 導電凸塊 25 化鍍金屬阻障層 26 焊接材料 31 半導體晶片 311 電極墊 312 凸塊Film), epoxy (Epoxy) or solder mask. 110889 15 201011879 In accordance with the above structure, the conductive bumps 24 are made of copper; and a plurality of solder materials 26' are formed on the metallized metal barrier layer 25. Referring to FIG. 5, the other surface of the substrate body 20 has a plurality of ball bumps 203, and another insulating protective layer 21'' is formed on the surface, and the insulating protective layer 21 is exposed. a ball pad 2〇3, and a solder ball 27 is formed on the ball potential 203; a semiconductor wafer w is provided, the semiconductor wafer 31 has a plurality of electrode pads 311, and the electrode pads 3 ιι-- In block 312, the bump 312 is electrically connected to the solder material 26 of the substrate body 20 in a flip chip manner. The package substrate of the present invention and the method for fabricating the same are formed on the electrical contact pad by the conductive bumps' and the conductive bumps are in phase with the electrical contacts. The second semiconductor has the bonding property between the electrical contact pad and the conductive bump, and the semiconductor wafer is electrically connected to the conductive bump by the solder bump, and the opening of the protective layer of the germanium edge and the electrical contact pad gradually The shrinkage leads to the loss of the electrical connection of the two (four) rings; the conductive bumps and the snagging avoid the formation of a metallization layer formed of a nickel/palladium/gold layer on the second pad, and the λ phenomenon can be reduced, and the package substrate can be reduced. Long-term use reliability and welding material: = force minerals used: ΐ:: 明:士:: The preferred embodiment of the present invention has been 'not the content is broadly defined two-fold content range' In the scope of the patent application for the technical entity or party, the application for patents, if any other person is finished, the right is the same as the definition of the patent application scope below, or the same equivalent change, will be deemed to be covered in 110889 16 201011879 This patent application is covered. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a conventionally packaged substrate with a wire bonding and a flip chip bonded to a body wafer; the semiconductive second embodiment 2A to 2G is a package substrate of the present invention and a method for manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a cross-sectional view showing another embodiment of FIG. 2A; FIG. 2B is a cross-sectional view showing another embodiment of FIG. 2B; 3E is a schematic cross-sectional view of a package substrate of the present invention and a method for fabricating the same; FIG. 3D is a cross-sectional view of another embodiment of FIG. 3D. FIGS. 4A to 4E are diagrams of the present invention. FIG. 4D is a cross-sectional view of another embodiment of FIG. 4D, and FIG. 5 is a flip chip manner of the package substrate of the present invention. A schematic cross-sectional view of a semiconductor wafer is attached. [Main component symbol description] 10, 20 substrate body 101 flip chip 102 wire 塾 103, 203 ball pad 10a crystal face 10b ball ball surface 110889 17 201011879 110a 110b '11a : lib 12 13, 27 '141a, 141b • 142a 142b 143a 143b 144a 14a 14b 15 16 17 ❿201 202 2 卜21, 210 210' 22 23 230 first opening second opening first insulating protective layer second insulating protective layer metal layer solder ball non-active surface Electrode pad second electrode pad solder bump first semiconductor wafer second semiconductor wafer bonding material wire encapsulant material electrical contact pad line insulation protective layer opening opening conductive layer resistive opening area 18 110889 201011879 24 conductive bump 25 Metallized barrier layer 26 solder material 31 semiconductor wafer 311 electrode pad 312 bump

〇 19 110889〇 19 110889

Claims (1)

201011879 十、申請專利範圍： 1. 一種封裝基板，係包括： . 基板本體’至少一表面具有複數電性接觸墊，且 該電性接觸墊嵌埋於該基板本體中，並顯露於該基板 本體表面； 絕緣保護層，係覆設於該基板本體上，並露出該 些電性接觸墊； 導電凸塊’係設於該電性接觸墊上；以及 化鍍金屬阻障層，係覆設於該導電凸塊上，且該 化鑛金屬阻障層係為鎳/把/金層。 2·如申請專利範圍第1項之封裝基板，其中，該基板本 體係為具有核心層之基板本體或無核心層之基板本 3.201011879 X. Patent application scope: 1. A package substrate, comprising: a substrate body having at least one surface having a plurality of electrical contact pads, wherein the electrical contact pads are embedded in the substrate body and exposed on the substrate body An insulating protective layer is disposed on the substrate body to expose the electrical contact pads; a conductive bump is disposed on the electrical contact pad; and a metallized barrier layer is disposed on the surface The conductive bump is on the conductive bump, and the metallized barrier layer is a nickel/bar/gold layer. 2. The package substrate of claim 1, wherein the substrate is a substrate body having a core layer or a substrate having no core layer. 6.6. 如申請專利範㈣1項之封裝基板，其中，該基板本 體復包括線路’且該線路係嵌埋於該基板本體中，並 辩員露於該基板本體表面。 如申請專利範圍第1項之封裝基板，其中，該電性接 觸墊表面係低於、高於或齊平於該基板本體表面。 利範圍第1項之封裝基板，其中，該絕緣保 ，、有開口 ’以露出該些電性接觸墊。 ::請專利範圍第1項之封裝基板，其中，該絕緣保 4曰具有複數開孔，以對應露出各該電性接觸墊。 軌圍弟1項之封裝基板，其中’該絕緣保 4層係為聚亞㈣樹脂（PI，PQly-imide)、介電增層 110889 20 201011879 臈（ABF，Aj inomoto Bui ld-up Fi lm)、環氧樹脂（Epoxy) 或防焊層。 ；8.如申請專利範圍第1項之封裝基板，其中，該導電凸 . 塊係為銅。 10 9.如申請專利範圍第丨項之封裝基板，復包括烊接材 料’係形成於該化鍍金屬阻障層上。 一種封裝基板製法，係包括： Ο 提供一基板本體，該基板本體之至少一表面具有 複數電性接觸墊，且該電性接觸塾嵌埋於該基板本體 中，並顯露於該基板本體表面； 肢 於該基板本體上形成有絕緣保護層，並 電性接觸墊，· 备出該些 層； 層； 於該絕緣保護層及電性接㈣上形成有導電 〇 於該開口區中之導電層上形成有導電凸塊； 移除該阻層及其所覆蓋之導電層H ;u導電凸塊上形成有化鍍金屬阻障層 鍍金屬阻障層係為鎳/鈀/金層。 該化 11.如申請專利範 ㈣乾圍第10項之封裝基板製法 基板本體係為具有核心層 ❹;、，该 基板本體。 溉+肢次無核心層之 】】0889 21 201011879 12·:申：專利範圍第i。項之封裝基板製法 基板本體復包括線路， ’、 該 :_，並顯露於該基板本體=路該基板本趙 13.:广請專利範圍第10項之封裝基板製法 電性接觸墊表面係低於 _ 、 八τ 該 面。 ;问於或齊平於該基板本體表 =申請料範圍第1G項之封裝基板製法，其中，該 ::::層形成有一開口，以露出該些電性接觸墊。 如申言月專利範圍第10項之封裝基板製法，1中，， 絕緣保護層形成有複數開孔，以對應露出各該電性接 觸墊。 X电庇接 14 ❹15 16.如申凊專利範圍第1〇項之封裝基板製法其中，該 絕緣保護層係為聚亞酿胺樹脂（pi，p〇ly七响、^ 電增層膜（ABF，Ajinomoto Build 一 叩 FUin)、環氧樹 脂（Epoxy)或防焊層。 Π·如申請專利範圍第10項之封裝基板製法’其中該 導電凸塊係為銅。 18·如申請專利範圍第10項之封裝基板製法，復包括於 該化鑛金屬阻障層上形成有焊接材料。 19· 一種封裝基板製法，係包括： k供一基板本體，該基板本體之至少一表面具有 複數電性接觸墊，且該電性接觸墊嵌埋於該基板本體 中’並顯露於該基板本體表面； 於該基板本體上形成有導電層； 】10889 22 201011879 !工％風有阻層 穿之開Π卜以對岸露中二—限^形成有貫 層； 讀應路出該電性接觸墊上之部份導電 於該開口區中之導電； 电增上形成有導電凸塊 移除該阻層及其所覆蓋之導電層； 於該基板本體上形成有絕緣保護層 電性接觸墊；以及 並露出該些 且該化 於該導電凸塊上形成有化鍍金屬阻障層 ❹ 鍍金屬阻障層係為鎳/鈀/金層。 20.如申請專利範圍第19項之封袭基板製法其中該 Ϊΐί:係為具有核心層之基板本體或無核心層之 21·如申請專·圍第19項之封I基板製法，其中，該 ^板本體復包括祕’且該線路係嵌埋於該基板本體 肀，並顯露於該基板本體表面。 〇22.如巾請專利範圍第19項之封裝基板製法，其中，該 =ί·生接觸墊表面係低於、高於或齊平於基板本體表 23.如申請專利範圍第19項之封裝基板製法，其令，該 24 ^緣保護層形成有—開°，以露出該些電性接觸塾。 *乃申請專利範圍第19項之封裝基板製法，其中，該 、巴緣保5蔓層形成有複數開孔，以對應露出各該電性接 觸塾。 5·如申請專利範圍帛19項之封裝基板製法，其中，該 110889 23 201011879 絕緣保護層係為聚亞醮胺樹脂（pi，p〇iy_iinide)、介 •=層膜upFllm)、環氧樹 如（Epoxy)或防焊層。 :26·如申請專利範圍第19項之封裝基板製法，其 導電凸塊係為銅。 2?.如申請專利範圍第19項之封震基板製法，復包括於 該化鍍金屬阻障層上形成有焊接材料。 28. —種封裝基板製法，係包括： 提供一基板本體，該基板本體之至少一表面且有 複數電性接觸塾，且該電性接觸墊嵌埋於該基板本體 中，並顯露於該基板本體表面； ^ ; ~基板本體上形成有阻層，且該阻層中形成有 貝穿之開口區，以對應露出該電性接觸墊； 於該開σ區中之電性接觸墊上以化鍵方 有導電凸塊； 移除該阻層； 於該基板本體上形成有絕緣保護層，並露出該些 電性接觸塾；以及 於該導電凸塊上形成有化鍍金屬阻障層，且該化 鐘金屬阻障層係為鎳/鈀/金層。 29·如申請專利範圍第28項之封裝基板製法，其中，該 基板本體係為具有核心層之基板本體或無核心層之 基板本體。 30.如申請專利範圍第28項之封裝基板製法，其中，該 110889 24 2〇l〇iig79 基板本體復包括tThe package substrate of claim 4, wherein the substrate body comprises a circuit ” and the circuit is embedded in the substrate body, and the defender is exposed on the surface of the substrate body. The package substrate of claim 1, wherein the surface of the electrical contact pad is lower, higher or flush with the surface of the substrate body. The package substrate of item 1, wherein the insulation has an opening to expose the electrical contact pads. The package substrate of claim 1, wherein the insulating layer has a plurality of openings to correspondingly expose the respective electrical contact pads. A package substrate of one of the rails, in which 'the insulation is 4 layers of poly (tetra) resin (PI, PQly-imide), dielectric build-up 110889 20 201011879 臈 (ABF, Aj inomoto Bui ld-up Fi lm) Epoxy or solder mask. 8. The package substrate of claim 1, wherein the conductive bump is copper. 10. The package substrate of claim </RTI> of claim </ RTI> wherein the splicing material is formed on the metallized barrier layer. A method for manufacturing a package substrate, comprising: providing a substrate body, wherein at least one surface of the substrate body has a plurality of electrical contact pads, and the electrical contact pads are embedded in the substrate body and exposed on the surface of the substrate body; Forming an insulating protective layer on the substrate body, and electrically contacting the pads, preparing the layers; forming a conductive layer on the insulating protective layer and the electrical connection (4) with conductive turns in the open region A conductive bump is formed thereon; the resist layer and the conductive layer H covered thereon are removed; and the metallized barrier layer formed on the conductive bump is a nickel/palladium/gold layer. The invention is as follows: (4) The package substrate method of the tenth item of the dry circumference method. The substrate has a core layer; and the substrate body. Irrigation + limbs without core layer]] 0889 21 201011879 12·: Shen: Patent scope i. The package substrate of the package substrate comprises a circuit, ', the: _, and is exposed on the substrate body = the substrate of the substrate. Zhao Zhao: The wide range of the surface of the package substrate made of the patent scope 10 is low. On _, 八τ this side. Asking or flushing the substrate body table = the package substrate method of claim 1G, wherein the :::: layer is formed with an opening to expose the electrical contact pads. In the method of manufacturing a package substrate according to claim 10 of the claim, in the insulating layer, a plurality of openings are formed to correspondingly expose the respective electrical contact pads. The invention relates to a package substrate method according to the first aspect of the invention, wherein the insulating protective layer is a poly-branched amine resin (pi, p〇ly seven-ring, ^ electric build-up film (ABF) , Ajinomoto Build a FUin), epoxy resin (Epoxy) or solder resist layer. Π · The patent application method of claim 10 of the package substrate method 'where the conductive bump is copper. 18 · If the scope of patent application 10 The method for manufacturing a package substrate comprises forming a solder material on the barrier layer of the metallized metal. 19) A method for manufacturing a package substrate, comprising: k for a substrate body, wherein at least one surface of the substrate body has a plurality of electrical contacts a pad, and the electrical contact pad is embedded in the substrate body ′ and exposed on the surface of the substrate body; a conductive layer is formed on the substrate body; 】 10889 22 201011879 工% wind has a resistance layer to open the Π a cross layer is formed on the opposite side of the opposite side; the portion of the electrical contact pad is electrically conductive to conduct electricity in the open area; and the conductive bump is formed on the electric scale to remove the resist layer and Covered conductive layer; An insulating contact layer electrical contact pad is formed on the substrate body; and the metal bump barrier layer is formed on the conductive bump to form a nickel/palladium/gold layer. 20. The method for manufacturing a sealed substrate according to claim 19, wherein the method is a substrate body having a core layer or a coreless layer, and the method for manufacturing a substrate is as described in claim 19, wherein The board body complex includes the secret ' and the circuit is embedded in the substrate body 肀 and exposed on the surface of the substrate body. 〇 22. The method for manufacturing a package substrate according to claim 19, wherein the The contact pad surface is lower than, higher than or flush with the substrate body. The package substrate method according to claim 19, wherein the 24 ^ edge protective layer is formed with -open to expose the electricity Sexual contact 塾. * The method for manufacturing a package substrate according to claim 19, wherein the berry layer of the berry layer is formed with a plurality of openings to correspondingly expose the electrical contact 塾. 5. If the scope of application is 帛19th package substrate manufacturing method, wherein 110889 23 201011879 The insulating protective layer is a polyimide resin (pi, p〇iy_iinide), a layer of film upFllm, an epoxy tree such as (Epoxy) or a solder mask. [26] The package substrate method of claim 19, wherein the conductive bump is copper. 2. The method for producing a sealed substrate according to claim 19 of the patent application, comprising forming a solder material on the metallized barrier layer. 28. The method of manufacturing a package substrate, comprising: providing a substrate body, at least one surface of the substrate body and having a plurality of electrical contacts, and the electrical contact pads are embedded in the substrate body and exposed on the substrate a surface of the body; ^ ; ~ a resistive layer is formed on the substrate body, and an opening region of the barrier layer is formed in the resist layer to correspondingly expose the electrical contact pad; and an electrical contact pad is formed on the electrical contact pad in the open σ region The conductive bump is removed; the resistive layer is removed; an insulating protective layer is formed on the substrate body, and the electrical contact is exposed; and a metallized barrier layer is formed on the conductive bump, and the conductive bump is formed on the conductive bump The metal barrier layer is a nickel/palladium/gold layer. The method of manufacturing a package substrate according to claim 28, wherein the substrate is a substrate body having a core layer or a substrate body having no core layer. 30. The method for manufacturing a package substrate according to claim 28, wherein the 110889 24 2〇l〇iig79 substrate body includes t 該 表 中， 、&quot;，且該線路係嵌埋於該基板本 〒^露於該基板本體表面。 本 . •如申晴專利範圍望9 δ S 、項之料基板製法，其中， 面。 、面係低於、高於或齊平於基板本體 利範圍第28項之封裝基板製法，其中，該 33如%成有—開口 ’以露出該些電性接觸塾。 申請專利範圍第28項之封裝基板製法，其上 觸^保遴層形成有複數開孔，以㈣露出各該電性接 34. 如申凊專利範圍第28項之封裝基板製法，其中，該 絕緣保護層係為聚亞醯胺樹脂（pi, pGly_imide)、 電'曰層膜（ABF, Ajinomoto Build_up Film)、環氧樹 脂（Epoxy)或防焊層。 35. 如申請專利範圍第28項之封裝基板製法其中該 導電凸塊係為銅。 036.如中請專利範圍第28項之封裝基板製法復包括於 該化鍍金屬阻障層上形成有焊接材料。 110889 25In the table, , &quot;, and the circuit is embedded in the substrate and exposed on the surface of the substrate body. Ben. • For example, Shen Qing's patent scope is 9 δ S, the material substrate method of the item, among them, the surface. The method of manufacturing a package substrate that is lower than, higher than, or flush with the substrate body, wherein the 33 is made to have an opening to expose the electrical contacts. The package substrate method of claim 28, wherein the upper contact layer is formed with a plurality of openings, and (4) exposing each of the electrical contacts 34. The package substrate method of claim 28, wherein The insulating protective layer is a polyimide resin (pi, pGly_imide), an ABF (Ajinomoto Build_up Film), an epoxy resin (Epoxy) or a solder resist layer. 35. The package substrate method of claim 28, wherein the conductive bump is copper. 036. The package substrate method of claim 28, wherein the method for manufacturing a package substrate comprises forming a solder material on the metallized barrier layer. 110889 25
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US9305875B2 (en) 2013-01-28 2016-04-05 Fujitsu Limited Method of manufacturing semiconductor device capable of enhancing bonding strength between connection terminal and electrode
US10043774B2 (en) 2015-02-13 2018-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit packaging substrate, semiconductor package, and manufacturing method
TWI692072B (en) * 2018-04-05 2020-04-21 日商三菱電機股份有限公司 Semiconductor module and its manufacturing method

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US6413851B1 (en) * 2001-06-12 2002-07-02 Advanced Interconnect Technology, Ltd. Method of fabrication of barrier cap for under bump metal
US6732908B2 (en) * 2002-01-18 2004-05-11 International Business Machines Corporation High density raised stud microjoining system and methods of fabricating the same
TWI220068B (en) * 2003-05-29 2004-08-01 Advanced Semiconductor Eng A structure of chip package with copper bumps and manufacture thereof
TWI268012B (en) * 2003-08-07 2006-12-01 Phoenix Prec Technology Corp Electrically conductive structure formed between neighboring layers of circuit board and method for fabricating the same

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Publication number Priority date Publication date Assignee Title
US9305875B2 (en) 2013-01-28 2016-04-05 Fujitsu Limited Method of manufacturing semiconductor device capable of enhancing bonding strength between connection terminal and electrode
US9620470B2 (en) 2013-01-28 2017-04-11 Fujitsu Limited Semiconductor device having connection terminal of solder
TWI579992B (en) * 2013-01-28 2017-04-21 Fujitsu Ltd Semiconductor device and method of manufacturing the semiconductor device
US10043774B2 (en) 2015-02-13 2018-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit packaging substrate, semiconductor package, and manufacturing method
TWI662658B (en) * 2015-02-13 2019-06-11 台灣積體電路製造股份有限公司 Integrated circuit packaging substrate, semiconductor package and manufacturing method thereof
TWI692072B (en) * 2018-04-05 2020-04-21 日商三菱電機股份有限公司 Semiconductor module and its manufacturing method

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