CN1288729C - Semiconductor packaging member and method for making same - Google Patents

Semiconductor packaging member and method for making same Download PDF

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Publication number
CN1288729C
CN1288729C CNB031019501A CN03101950A CN1288729C CN 1288729 C CN1288729 C CN 1288729C CN B031019501 A CNB031019501 A CN B031019501A CN 03101950 A CN03101950 A CN 03101950A CN 1288729 C CN1288729 C CN 1288729C
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Prior art keywords
semiconductor package
package part
layer
making
chip
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CN1521817A (en
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黄建屏
王愉博
黄致明
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

The present invention relates to a semiconductor packaging member and a production method thereof. Firstly, an insulating material layer is provided with a plurality of openings, soldering is laid in each opening, and a first copper layer and a second copper layer are orderly formed on the insulating material layer and the soldering, the first and the second copper layers form a plurality of conductive traces after being patterned, each conductive trace has a terminal, and a metal level is laid on the terminal of each conductive trace; then, the conductive traces are connected to a conductive trace of at least one chip, and the chip is electrically connected with the terminals laid with the metal layer through a conductive assembly, such as a bonding wire, etc.; finally, a packaging colloid is formed to coat the chip, the conductive assembly and the conductive traces, the insulation material layer and the soldering are exposed out of the packaging colloid, and the exposed soldering is used as the input/output end of the semiconductor packaging member. In the packaging structure, the conductive traces can be laid elastically, the arc length of the bonding wire is shortened effectively, and the circuit layout performance and the electric connection quality of the semiconductor packaging member are improved.

Description

Semiconductor package part and method for making thereof
Technical field
The present invention is relevant a kind of semiconductor package part and method for making thereof, particularly about a kind ofly not needing to use pedestal, and can improving the semiconductor package part of circuit layout (Routability) and the method for making this semiconductor package part.
Background technology
The general semiconductor package part (SemiconductorPackage) that uses lead frame (Lead Frame), the flat pin-free in four limits (Quad Flat Non-lead for example, QFN) encapsulating structure etc., it is the sticking semiconductor chip of establishing on as the lead frame of chip bearing member (Chip Carrier), and the pin of lead frame exposes outside the packing colloid of coating chip, make the pin that exposes output/input (Input/Output as semiconductor package part, I/O) end, with external device, printed circuit board (PCB) (Printed Circuit Board for example, PCB) form electric connection, chip is operated by this external device.
This QFN semiconductor package part is found in United States Patent (USP) the 6th, 130, and 115,6,143,981 and 6,229, in No. 200, as shown in Figure 6, be with at least one chip 20, on the sticking chip carrier of putting at lead frame 21 (Die Pad) 210 of adhesive (Adhesive, not icon), and make this chip 20 by many bonding wires (Bonding Wire) 22, be electrically connected to many pin twos 11 around chip carrier 210; Then, on lead frame 21, form (as epoxy resin with resin material, Epoxy Resin) packing colloid of making (Encapsulant) 23 makes it coat this chip 20, bonding wire 22 and lead frame 21, and pin two 11 at least one surperficial 212 expose outside packing colloid 23.
Shown in Fig. 7 A, the pin two 11 of above-mentioned lead frame 21 the number that number is the weld pad 201 on the roughly corresponding action face 200 that is laid in chip 20 is set, make each weld pad 201 borrow bonding wire 22 to be electrically connected to corresponding pin two 11.Have again, pin two 11 around chip carrier 210 is with chip carrier 210 preset distance to be arranged apart, therefore, is welded on the arc length of the bonding wire 22 of 11 of chip 20 and pin twos, be greater than the distance of 210 of pin two 11 and chip carriers, could electrically connect chip 20 effectively to pin two 11.Yet, shown in Fig. 7 B, when the 20 ' time of chip that will use Highgrade integration (Highly Integrated), i.e. this chip 20 ' have weld pad 201 that quantity is more or density is higher, relatively need to lay more pin two 11, make the distance of 210 of pin two 11 and chip carriers and bonding wire 22 ' arc length increase; The long bonding wire 22 ' difficulty of bonding wire (Wire Bonding) operation is promoted, and when mold pressing (Molding) operation that forms packing colloid 23 is carried out, the impact of long bonding wire 22 ' be subject to resin mold stream, produce skew (Sweep) or displacement (Shift) phenomenon, the bonding wire of skew or displacement may be touched each other, cause short circuit (Short) problem, influence electrically connects quality; Have again,, then may make the bonding wire operation be difficult to carry out apart, cause and to pass through bonding wire, electrically connect the situation of chip to pin or lead frame if far away excessively between pin and chip carrier.
For shortening the distance between bonding wire arc length or pin and chip carrier, semiconductor package as shown in Figure 8 appears.As shown in the figure, on each pin two 11, form the extension 213 that extends towards chip carrier 210 directions in the mode that etches partially (Half-Etching), it is in order to shorten the distance of 210 of pin two 11 and chip carriers, make the chip 20 of Highgrade integration ' can borrow bonding wire 22, be electrically connected to the extension 213 of pin two 11 with suitable arc length.
Yet the shortcoming of this encapsulating structure is, form extension 213 will make lead frame 21 ' manufacture difficulty improve, cost increases; Have, when carrying out the bonding wire operation, the extension 213 of pin two 11 easily produces and moves (Dislocation), is difficult to accurately weld thereon establish bonding wire 22, thereby causes the difficulty of bonding wire operation again.
In addition as United States Patent (USP) the 5th, 830,800 and 6,072, a kind of semiconductor package part that does not have pedestal of No. 239 inventions, its operation roughly be shown in Fig. 9 A to 9D like that.At first, in Fig. 9 A, prepare a carrier made of copper (Carrier) 30, and connect on a surface of this carrier 30 and establish a light shield (Mask) 31, this light shield 31 offers many openings 310, makes the predetermined position of carrier 30 borrow this opening 310 to expose.Then, in Fig. 9 B, in the opening 310 of each light shield 31, form contact or terminal (Terminal) 32, remove light shield 31 from carrier 30 then, carrier 30 and contact 32 are exposed in the mode of electroplating.In Fig. 9 C, glue brilliant (DieBonding) and bonding wire operation in regular turn, with a chip 33 sticking putting on carrier 30, and form many bonding wires 34 to electrically connect chip 33 to contact 32; Then, carry out a molding operation, on carrier 30, to form packing colloid 35 in order to coating chip 33 and bonding wire 34.At last, in Fig. 9 D, remove carrier 30 in etching modes such as (Etching), make contact 32 surfaces 320 original and that carrier 30 touches expose outside packing colloid 35,32 I/O ends of the contact that exposes as semiconductor package part, electrically connect with external device (not icon), so the manufacturing process that just finishes semiconductor package part.
The advantage of this semiconductor package part is to need not to use pedestal (as prefabricated lead frame etc.), and packing colloid 35 does not need to engage with lead frame 21, thereby avoids between packing colloid 35 and lead frame 21 to produce delaminations (Delamination).Yet, this packaging part is not broken away from the shortcoming of prior art, be exactly when weld pad quantity of laying on the chip 33 or density raising, relatively need to form than multiple-contact 32, the distance of 33 of contact 32 and chips is increased, to produce the problem shown in similar Fig. 7 B this moment, as causing problems such as skew, displacement and short circuit because of bonding wire is long, thereby influence electric connection quality.
Therefore, how addressing the above problem, how to provide a kind of and can flexibly lay conductive trace, can effectively shorten the semiconductor package of bonding wire arc length, improve circuit layout and electrically connect quality, is instant problem.
Summary of the invention
Main purpose of the present invention is to provide a kind of semiconductor package part and method for making thereof, can flexibly lay the conductive trace (Conductive Trace) in the semiconductor package part, and then can effectively shorten in order to electrically connect the bonding wire arc length of chip to this conductive trace, improve the circuit layout (Routability) of semiconductor package part and electrically connect quality.
Another object of the present invention is to provide a kind of semiconductor package part and method for making thereof, it does not need to use pedestal, thereby can reduce the manufacturing cost of semiconductor package part.
For reaching above-mentioned and other purpose, a kind of semiconductor package part of the present invention comprises: an insulation material layer offers many openings that run through insulation material layer on its predetermined position; One scolder is in the opening of this insulation material layer respectively of being laid in; One first bronze medal layer is formed on this insulation material layer and the scolder; One second bronze medal layer, utilizing this first bronze medal layer to electroplate as conductive layer is formed on this first bronze medal layer, make this first and second copper layer patternization to form many conductive traces, respectively a side of this conductive trace forms a terminal, and opposite side then is electrically connected to this scolder relatively; At least one chip connects and puts on the predetermined position of this conductive trace, and is electrically connected to this terminal; And a packing colloid, coat this chip and conductive trace, make this insulation material layer and scolder expose outside this packing colloid.
The method for making of this semiconductor package part comprises the following steps: to prepare a metal carrier; Lay an insulation material layer on a surface of this metal carrier, and offer many openings that run through this insulation material layer at the predetermined position of this insulation material layer; Lay a scolder in the opening of this insulation material layer respectively; Form one first bronze medal layer on this insulation material layer and scolder; Utilize this first bronze medal layer on this first bronze medal layer, to electroplate and form one second bronze medal layer as conductive layer, and utilize this first and second copper layer of etching mode patterning to form many conductive traces, make respectively that a side of this conductive trace forms a terminal, opposite side then is electrically connected to this scolder relatively; Connect and put at least one chip on the predetermined position of this conductive trace, and electrically connect this chip to this terminal; Form a packing colloid to coat this chip and conductive trace; And remove this metal carrier, this insulation material layer and scolder are exposed.
The advantage of above-mentioned semiconductor package part is not need to use pedestal (as prefabricated lead frame, substrate etc.) as chip bearing member, chip is connect be located on the conductive trace, and make conductive trace can adapt to the integrated degree of chip or the distribution situation of weld pad, flexibly lay and can deeply weld the laying zone of bonding wire even with chip, effectively shorten in order to electrically connect the bonding wire arc length of chip to the terminal of conductive trace, shorten the electrical connection path between chip and conductive trace, can improve the circuit layout of semiconductor package part and electrically connect quality, the existing short circuit that causes because of bonding wire is long of forgoing, shortcomings such as bonding wire operational difficulty; Simultaneously, need not to use pedestal also can reduce the manufacturing cost of semiconductor package part.
Description of drawings
Fig. 1 shows the cutaway view of the semiconductor package part of the embodiment of the invention 1;
Fig. 2 shows the upward view of semiconductor package part shown in Figure 1;
Fig. 3 A to 3G shows the process schematic diagram of semiconductor package part shown in Figure 1;
Fig. 4 shows the cutaway view of the semiconductor package part of the embodiment of the invention 2;
Fig. 5 shows the cutaway view of the semiconductor package part of the embodiment of the invention 3;
Fig. 6 shows the cutaway view of existing semiconductor package part;
Fig. 7 A and 7B show the top view of semiconductor package part shown in Figure 6;
Fig. 8 shows the cutaway view of another existing semiconductor package part; And
Fig. 9 A to 9D shows the process schematic diagram of another existing semiconductor package part.
Embodiment
Below promptly cooperate Fig. 1 to Fig. 5, describe semiconductor package part of the present invention and method for making thereof in detail.
Embodiment 1
The invention provides a kind of semiconductor package part that does not have pedestal, be to use insulation (Dielectric) material layer, on this insulation material layer, flexibly to lay conductive trace (Conductive Trace), thereby can effectively shorten the arc length of bonding wire (Bonding Wire), improve the circuit layout (Routability) of packaging part and electrically connect quality.As shown in Figures 1 and 2, this semiconductor package part comprises an insulation material layer 10, offers many openings 100 that run through insulation material layer 10 at its predetermined position; Scolder (Solder) 11 is in the opening 100 of this insulation material layer 10 respectively of being laid in; First thin copper layer 12 is formed on insulation material layer 10 and the scolder 11; The second bronze medal layer 13 is laid on first thin copper layer 12, makes first thin copper layer 12 and the second bronze medal layer 13 be formed with many conductive traces (Conductive Trace) 130, and each conductive trace 130 has terminal (Terminal) 131; One metal level 141 is on the terminal 131 of each conductive trace 130 that is laid in; At least one chip 15 is put on the predetermined position of conductive trace 130 by adhesive (Adhesive, not icon) is sticking; Many bonding wires 16 are in order to electrically connect chip 15 to the terminal 131 that is laid with metal level 141; And packing colloid (Encapsulant) 17, in order to coating chip 15, bonding wire 16 and conductive trace 130, make insulation material layer 10 and scolder 11 expose outside packing colloid 17.
Above-mentioned semiconductor package part can be made from the process shown in Fig. 3 A to 3G.
At first, in Fig. 3 A, preparation metal carrier (Carrier), for example copper coin (Cu Plate) 18.Then, on a surface of this copper coin 18, lay insulation material layer 10, this insulation material layer 10 can be used epoxy resin (Epoxy Resin), polyimides (Polyimide) or Te Fulong, and (polytetrafluoroethylene PTFE) waits and not to have a material of conductivity and make.Then, at the predetermined position of insulation material layer 10, offer many openings 100 that run through insulation material layer 10, make part copper coin 18 borrow this opening 100 to expose, the opening 100 of insulation material layer 10 is follow-up I/O (Input/Output, I/O) Duan positions that are used to form semiconductor package part.
Then, in Fig. 3 B, lay a scolder 11 to electroplate modes such as (plating), tin/lead (Sn/Pb) alloy etc. for example, in the opening 100 of each insulation material layer 10, this scolder 11 is deposited on the copper coin 18 that exposes outside in the opening 100, and scolder 11 thickness in the opening 100 that is laid in are better less than the degree of depth of this opening 100.With scolder 11 surfaces that copper coin 18 touches, will in subsequent handling, expose, as the I/O end of semiconductor package part.This electroplating technology belongs to prior art, so in this not repeat specification.
Then in Fig. 3 C, with electroless plating plated film (Electroless Plating) or sputter modes such as (Sputtering), on insulation material layer 10 and scolder 11, form first thin copper layer 12, make this first thin copper layer 12 cover the surface of whole insulation material layer 10 and the scolder 11 in all openings 100 that are laid in; The thickness of first thin copper layer 12 is about 1 to 3 μ m.Belong to prior art in order to electroless plating plated film or the sputter technology that forms first thin copper layer 12, so in this not repeat specification.
In Fig. 3 D, on first thin copper layer, 12 lay the second bronze medal layer 13 with modes such as plating, the thickness of this second bronze medal layer 13 is about 15 to 20 μ m greater than the thickness of first thin copper layer 12.Then, utilize existing exposure (Exposing), development (Developing) and etching modes such as (Etching), make first thin copper layer 12 and the second bronze medal layer, 13 patterning (Patterning), form many conductive traces 130, make respectively that this conductive trace 130 has a terminal 131, this terminal 131 is to refer to (Bond Finger) as the follow-up weldering that is used for electrically connecting with chip (not icon).
Perhaps; shown in Fig. 3 D1; can on many conductive traces 130 of borrowing patterning to form, lay an insulating barrier 140; for example refuse solder flux (Solder Mask), polyimides insulating cements such as (Polyimide); be used for covering conductive trace 130; make the terminal 131 of conductive trace 130 expose outside this insulating barrier 140, the insulating barrier 140 that covers conductive trace 130 plays the effect of protection conductive trace 130, and the terminal 131 that exposes is the follow-up usefulness that refers to as weldering of confession then.
Then, on the terminal (or weldering refers to) 131 of each conductive trace 130, lay a metal level 141 with modes such as plating, this metal level 141 can be silver (Ag) layer or nickel/gold (Ni/Au) alloy-layer etc., use and the conductive component that electrically connects chip (bonding wire for example, icon not) material that has good weldability between is better, and follow-up can electrically being welded on well of this conductive component referred on 131.
In Fig. 3 E, prepare a chip 15, has the relative non-action face (Non-active Surface) 151 of an action face (Active Surface) 150 and, be laid with electronic building brick and electronic circuit (Electronic Element and Circuit, not icon) on its action face 150.Carry out sticking brilliant (Die Bonding) operation, borrow non-action face 151 sticking put on the predetermined position of conductive trace 130 of adhesive (Adhesive, not icon) this chip 15.
Then, carry out a bonding wire (Wire Bonding) operation, form many bonding wires 16 and make its action face that is soldered to chip 15 150 and the weldering that is laid in refer to make metal level 141 on 131 chip 15 borrow bonding wire 16 to be electrically connected to weldering and refer to 131.
In Fig. 3 F, carry out a mold pressing (Molding) operation, with the above-mentioned semi-finished product of finishing sticking crystalline substance and bonding wire operation, insert encapsulating mould commonly used (Encapsulation Mold, icon not) in, and injection resin material, epoxy resin etc. for example, make in its die cavity that is filled in this encapsulating mould (not icon), form the packing colloid 17 of coating chip 15, bonding wire 16 and conductive trace 130, after resin material solidifies (Cure), remove encapsulating mould, then finish the operation of packing colloid 17, the assembly that this packing colloid 17 is coated is avoided extraneous aqueous vapor or pollutant sources infringement.
At last, in Fig. 3 G, finish the operation of packing colloid 17 after, carry out all single (Singulation) operations, use cutting tool 4 cutting packing colloids 17; Then, remove copper coin 18 from insulation material layer 10, make scolder 11 in insulation material layer 10 and the opening 100 original and that copper coin 18 touches is surface exposed in etched mode.So promptly finish semiconductor package part of the present invention, shown in Fig. 1 and 2.The scolder 11 that exposes is as the I/O end of semiconductor packages, and with external device, for example printed circuit board (PCB) (Printed Circuit Board, not icon) electrically connects, and can operate on the printed circuit board (PCB) thereby chip 15 is electrically conducted.
The advantage of above-mentioned semiconductor package part is, do not need to use pedestal (as prefabricated lead frame, substrate etc.) as chip bearing member, chip is connect be located on the conductive trace, and can adapt to the integrated degree of chip or the distribution situation of weld pad, conductive trace is flexibly laid, and can be deeply and the laying zone of the bonding wire of chip weldering company, effectively shorten in order to electrically connect the arc length of chip to the bonding wire of the terminal (weldering refers to) of conductive trace, shorten the electrical connection path between chip and the conductive trace, improve the circuit layout of semiconductor package part and electrically connect quality, the existing short circuit that causes because of bonding wire is long of forgoing, shortcomings such as bonding wire operational difficulty; Simultaneously, do not need to use pedestal can reduce the manufacturing cost of semiconductor package part yet.
Embodiment 2
Fig. 4 shows the semiconductor package part of the embodiment of the invention 2.As shown in the figure, the structure of the semiconductor package part of this embodiment is roughly similar to the foregoing description 1, and difference is, the chip 15 of embodiment 2 is to connect and be located on the conductive trace 130 to cover crystalline substance (Flip-Chip) mode; Just, when gluing brilliant operation, the action face 150 of chip 15 is towards conductive trace 130, and borrows a plurality of welding blocks (Solder Bump) 16 ' be electrically connected to the terminal 131 of conductive trace 130, at this, this terminal 131 as and weld pad (Bond Pad) of welding block 16 ' weldering company.Simultaneously, can on conductive trace 130, lay an insulating barrier 140, make terminal 131 expose outside this insulating barrier 140, with welding block 16 ' be connected to cover conductive trace 130.
Compare with the structure of conductive trace with connect chip with bonding wire, utilize welding block 16 ' Flip Chip, can further shorten the electrical connection path of 130 of chip 15 and conductive traces, more can guarantee the electric connection quality of 130 of chip 15 and conductive traces.
Have again, the non-action face 151 of chip 15 can optionally expose outside the packing colloid 17 of coating chip 15, the heat that chip 15 runnings are produced can be borrowed this non-action face 151 that exposes effectively to be emitted to the external world, and then improve the radiating efficiency of semiconductor package part.
Embodiment 3
Fig. 5 shows the semiconductor package part of the embodiment of the invention 3.As shown in the figure, the semiconductor package part structure of embodiment 3 is roughly similar to the foregoing description 1, difference only is, the semiconductor package part of embodiment 3 also has many hedge plantings and is located at soldered ball (Solder Ball) 19 on the scolder 11 that exposes, this encapsulating structure that is laid with soldered ball 19 is called ball grid array (Ball GridArray, BGA) structure makes soldered ball 19 electrically connect as the I/O end and the external device (not icon) of semiconductor package part.

Claims (36)

1. the method for making of a semiconductor package part is characterized in that, this method for making comprises the following steps:
Prepare a metal carrier;
Lay an insulation material layer on a surface of this metal carrier, and offer a plurality of openings that run through insulation material layer at the predetermined position of this insulation material layer;
Lay a scolder in the opening of this insulation material layer respectively;
Form one first bronze medal layer on this insulation material layer and scolder;
Utilize this first bronze medal layer on this first bronze medal layer, to electroplate and form one second bronze medal layer as conductive layer, and utilize this first and second copper layer of etching mode patterning to form many conductive traces, make respectively that a side of this conductive trace forms a terminal, opposite side then is electrically connected to this scolder relatively;
Connect and put at least one chip on the predetermined position of this conductive trace, and electrically connect this chip to this terminal;
Form a packing colloid, coat this chip and conductive trace; And
Remove this metal carrier, this insulation material layer and scolder are exposed.
2. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, this method for making also comprises lays the step of a metal level on the terminal of this conductive trace respectively, makes this chip be electrically connected to the terminal that this is laid with metal level.
3. the method for making of semiconductor package part as claimed in claim 2 is characterized in that, this metal level is a silver layer.
4. the method for making of semiconductor package part as claimed in claim 2 is characterized in that, this metal level is one nickel/gold alloy layer.
5. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, this method for making also comprises lays the step of an insulating barrier on these many conductive traces, and making respectively, the terminal of this conductive trace exposes outside this insulating barrier.
6. the method for making of semiconductor package part as claimed in claim 5 is characterized in that, this insulating barrier is to refuse welding flux layer.
7. the method for making of semiconductor package part as claimed in claim 5 is characterized in that, this insulating barrier is a polyimide layer.
8. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, this metal carrier is to be made of copper.
9. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, this insulation material layer is that the material that is selected from epoxy resin, polyimides and Te Fulong composition cohort is made.
10. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, this scolder is tin/lead alloy.
11. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, this scolder, the second bronze medal layer and metal level are to lay with plating mode.
12. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, this first bronze medal layer is that the mode with the electroless plating plated film forms.
13. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, this first bronze medal layer is to form with sputtering way.
14. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, the thickness of this first bronze medal layer is less than the thickness of this second bronze medal layer.
15. the method for making of semiconductor package part as claimed in claim 14 is characterized in that, the thickness of this first bronze medal layer is 1 to 3 micron.
16. the method for making of semiconductor package part as claimed in claim 14 is characterized in that, the thickness of this second bronze medal layer is 15 to 20 microns.
17. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, the patterning of this first and second copper layer is to utilize exposure, development and etching mode and form many conductive traces.
18. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, this metal carrier is to remove with etching mode.
19. the method for making of semiconductor package part as claimed in claim 2 is characterized in that, this chip is to borrow many bonding wires to be electrically connected to this terminal.
20. the method for making of semiconductor package part as claimed in claim 2 is characterized in that, this chip is to borrow a plurality of welding blocks to be electrically connected to this terminal.
21. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, this method for making also comprises and plants the step of a plurality of soldered balls on this scolder that exposes.
22. a semiconductor package part is characterized in that, this semiconductor package part comprises:
One insulation material layer is offered many openings that run through insulation material layer at its predetermined position;
One scolder is in the opening of this insulation material layer respectively of being laid in;
One first bronze medal layer is formed on this insulation material layer and the scolder;
One second bronze medal layer, utilizing this first bronze medal layer to electroplate as conductive layer is formed on this first bronze medal layer, make this first and second copper layer patternization to form many conductive traces, respectively a side of this conductive trace forms a terminal, and opposite side then is electrically connected to this scolder relatively;
At least one chip connects and puts on the predetermined position of this conductive trace, and is electrically connected to this terminal; And
One packing colloid in order to coat this chip and conductive trace, makes this insulation material layer and scolder expose outside this packing colloid.
23. semiconductor package part as claimed in claim 22 is characterized in that, this semiconductor package part also comprises: a metal level on the terminal of this conductive trace respectively of being laid in, makes this chip be electrically connected to the terminal that this is laid with metal level.
24. semiconductor package part as claimed in claim 23 is characterized in that, this metal level is a silver layer.
25. semiconductor package part as claimed in claim 23 is characterized in that, this metal level is one nickel/gold alloy layer.
26. semiconductor package part as claimed in claim 22 is characterized in that, this semiconductor package part also comprises: an insulating barrier, on these many conductive traces that are laid in, making respectively, the terminal of this conductive trace exposes outside this insulating barrier.
27. semiconductor package part as claimed in claim 26 is characterized in that, this insulating barrier is to refuse welding flux layer.
28. semiconductor package part as claimed in claim 26 is characterized in that, this insulating barrier is a polyimide layer.
29. semiconductor package part as claimed in claim 22 is characterized in that, this insulation material layer is that the material that is selected from epoxy resin, polyimides and Te Fulong composition cohort is made.
30. semiconductor package part as claimed in claim 22 is characterized in that, this scolder is tin/lead alloy.
31. semiconductor package part as claimed in claim 22 is characterized in that, the thickness of this first bronze medal layer is less than the thickness of this second bronze medal layer.
32. semiconductor package part as claimed in claim 31 is characterized in that, the thickness of this first bronze medal layer is 1 to 3 micron.
33. semiconductor package part as claimed in claim 31 is characterized in that, the thickness of this second bronze medal layer is 15 to 20 microns.
34. semiconductor package part as claimed in claim 23 is characterized in that, this chip is to borrow many bonding wires to be electrically connected to this terminal.
35. semiconductor package part as claimed in claim 23 is characterized in that, this chip is to borrow a plurality of welding blocks to be electrically connected to this terminal.
36. semiconductor package part as claimed in claim 22 is characterized in that, this semiconductor package part also comprises: a plurality of soldered balls plant on this scolder that exposes.
CNB031019501A 2003-01-30 2003-01-30 Semiconductor packaging member and method for making same Expired - Fee Related CN1288729C (en)

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