CN1228825C - Semiconductor chip package and process for making same - Google Patents

Semiconductor chip package and process for making same Download PDF

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Publication number
CN1228825C
CN1228825C CNB031019528A CN03101952A CN1228825C CN 1228825 C CN1228825 C CN 1228825C CN B031019528 A CNB031019528 A CN B031019528A CN 03101952 A CN03101952 A CN 03101952A CN 1228825 C CN1228825 C CN 1228825C
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Prior art keywords
chip
semiconductor chip
substrate
insulating barrier
chip package
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CNB031019528A
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CN1521816A (en
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普翰屏
黄建屏
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention relates to a semiconductor chip package structure and a producing method thereof. A chip is bonded on a substrate, and an insulating layer is coated on the substrate and the chip, so bonding wire pads of the substrate and chip electric contact points are exposed out of the insulating layer. A metal layer is then coated on the surface of the insulating layer, including the exposed parts, such as the bonding wire pads and the electric contact points. A plurality of conducting circuits which are electrically connected with the chip contact points and the bonding wire pads of the substrate are formed by patterning. Traditional bonding wire techniques are replaced. Problems, such as conducting wire pouring or short circuit, etc. are avoided in a package procedures, and meanwhile, bonding wire limitation caused by the reduction of chip size and welding pad gaps can also be overcome by utilizing the electric connection of the chip and the substrate of a circuit distribution technique. The present invention can meet the package requirements of the chip (such as smaller than 90 nanometers) of a novel generation.

Description

Semiconductor chip package and manufacture method thereof
Technical field
The invention relates to a kind of semiconductor chip package and manufacture method thereof, particularly about a kind of trend that cooperates chips welding spacing of new generation downsizing, in batch mode (BatchType) produces the semiconductor chip package and the manufacture method thereof of a plurality of high density packages on a slice carrier.
Background technology
Spherical grid array type (Ball Grid Array, BGA) the semiconductor packages operation is a kind of advanced semiconductor packaging, be characterized on substrate bonding semiconductor chip and impose bonding wire, make the lead that connects between chip and the substrate form electrical connection.
Along with the raising of chip integrated (Integration) degree, lead is laid quantity and is increased sharply, and therefore under limited chip area, has only the spacing distance (Pitch) between reduction lead and the lead, just may hold, lay more lead; But, dwindle wire pitch and will make between lead and the lead and draw closer together, in mold pressing procedure subsequently, regular meeting has influence on the quality of manufactured goods because of bonding wire skew (Wire Sweeping) causes short circuit (Short).
Increase the puzzlement that the wire-to-wire clearance caused diminishes for improving high-density semiconductor chip number of conductors, as shown in Figure 1, United States Patent (USP) the 5th, 581, proposed for No. 122 a kind of chip 11 peripheral with the wire bond pad 102 (Fingers) that provides lead 110 to weld between on substrate 10 surfaces, set up the semiconductor package part of ground loop 17 (Ground Ring) and power ring 18 (Power Ring), this encapsulating structure is set up ground loop 17 (power ring 18) around chip 11, and will be formed on ground connection weld pad numerous on chip 11 circuit face (power supply weld pad) (not icon) in the bonding wire mode, be electrically connected on this ground loop 17 (this power ring 18), make earth connection 112, power line 111 and be connected to that the holding wire 110 on the wire bond pad (not icon) is distributed in the different hierarchical spaces around the substrate 10, increase the spacing between the lead, reduce the thing that is short-circuited because of the lead skew and take place.
Though just said structure can increase the spacing between the lead, but at the more and more high and chip of wire density gradually under the trend of microminiaturization, the spacing (BondPitch) of each electrical contact of chip circuit surface is gradually reduced to 40 microns from 60 microns, even chip of new generation more narrows down to 30 microns, under same chip, can settle more I/O end (I/O Connection) like this, reach the target that reduces cost and promote the chip effect; Therefore said structure can't satisfy the integrated demand of chip height of new generation.
Have again, for the weld pad spacing that cooperates chip is constantly dwindled (Fine Pitch), provide the wire bond pad spacing (Bond Finger Pitch) of wire bonds also to be contracted to 125 microns on the substrate from 150 microns, the wire bond pad spacing of substrate of future generation more can narrow down to 100 microns, to adapt to the market mainstream that the weld pad spacing is dwindled.And the lead short circuit problem that the also unable solution of said structure causes because of weld pad spacing microminiaturization.
On the other hand,, carry out the welding of lead, can be subject to the limit of mechanical precision and meet with bottleneck with existing bonding equipment (Wire Bonder) if the electrical contact spacing of chip of new generation is contracted to 30 microns; And when forming, the substrate wire bond pad, make the spacing below 100 microns be difficult to have breakthrough again again often because of the restriction of etching technique.In addition, after the spacing of electrical contact is dwindled more, between the more difficult pilot of high-density wiring near or problem such as topple over, the enforcement that makes subsequent handling is difficulty more.
Adopt Flip Chip (Flip-chip Technology) to replace lead for this reason and solve above-mentioned bonding wire problem.But, use Flip Chip to form the high welding block of cost in the wafer operation stage; And the substrate of using as carries chips, for cooperating tiny welding block spacing (about 100 to 200 microns), need to replace the conventional substrate operation with increasing a layer technology (Build-up), can obviously improve the cost of substrate like this, can't accept (increase the laminar substrate cost and be generally more than five times of conventional substrate cost) for market.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of traditional bonding equipment (Wire Bonder) restriction that breaks through, make between chip and the substrate and needn't electrically connect, avoid the mold pressing processing procedure to cause the semiconductor chip package and the method for making thereof of bonding wire short circuit by bonding wire.
Another object of the present invention is to provide a kind of and needn't use expensive substrate to increase layer or welding block formation technology, the chip of new generation that promptly can be the reduction of electrical contact spacing provides the semiconductor chip package and the method for making thereof of electric connection.
A further object of the present invention is to provide a kind of bonding wire limit that overcomes, and meets the semiconductor chip package and the method for making thereof of chip of new generation (as the chip below 90 nanometers) encapsulation.
For reaching above-mentioned purpose, the manufacture method of semiconductor chip package of the present invention comprises the following steps: prefabricated-one substrate, this substrate has the front and the back side, pre-definedly on this substrate front side goes out the chip connecting area, and forms many wire bond pads on the substrate front side outside this chip connecting area; Bonding at least one chip on this chip connecting area, this chip has circuit face and inverter circuit face, forms a plurality of electrical contacts on the circuit face of this chip, and each corresponding wire bond pad of each electrical contact; The cloth insulating layer coating is to substrate, covering this chip circuit face and substrate front side, and exposes outside each electrical contact and each wire bond pad; On this insulating barrier, form metal level, in order to cover and to connect this electrical contact and wire bond pad; This metal level of patterning to form many conducting wires, makes an end of this conducting wire connect this electrical contact, and the other end connects the pairing wire bond pad of this electrical contact; Form insulating barrier, in order to cover this electrical contact, conducting wire and wire bond pad; And plant the back side of a plurality of soldered balls to this substrate, electrically connect for this chip and external device.
In other words, the present invention relates to a kind of manufacture method of semiconductor package, it is characterized in that, this manufacture method may further comprise the steps:
Prepare a substrate, this substrate has a positive and back side, pre-definedly on this substrate front side goes out a chip connecting area and a plurality of wire bond pads of formation on the substrate front side this chip connecting area outside;
Bonding at least one chip is to this chip connecting area, this chip has a circuit face and an inverter circuit face, be bonded to this chip at this chip with its inverter circuit face and connect in the district, and on this chip circuit face, form a plurality of electrical contacts, and each corresponding wire bond pad of each electrical contact;
Cloth covers one first insulating barrier to substrate, covers this chip circuit face and substrate front side, and exposes outside each electrical contact and each wire bond pad;
Form a metal level to this first insulating barrier, cover and connect this electrical contact and wire bond pad;
This metal level of patterning forms many conducting wires, makes this conducting wire one end connect this electrical contact, and the other end then connects the pairing wire bond pad of this electrical contact; Form one second insulating barrier, in order to cover this electrical contact, conducting wire and wire bond pad; And plant a plurality of soldered balls to this substrate back, electrically connect for this chip and external device.
Semiconductor chip package of the present invention comprises: a substrate, and it has the front and the back side, pre-definedly on this substrate front side goes out the chip connecting area, and is distributed with many wire bond pads on the outer substrate front side of this chip connecting area; At least one chip, sticking putting on this chip connecting area, this chip has circuit face and relative inverter circuit face, is formed with a plurality of electrical contacts on this circuit face, and each is corresponding mutually with a wire bond pad to make each electrical contact; Insulating barrier is that cloth is layed onto on the substrate, covering this chip circuit face and substrate front side, and exposes outside each electrical contact and each wire bond pad; Many conducting wires are formed on this insulating barrier, in order to electrically connect this electrical contact and wire bond pad; Insulating barrier is in order to cover this electrical contact, conducting wire and wire bond pad; And a plurality of soldered balls, be to plant at this substrate back, be electrically connected to external device for this chip.
In other words, the invention still further relates to a kind of semiconductor chip package, it is characterized in that, this encapsulating structure comprises:
One substrate, it has a positive and back side, pre-definedly on this substrate front side goes out a chip connecting area, and is distributed with a plurality of wire bond pads on the outer substrate front side of this chip connecting area;
At least one chip, sticking putting on this chip connecting area, this chip has a circuit face and a relative inverter circuit face, is formed with a plurality of electrical contacts on this circuit face, and each is corresponding mutually with a wire bond pad to make each electrical contact;
One first insulating barrier, cloth covers to substrate, covers this chip circuit face and substrate front side, and exposes outside each electrical contact and each wire bond pad;
Many conducting wires are formed on this first insulating barrier, in order to electrically connect this electrical contact and wire bond pad;
One second insulating barrier covers this electrical contact, conducting wire and wire bond pad; And
A plurality of soldered balls are to plant at this substrate back, are electrically connected to external device for this chip.
Semiconductor chip package of the present invention and manufacture method thereof, it is the conducting wire that forms the electrical contact and the substrate wire bond pad of a plurality of electric connection chips at encapsulated phase, the replacement lead is used for chip and substrate forms the relation that is electrically conducted, break through the mechanical limit of bonding equipment (Bonder) whereby, produce when avoiding mold pressing that lead is toppled over and problem such as short circuit, thereby solve the difficulty of the wire bonds that chip of new generation (as the chip below 90 nanometers) size and spacing reduction produced; Need not adopt simultaneously expensive welding block formation operation (covering brilliant operation) again or increase a layer technology, reach the effect that reduces packaging cost.
Description of drawings
Fig. 1 is a United States Patent (USP) the 5th, 581, looks schematic diagram on the semiconductor package part of No. 122 cases;
Fig. 2 is the generalized section of semiconductor chip package embodiment 1 of the present invention;
Fig. 3 A to Fig. 3 E is the integral manufacturing flow chart of the semiconductor chip package of Fig. 2;
Fig. 4 is the generalized section of the embodiment 2 of semiconductor chip package of the present invention;
Fig. 5 is the generalized section of the embodiment 3 of semiconductor chip package of the present invention;
Fig. 6 is the generalized section of semiconductor chip package embodiment 4 of the present invention.
Embodiment
Below cooperate Fig. 2 to Fig. 6, describe the embodiment of semiconductor chip package of the present invention and method for making in detail.Be noted that, it is graphic that Fig. 2 to 4 is the signal of simplification, only the mode with signal illustrates basic conception of the present invention, only show the assembly relevant in the accompanying drawing with the present invention, rather than component count, shape and size when implementing according to reality are drawn, form, quantity and the ratio of each assembly can arbitrarily change during its actual enforcement, and its assembly layout form may be more complicated.
Embodiment 1
As shown in Figure 2, semiconductor chip package 2 of the present invention comprises substrate 20; Be bonded in the semiconductor chip 21 on this substrate 20, be formed with a plurality of electrical contacts 212 on this chip 21, be formed on this substrate 20 many wire bond pads 202 in correspondence with each other; Covering the insulation insulating barrier 22 on the substrate 20, is to expose outside this electrical contact 212 and wire bond pad 202; Many the conducting wires 23 that are formed on this insulation insulating barrier 22 are used for electrically connecting this electrical contact 212 and wire bond pad 202; Cover the insulating barrier 24 of this electrical contact 212, conducting wire 23 and wire bond pad 202; And a plurality of soldered balls 25 that plant in this substrate 20 bottoms.
Below, describe the integral manufacturing flow process of above-mentioned semiconductor chip package in detail by Fig. 3 A to Fig. 3 E.
At first, see also Fig. 3 A.Prepared substrate 20 and at least one semiconductor chip 21, this substrate 20 generally is bismaleimide-triazine resin (Bismaleimide Triazine, BT) substrate, FR-4 substrate or ceramic substrate etc., it has front 200 and opposing backside surface 201, pre-definedly on these substrate 20 fronts 200 go out chip connecting area 200a, and be positioned at outside this chip connecting area 200a, wire bond pad accumulation regions 200b for many wire bond pads 202 (Fingers) distribution, each wire bond pad 202 is by the conductive trace 203 that runs through substrate 20, be communicated to the solder ball pad 204 (Ball Pads) at substrate 20 back sides 201, after making the signal of chip 21 be passed to substrate 20 and soldered ball (not icon), be delivered to the external world again by this wire bond pad 202.
Then, as shown in the figure, earlier the thickness with wafer is ground to below 3 mils (mil), cut into many single semiconductor chips 21 after, borrow adhesive 26 (as elargol), this chip 21 is bonded on the chip connecting area 200a.This chip 21 has circuit face 210 and inverter circuit face 211, is formed with a plurality of electrical contacts 212 (Electric Contacts) on this circuit face 210, and each electrical contact 212 is all corresponding mutually with a wire bond pad 202.
Secondly, see also Fig. 3 B, cloth insulating layer coating 22 on the front 200 of this substrate 20 and chip 21, this insulating barrier 22 is optional to be made by polyimides (Polyimide) or epoxy resin materials such as (Epoxy), by printing (Screen Printing) or rotary coating modes such as (Spin Coating), insulating material cloth is layed onto on substrate 20 positive 200 and chip 21 circuit face 210, and this electrical contact 212 and this wire bond pad 202 are exposed, other zone of substrate 20 is then covered by this insulating barrier 22.
Then, see also Fig. 3 C, utilize sputter (Sputtering) or electroless plating plated film modes such as (ElectrolessPlating), on the insulating barrier 22 that comprises exposed divisions such as this wire bond pad 202 and chip 21 electrical contacts 212, apply the coating metal layer 230 that materials such as plating one deck such as titanium, nickel vfanadium compound, titanium tungsten compound, chromium, nickel or copper form, as the knitting layer of coating; On this coating metal layer 230, plate the circuit cambium layer 231 of establishing one deck such as nickel dam, copper layer or metal materials such as nickel alloy, copper alloy afterwards, these chip 21 electrical contacts 212 can be electrically connected on the wire bond pad 202 of substrate 20 by two metal levels 230,231.
Afterwards, see also Fig. 3 D.On this electroplated metal layer 231 and substrate 20 back sides, be coated with photoresist layer 27 (Photoresist Layer) respectively, and cover with expose (Exposure) with light shield 28, development (Development) and etching operations such as (Etching), technology by this coating metal layer 230 of patterning (Pattern) and circuit cambium layer 231, form many one ends and connect this chip 21 electrical contacts 212, the other end connects the conducting wire 23 of substrate 20 wire bond pads 202, each chip 21 electrical contact 212 all can be electrically connected on the wire bond pad 202 of corresponding substrate 20, to replace traditional bonding wire operation by conducting wire 23.
See also Fig. 3 E.At metal level 230, after 231 patternings are finished, divest method or dry type divests method with wet type commonly used, remove the photoresist layer (not icon) on the back side 201 of this circuit cambium layer 231 and substrate 20, after making this electrical contact 212 lay metal level, can be electrically connected on substrate 20 wire bond pads 202 by this conducting wire 23.
See also Fig. 2 subsequently, utilize mold pressing or coating technique, epoxy resin (Epoxy) or polyimides insulating material such as (Polyimide) are covered on the front 200 of substrate 20, form an insulating barrier 24 that covers this electrical contact 212, conducting wire 23 and wire bond pad 202; And plant a plurality of soldered balls 25 at the back side 201 of substrate 20, form a spherical grid array type semiconductor packaging part with the conductive path that connects this electrical contact 212, conducting wire 23, wire bond pad 202, conductive trace 203 and soldered ball 25.
Embodiment 2
Fig. 4 is the embodiment 2 of semiconductor chip package of the present invention, operation and structure that embodiment 2 adopts are roughly identical with the foregoing description 1, difference is, the pre-defined chip 31 that supplies connects on the zone of putting on this substrate 30, also can offer the opening 300a of an area greater than this semiconductor chip 31, in the time of last, can borrow adhesive 36 with chip 31 cementations in opening 300a, by the difference in height between further reduction chip 31 circuit face 310 of taking in of this opening 300a and substrate 30 fronts 300, the whole height of semiconductor package part can be reduced so on the one hand, also the convenience that insulating barrier cloth covers operation can be promoted on the other hand.
Embodiment 3
Fig. 5 is the embodiment 3 of semiconductor chip package of the present invention, operation that this embodiment 3 adopts and structure and the foregoing description 1 are roughly the same, its difference is, after these insulating barrier 44 cloth cover and finish, expose opening 440 forming many on corresponding to earth lead 43 position of (referring to be used for the conducting wire of ground connection) on this insulating barrier 44, make and connect the heat sink of putting above insulating barrier 44 45, can expose opening 440 by this and be electrically connected to earth lead 43, thereby increase the radiating efficiency of packaging part and the effect of shield electromagnetic interference.
Embodiment 4
Fig. 6 is the embodiment 4 of semiconductor chip package of the present invention, operation that this embodiment 4 adopts and structure and the foregoing description are roughly the same, difference is, after these insulating barrier 54 cloth cover and finish, expose opening 540 forming many on corresponding to the position of this conducting wire 53 on this insulating barrier 54, for another packaging part or chip 55 storehouses and be electrically connected on the encapsulating structure of the foregoing description, thereby form a multi-chip module structure of highly amassing into change (Multi-chip Module, MCM).
In sum, utilize above-mentioned circuit laying technology, form many and electrically connect the electrical contact of chip and the conducting wire of substrate wire bond pad, can solve the bonding wire difficulty that chip of new generation (as the chip below 90 nanometers) causes because of the reduction of size and spacing, break through the mechanical limit of bonding equipment, problems such as the lead that has produced when having exempted mold pressing is toppled over, short circuit; Simultaneously, also need not to adopt expensive welding block formation technology or substrate to increase a layer technology, relatively meet the economic benefit in market with conducting wire electric connection chip and substrate.

Claims (27)

1. the manufacture method of a semiconductor package is characterized in that, this manufacture method may further comprise the steps:
Prepare a substrate, this substrate has a positive and back side, pre-definedly on this substrate front side goes out a chip connecting area and a plurality of wire bond pads of formation on the substrate front side this chip connecting area outside;
Bonding at least one chip is to this chip connecting area, this chip has a circuit face and an inverter circuit face, this chip is bonded to this chip with its inverter circuit face and connects in the district, and forms a plurality of electrical contacts on this chip circuit face, and the corresponding wire bond pad of each electrical contact;
Cloth covers one first insulating barrier to substrate, covers this chip circuit face and substrate front side, and exposes outside each electrical contact and each wire bond pad;
Form a metal level to this first insulating barrier, cover and connect this electrical contact and wire bond pad;
This metal level of patterning forms many conducting wires, makes this conducting wire one end connect this electrical contact, and the other end then connects the pairing wire bond pad of this electrical contact; Form one second insulating barrier, in order to cover this electrical contact, conducting wire and wire bond pad; And plant a plurality of soldered balls to this substrate back, electrically connect for this chip and external device.
2. the manufacture method of semiconductor chip package as claimed in claim 1 is characterized in that, this chip thickness wear down in advance becomes below 3 mils.
3. the manufacture method of semiconductor chip package as claimed in claim 1 is characterized in that, this first insulating barrier is to be made by a polyimides material that is electrically insulated.
4. the manufacture method of semiconductor chip package as claimed in claim 1 is characterized in that, this first insulating barrier is to be made by an epoxy resin material that is electrically insulated.
5. the manufacture method of semiconductor chip package as claimed in claim 1 is characterized in that, this metal level comprises a skim metal level and a circuit cambium layer.
6. the manufacture method of semiconductor chip package as claimed in claim 5 is characterized in that, this coating metal layer is to be formed on this first insulating barrier with sputtering way.
7. the manufacture method of semiconductor chip package as claimed in claim 5 is characterized in that, this coating metal layer is that the mode with the electroless plating plated film is formed on this first insulating barrier.
8. the manufacture method of semiconductor chip package as claimed in claim 5 is characterized in that, this coating metal layer is to be made by any material that is selected from titanium, nickel vfanadium compound, titanium tungsten compound, chromium, nickel or the copper.
9. the manufacture method of semiconductor chip package as claimed in claim 5 is characterized in that, this circuit cambium layer is to be formed on this coating metal layer with plating mode.
10. the manufacture method of semiconductor chip package as claimed in claim 5 is characterized in that, any metal material that this circuit cambium layer is selected from nickel dam, copper layer, nickel alloy or the copper alloy is made.
11. the manufacture method of semiconductor chip package as claimed in claim 1 is characterized in that, this first, second insulating barrier is to be made by epoxy resin or polyimide material.
12. a semiconductor chip package is characterized in that, this encapsulating structure comprises:
One substrate, it has a positive and back side, pre-definedly on this substrate front side goes out a chip connecting area, and is distributed with a plurality of wire bond pads on the outer substrate front side of this chip connecting area;
At least one chip, sticking putting on this chip connecting area, this chip has a circuit face and a relative inverter circuit face, is formed with a plurality of electrical contacts on this circuit face, makes each electrical contact corresponding mutually with a wire bond pad;
One first insulating barrier, cloth covers to substrate, covers this chip circuit face and substrate front side, and exposes outside each electrical contact and each wire bond pad;
Many conducting wires are formed on this first insulating barrier, in order to electrically connect this electrical contact and wire bond pad;
One second insulating barrier covers this electrical contact, conducting wire and wire bond pad; And
A plurality of soldered balls plant at this substrate back, are electrically connected to external device for this chip.
13. semiconductor chip package as claimed in claim 12 is characterized in that, is formed with an area on this chip connecting area greater than chip and the perforate that can take in for chip.
14. semiconductor chip package as claimed in claim 12 is characterized in that, this chip thickness wear down in advance becomes below 3 mils.
15. semiconductor chip package as claimed in claim 12 is characterized in that, this first insulating barrier is to be made by a polyimides material that is electrically insulated.
16. semiconductor chip package as claimed in claim 12 is characterized in that, this first insulating barrier is to be made by an epoxy resin material that is electrically insulated.
17. semiconductor chip package as claimed in claim 12 is characterized in that, this metal level comprises a skim metal level and a circuit cambium layer.
18. semiconductor chip package as claimed in claim 17 is characterized in that, this coating metal layer is to be formed on this first insulating barrier with sputtering way.
19. semiconductor chip package as claimed in claim 17 is characterized in that, this coating metal layer is that the mode with the electroless plating plated film is formed on this first insulating barrier.
20. semiconductor chip package as claimed in claim 17 is characterized in that, this coating metal layer is become by titanium, nickel vfanadium compound, titanium tungsten compound, chromium, nickel or copper.
21. semiconductor chip package as claimed in claim 17 is characterized in that, this circuit cambium layer is to be formed on this coating metal layer with plating mode.
22. semiconductor chip package as claimed in claim 17 is characterized in that, this circuit cambium layer is to be made by any metal material that is selected from nickel dam, copper layer, nickel alloy or the copper alloy.
23. semiconductor chip package as claimed in claim 12 is characterized in that, this second insulating barrier is to be made by epoxy resin or polyimide material.
24. semiconductor chip package as claimed in claim 12 is characterized in that, the position corresponding to this conducting wire on this second insulating barrier is formed with a plurality of openings that expose.
25., it is characterized in that this conducting wire is to electrically connect by this second an insulating barrier opening and a heat sink as claim 12 or 24 described semiconductor chip packages.
26., it is characterized in that this conducting wire is to electrically connect by this second an insulating barrier opening and a chip as claim 12 or 24 described semiconductor chip packages.
27., it is characterized in that this conducting wire is to electrically connect by this second insulating barrier opening and semiconductor packaging part as claim 12 or 24 described semiconductor chip packages.
CNB031019528A 2003-01-30 2003-01-30 Semiconductor chip package and process for making same Expired - Lifetime CN1228825C (en)

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CN102157502B (en) * 2011-03-23 2014-05-07 南通富士通微电子股份有限公司 System-in-package structure
WO2012126374A1 (en) 2011-03-22 2012-09-27 Nantong Fujitsu Microelectronics Co., Ltd. 3d system-level packaging methods and structures
WO2012126377A1 (en) 2011-03-22 2012-09-27 Nantong Fujitsu Microelectronics Co., Ltd. System-level packaging methods and structures
CN102157394A (en) * 2011-03-22 2011-08-17 南通富士通微电子股份有限公司 High-density system-in-a-package method
US9543269B2 (en) 2011-03-22 2017-01-10 Nantong Fujitsu Microelectronics Co., Ltd. System-level packaging methods and structures
US20140001622A1 (en) 2012-06-27 2014-01-02 Infineon Technologies Ag Chip packages, chip arrangements, a circuit board, and methods for manufacturing chip packages
US20150325748A1 (en) 2014-05-07 2015-11-12 Genesis Photonics Inc. Light emitting device
TWI641285B (en) 2014-07-14 2018-11-11 新世紀光電股份有限公司 Light emitting module and method for manufacturing light emitting unit
CN105322058A (en) * 2014-07-25 2016-02-10 新世纪光电股份有限公司 Manufacturing method of light emitting unit
CN107154385A (en) * 2016-03-04 2017-09-12 讯芯电子科技（中山）有限公司 Stack package structure and its manufacture method
JP6663965B1 (en) * 2018-10-04 2020-03-13 日本航空電子工業株式会社 Method of producing electronic component mounting structure, electronic component mounting structure, electronic component mounting module, and electronic component mounting wiring board
CN113707566B (en) * 2021-08-16 2024-06-25 矽磐微电子(重庆)有限公司 Method for manufacturing semiconductor structure and semiconductor structure

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