CN1344026A - 多芯片组件 - Google Patents
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Abstract
在母芯片上安装层叠芯片的多芯片组件中,提供芯片尺寸更小的多芯片组件。在母芯片的中央配置数字单元5,在其上安装层叠芯片10。将模拟单元4配置在母芯片的周围,在模拟单元4和数字单元5之间配置I/O单元组22。连接层叠芯片10和母芯片1的引线23和数字布线125不与模拟单元4交叉地连接I/O单元组22。由此,减少I/O单元区域6中配置的I/O单元数目,缩小I/O区域,缩小母芯片的尺寸。
Description
技术领域
本发明涉及在半导体芯片上安装其他半导体芯片的所谓多芯片组件,特别涉及在包含模拟单元的半导体芯片上安置其他半导体芯片的技术。
现有技术
半导体集成电路的集成度在年年提高,并且对各种电路进行集成,正在推进多功能化。为了实现更多功能化的半导体芯片,在半导体芯片(在本说明书中特别称为母芯片)上安置其他半导体芯片(在本说明书上称为层叠芯片)的所谓的多芯片组件正在实用化。多芯片组件通过重叠具有完全不同功能的芯片来缩小安装面积,并且通过减少在衬底上安装的芯片个数,可以降低电路的制造成本。
作为多芯片组件代表的应用例,可列举出在形成模拟、数字混载的运算电路或用于控制某些特定设备的控制电路的母芯片上,安装用于存储该电路使用的数据的DRAM(动态随机存取存储器)的层叠芯片的情况。
但是,目前的半导体芯片大多是模拟单元和数字单元混载的情况。模拟单元是将模拟值的信号用作数据的电路的总称,例如包括锁相环(PLL)、摸/数变换电路、数/模变换电路、相位比较电路等。数字单元是将数字值的信号用作数据的电路的总称,包括由各种逻辑电路构成的运算电路和存储器等。一般地,由于数字电路使用数字信号,在噪声强或微弱信号下也可以动作,所以可以高速动作、消耗功率低。通常的CD播放机和显示器等电子设备的控制,例如电机的转矩控制等,由于通过模拟信号来进行动作控制,所以例如控制电子设备动作的控制电路的输入输出需要模拟信号。因此,将模拟信号输入到这样的控制电路,将模拟信号变换为数字信号,进行各种运算处理,将其结果再次变换成模拟信号并输出到外部。因此,在电子设备的控制电路中大多使用模拟-数字混载的半导体芯片。
图5表示现有的多芯片组件,图5(a)表示其平面图,图5(b)表示其剖面图。母芯片101在衬底102上形成电路区域103,电路区域103的一部分成为模拟单元104,而另一部分成为数字单元105。母芯片101的周边部分配置将进行与芯片外部的信号授受的输入/输出单元(以下称为I/O单元)并列配置的I/O单元区域106。I/O单元区域106是多个I/O单元的集合体,各个I/O单元具有连接到模拟单元104和数字单元105的规定电路的布线、缓冲晶体管107、以及用于将它们与外部连接的键合焊盘108。缓冲晶体管107是用于放大(缓冲)内部使用的微弱信号以便输出到外部电路以及保护内部电路避免受到外部输入的信号中混入的噪声的影响而设置的,是与构成电路区域103的元件相比较,具有例如几百倍这样的非常大的尺寸的晶体管。键合焊盘108是用于在未图示的引线框架上引线键合的电极。半导体芯片内使用的所有信号通过I/O区域106与外部进行授受。
然后,在电路区域103上涂敷绝缘膜109,在其上安装层叠芯片110。层叠芯片110也有键合焊盘111,用引线112来与I/O单元区域106的键合焊盘108连接,层叠芯片110和电路区域103的规定电路进行连接。
例如如图6所示,电路区域103的模拟单元104将数字单元105的数字值的输出通过数/模变换电路121进行模拟变换,将通过I/O单元123向外部输出等的模拟值、例如电压值或电流值用作信号。为了正确地进行此时的信号授受,调整电路之间的阻抗和信号延迟等,将布线124、126的长度和宽度进行最佳化设计。
在这样的模拟单元104和布线124、126上交叉层叠芯片110的引线112时,引线112产生的电场成为噪声会传导给模拟单元104,使模拟单元104的工作产生不良,并且有特性恶化的危险。此外,由于从层叠芯片110上连接的I/O单元123配置在多数情况下连接到数字单元105的布线125,所以存在来自布线125的噪声也引起同样的问题的危险。因此,在通常的多芯片组件中,如图5所示,需要将模拟单元4分割配置在电路区域3的四角等,将层叠芯片的引线112配置在没有交叉的位置。
如上所述,在层叠芯片和I/O总线之间不能配置模拟单元104的情况成为母芯片的布局设计上的重大限制,要求进一步提高设计自由度。特别是在要配置的模拟单元的面积大、不能分割配置在四角的情况下,不得不放弃多芯片组件化。
此外,层叠芯片的引线键合的连接处大多数情况下是母芯片内部的规定电路,母芯片与外部的连接多为被限定在一部分上的电源等。尽管如此,用于引线键合的引线也不能交叉连接,由于需要将引线之间的角度均等地划分,所以所有引线被连接在I/O上的键合焊盘上,成为I/O总线的面积增大的主要因素。I/O总线的面积由于将I/O单元并列配置规定数目,所以需要多芯片组件的外周的长度。因此,无论将电路区域的部分缩小多少,只要不缩短I/O单元的长度,则产生不能将母芯片的面积进行进一步缩小的问题。
因此,本发明的目的在于提供设计自由度更高、面积更小的多芯片组件。
发明概述
本发明是用于解决上述课题的发明,是一种多芯片组件,包括:具有电路区域和多个键合焊盘的第1半导体芯片;以及具有多个键合焊盘并安装在第1半导体芯片上的第2半导体芯片;将第1和第2半导体芯片的键合焊盘通过引线键合来连接;其中,将第1半导体芯片的键合焊盘的至少一部分配置在电路区域的内部。
而且,所述电路区域有模拟单元和数字单元,将在该电路区域的内部配置的至少一个键合焊盘配置在模拟单元和数字单元之间。
而且,被重叠安装在第1半导体芯片上的数字单元上。
此外,提供一种多芯片组件,包括:第1半导体芯片,具有由电路区域、多个I/O单元组成的第1I/O单元组和多个I/O单元组成的第2I/O单元组;以及第2半导体芯片,具有由多个I/O单元组成的第3I/O单元组,并安装在所述第1半导体芯片上;第1I/O单元组的至少一部分用于连接外部电路,而第2I/O单元组和第3I/O单元组连接;其中,将第2I/O单元组的至少一部分配置在电路区域的内部。
而且,电路区域有模拟单元和数字单元,将在电路区域的内部配置的I/O单元组的至少一个配置在模拟单元和数字单元之间。
而且,被重叠安装在第1半导体芯片上的数字单元上。
而且,I/O单元有缓冲晶体管,第2I/O单元组中包含的缓冲晶体管与第1I/O单元组中包含的缓冲晶体管相比尺寸小。
附图的简要说明
图1是表示第1实施例的多芯片组件的图。
图2是表示第1实施例的母芯片的平面图。
图3是表示第2实施例的多芯片组件的图。
图4的表示第3实施例的多芯片组件的图。
图5是表示现有的多芯片组件的图。
图6是多芯片组件的局部放大图。
实施例
图1表示本发明第1实施例的多芯片组件,图1(a)表示其平面图,图1(b)表示其剖面图。母芯片1在衬底2上形成电路区域3,电路区域3的一部分为模拟单元4,不同的一部分为数字单元5。母芯片1的周边部分配置与外部进行信号授受的I/O单元区域6。I/O总线具有由连接到模拟单元4和数字单元5的规定电路的布线、缓冲晶体管7、以及将它们与外部连接的键合焊盘8组成的多个I/O单元。而且,在电路区域3上涂敷绝缘膜9,在其上安装层叠芯片10。层叠芯片10有多个键合焊盘11。以上具有与现有的多芯片组件相同的结构。而且,本实施例的多芯片组件是电子设备的控制电路,例如是仅处理DRAM这种数字电路信号的电路,层叠芯片10是DRAM。
本实施例的特征在于,在母芯片1的电路区域3的内部空出规定以上的间隔,将配置了键合焊盘20和缓冲晶体管21的I/O单元组22配置在层叠芯片10的四方,该键合焊盘20和层叠芯片10的键合焊盘11用引线23来相互连接。
这样,通过在电路区域3的内部设置用于与层叠芯片连接的I/O单元的I/O单元组22,从而减少I/O单元区域6中配置的I/O单元的数目,缩短I/O单元的长度,缩小I/O单元区域6的面积。由此,与现有的多芯片组件相比,使母芯片1的面积、即多芯片组件的面积缩小。
下面,说明本实施例的母芯片1上的电路配置。图2表示在本实施例的多芯片组件内除去层叠芯片10和引线23,仅示出母芯片1的电路配置。本实施例的电路区域3在其中心附近集中配置数字单元5,在电路区域3的周边部、即I/O单元区域6和数字单元5之间配置模拟单元4。I/O单元组22被配置在该数字单元5和模拟单元4之间。而且,如图1(a)所示,将层叠芯片10重叠配置在数字单元5上,通过引线23连接到数字单元5。数字单元5以具有至少可以将层叠芯片10重叠配置在其中心附近那样的宽部分来进行电路配置。
本实施例的多芯片组件由于将I/O单元组22配置在模拟单元4和数字单元5之间,并且将层叠芯片10重叠设置在数字单元5上,所以即使将I/O单元组22配置在电路区域3内,连接层叠芯片10和I/O单元组22的引线23、或如图6所示连结I/O单元123和数字单元105的布线125也不与模拟单元4交叉。
可是,本实施例的层叠芯片10是使用该运算电路的DRAM,被连接到数字电路5。即,层叠芯片10由母芯片1授受的数据都是数字数据,不进行模拟数据的授受。即使是这样的情况,也期望将I/O单元组22配置在模拟单元4和数字单元5之间,而不是数字单元5的内部。其原因在于,如果数字单元5包围配置在I/O单元组22的周围,则存在需要夹置I/O单元组22来连接数字单元5内部的元件的情况。当然,也可以对I/O单元组22进行迂回布线,但这种情况下,布线长度当然变长。此外,在使用进行自动布线设计的CAD软件的情况下,由于对这样的迂回不能进行最佳设计,所以需要用手工作业来设计,效率非常低。如果将I/O单元组22配置在模拟单元4和数字单元5之间,则容易将数字单元5的电路设计最佳化。
此外,层叠芯片10也可以重叠安装在数字单元5上。虽然由层叠芯片10的工作产生的电场和磁场会成为相对于模拟单元4的噪声源,但由于数字单元5使用数字数据,所以不易受到噪声的影响。
本实施例的I/O单元组22上配置的I/O单元与母芯片1的周边部分上配置的I/O单元区域6中配置的I/O单元一样,由缓冲晶体管21和键合焊盘20组成,但I/O单元组22中配置的缓冲晶体管21与I/O区域6的缓冲晶体管7相比较,尺寸可以缩小。这是因为I/O单元区域6的信号与母芯片1外部进行授受,与此相比,I/O单元组22使用的信号仅与被密封在多芯片组件内部的层叠芯片10进行授受,因而I/O单元组22的缓冲晶体管的驱动能力可以是较小的。此外,与外部连接的引线不同,由母芯片1和层叠芯片10之间的引线拾取能对电路产生损伤的噪声的概率也低,因而作为保护元件的缓冲晶体管用小尺寸就足够了。因此,I/O单元组22的I/O单元与I/O单元区域6中设置的I/O单元相比较,可以减小面积。因此,将本实施例的I/O单元区域6和I/O单元组22相加所得的面积比现有的I/O单元区域106的面积小。
此外,I/O单元组22上配置的I/O单元分别将缓冲晶体管21配置在数字单元5侧,将键合焊盘20配置在模拟单元4侧。层叠芯片10所连接的引线23越过缓冲晶体管21的上面被连接在键合焊盘20上。这是因为本实施例的层叠芯片10是DRAM,通过缓冲晶体管21连接到指定的数字单元5,如果将缓冲晶体管21配置在数字单元5侧,则可以进一步缩短布线长度。
图3表示本发明的第2实施例的多芯片组件。图3(a)是平面图,图3(b)是其剖面图。对于与第1实施例相同的结构附以相同的标号,并省略说明。
本实施例与第1实施例的差异在于,I/O单元组22在层叠芯片10的左右设置两处,沿层叠芯片10的上下方向来配置。本实施例与第1实施例相比较,是需要确保更大的数字单元5的情况。层叠芯片10上所连接的引线的一部分23’被连接到I/O单元区域6中配置的键合焊盘20’,通过缓冲晶体管21’连接数字单元5。
本实施例由于I/O单元区域23少,所以通过给模拟单元4、数字单元5分配更多的电路区域3的区域,缩小电路区域3。因此,一部分I/O单元被配置在I/O单元区域23。这样,通过将I/O单元配置在I/O单元区域23中,并配置在I/O单元区域6,将电路区域3的面积和I/O单元区域6的长度最佳化,可以将母芯片1设计得最小。
当然,如何配置I/O单元23,可以按照设计时的情况任意地配置。例如,如图4所示,也可以将层叠芯片10的两边所对应的I/O区域25合并配置。此外,也可以将任意的边所对应的I/O单元配置在I/O单元区域6。
如以上说明,由于本发明的多芯片组件将母芯片的键合焊盘的至少一部分配置在电路区域的内部,可以缩小I/O总线的面积,即可以缩短母芯片的外周长度,所以可以形成更小型的多芯片组件。此外,由于层叠芯片的引线23不延伸至母芯片外周部的I/O单元区域6,所以不需要将模拟单元4分割配置等,可以在高自由度下进行模拟单元4的设计。
而且,由于所述键合焊盘被配置在模拟单元和数字单元之间,所以与将模拟单元内部配置在数字单元内部相比较,可以缩短电路的布线长度,并且可以用设计软件将电路配置自动最佳化。
而且,由于层叠芯片被重叠安装在母芯片的数字单元上,所以可以防止因层叠芯片的工作所产生的噪声传导给模拟单元。
而且,由于电路区域内的I/O单元区域中配置的I/O单元的缓冲晶体管可以比母芯片周围的I/O总线上配置的I/O单元的缓冲晶体管小,所以能够使缓冲晶体管进一步小型化。
Claims (11)
1.一种多芯片组件,包括:具有电路区域和多个键合焊盘的第1半导体芯片;以及具有多个键合焊盘并安装在所述第1半导体芯片上的第2半导体芯片;将所述第1和第2半导体芯片的键合焊盘通过引线键合来连接;其特征在于:
将所述第1半导体芯片的键合焊盘的至少一部分配置在所述电路区域的内部。
2.如权利要求1所述的多芯片组件,其特征在于,所述电路区域有模拟单元和数字单元,将在所述电路区域的内部配置的键合焊盘的至少一个配置在所述模拟单元和数字单元之间。
3.如权利要求2所述的多芯片组件,其特征在于,所述第2半导体芯片被重叠安装在所述第1半导体芯片上的所述数字单元上。
4.一种多芯片组件,包括:第1半导体芯片,具有由电路区域、多个I/O单元组成的第1I/O单元组和多个I/O单元组成的第2I/O单元组;以及第2半导体芯片,具有由多个I/O单元组成的第3I/O单元组,并安装在所述第1半导体芯片上;
所述第1I/O单元组的至少一部分用于连接外部电路,而所述第2I/O单元组和所述第3I/O单元组连接;
其特征在于,将所述第2I/O单元组的至少一部分配置在所述电路区域的内部。
5.如权利要求4所述的多芯片组件,其特征在于,所述电路区域有模拟单元和数字单元,
将在所述电路区域的内部配置的I/O单元组的至少一个配置在所述模拟单元和数字单元之间。
6.如权利要求5所述的多芯片组件,其特征在于,所述第2半导体芯片被重叠安装在所述第1半导体芯片上的所述数字单元上。
7.如权利要求6所述的多芯片组件,其特征在于,所述I/O单元有缓冲晶体管,所述第2I/O单元组中包含的缓冲晶体管与所述第1I/O单元组中包含的缓冲晶体管相比尺寸小。
8.如权利要求1所述的多芯片组件,其特征在于,所述第2半导体芯片由数字电路构成。
9.如权利要求4所述的多芯片组件,其特征在于,所述第2半导体芯片由数字电路构成。
10.如权利要求1所述的多芯片组件,其特征在于,所述第2半导体芯片是DRAM。
11.如权利要求4所述的多芯片组件,其特征在于,所述第2半导体芯片是DRAM。
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CN100461398C (zh) * | 2004-02-26 | 2009-02-11 | 飞思卡尔半导体公司 | 具有交叉导体装配件的半导体封装件及制造方法 |
CN100573841C (zh) * | 2005-08-01 | 2009-12-23 | 松下电器产业株式会社 | 半导体装置 |
CN101577271B (zh) * | 2002-12-27 | 2012-08-08 | 株式会社半导体能源研究所 | 半导体器件以及其制作方法 |
CN103022005A (zh) * | 2012-12-22 | 2013-04-03 | 西安电子科技大学 | 一种基于外围垂直互连技术的叠层型3d-mcm结构 |
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JP2003108949A (ja) * | 2001-09-28 | 2003-04-11 | Rohm Co Ltd | 認証システム及び半導体装置 |
JP2004085366A (ja) * | 2002-08-27 | 2004-03-18 | Matsushita Electric Ind Co Ltd | マルチチップモジュールおよびそのテスト方法 |
US6977433B2 (en) * | 2003-10-28 | 2005-12-20 | Seagate Technology Llc | Multi function package |
US7166924B2 (en) * | 2004-08-17 | 2007-01-23 | Intel Corporation | Electronic packages with dice landed on wire bonds |
JP4958257B2 (ja) | 2006-03-06 | 2012-06-20 | オンセミコンダクター・トレーディング・リミテッド | マルチチップパッケージ |
JP5143413B2 (ja) * | 2006-12-20 | 2013-02-13 | オンセミコンダクター・トレーディング・リミテッド | 半導体集積回路 |
JP5453983B2 (ja) | 2009-07-28 | 2014-03-26 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
CN103858228B (zh) * | 2011-09-30 | 2016-11-09 | 富士电机株式会社 | 半导体装置及其制造方法 |
KR101898678B1 (ko) | 2012-03-28 | 2018-09-13 | 삼성전자주식회사 | 반도체 패키지 |
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Cited By (5)
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CN101577271B (zh) * | 2002-12-27 | 2012-08-08 | 株式会社半导体能源研究所 | 半导体器件以及其制作方法 |
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CN100573841C (zh) * | 2005-08-01 | 2009-12-23 | 松下电器产业株式会社 | 半导体装置 |
CN103022005A (zh) * | 2012-12-22 | 2013-04-03 | 西安电子科技大学 | 一种基于外围垂直互连技术的叠层型3d-mcm结构 |
CN103022005B (zh) * | 2012-12-22 | 2016-02-17 | 西安电子科技大学 | 一种基于外围垂直互连技术的叠层型3d-mcm结构 |
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