CN1333559A - 半导体器件及其制造方法、电路衬底及电子仪器 - Google Patents

半导体器件及其制造方法、电路衬底及电子仪器 Download PDF

Info

Publication number
CN1333559A
CN1333559A CN01125994A CN01125994A CN1333559A CN 1333559 A CN1333559 A CN 1333559A CN 01125994 A CN01125994 A CN 01125994A CN 01125994 A CN01125994 A CN 01125994A CN 1333559 A CN1333559 A CN 1333559A
Authority
CN
China
Prior art keywords
pressing mold
lead frame
semiconductor device
mentioned
die pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN01125994A
Other languages
English (en)
Other versions
CN1184678C (zh
Inventor
曾根广显
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of CN1333559A publication Critical patent/CN1333559A/zh
Application granted granted Critical
Publication of CN1184678C publication Critical patent/CN1184678C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

为了提供露出管芯垫片的半导体器件及其制造方法、电路衬底和电子仪器,引线框架10具有由第1和第2压模36和38夹持的部分,和比第1压模36凹部深度大的向下设置的管芯垫片14。在第1压模36凹部的底面上载有管芯垫片14,以活动状态在第1压模36上设置引线框架10。利用第2压模38把在引线框架10上的夹持部分压在第1压模36的方向上,进行模制工序。

Description

半导体器件及其制造方法、 电路衬底及电子仪器
本发明涉及半导体器件及其制造方法、电路衬底及电子仪器。
众所周知露出引线框架的管芯衬垫背面状态的封装。以前，关于该封装的制造工序，为了把管芯垫片压在金属膜内，在注入树脂时进行模压工序。但是，由于在管芯垫片和金属膜之间注入树脂，往往不能露出管芯垫片。
本发明用于解决上述的问题，其目的是提供能够露出管芯垫片背面的半导体器件及其制造方法，电路衬底及电子仪器。
(1)本发明的半导体制造方法，包含在第1和第2压模之间设置引线框架进行模压的工序、
上述的引线框架具有由上述第1和第2压模夹持的部分及设置在比上述第1压模的凹部深度大的向下的管芯衬垫，在所述第1压模的所述凹部底面上载有所述的管芯衬垫，在第1压模处以活动状态设置上述的夹持部分，用上述的第2压模把所述夹持部分压紧在上述的第1压模的方向，固定上述的引线框架。
按照本发明，第2压模根据引线框架的第1和第2压模压紧夹持部分，把管芯衬垫压在第1压模凹部的底面。由于在这种状态进行模压工序，在管芯衬垫和第1压模之间不能注入密封材料，能够使管芯衬垫的一部分露出封装。
(2)这种半导体器件的制造方法
所述的管芯衬垫的向下设置量D和用上述模压工序形成的封装厚度T之间具有下述关系
D＝(T/2)＋(0.1～0.2mm)
(3)这种半导体器件的制造方法
设置上述第1压模的引导销，在所述引线框架中形成孔穴，使所述引导销和所述孔穴互相配合，确定所述引线框架的位置，
上述的引导销具有锥形的尖端部和与所述第1压模垂直的基端部。
因此，引导销由于形成锥形尖端部，则容易插入引线框架的孔穴。还有，引导销在和第1压模垂直竖立的基部，孔穴的间隙小，则能够确定引线框架的正确位置。
(4)这种半导体器导件的制造方法
所述的引线框架具有外框，以及连接所述的管芯衬垫和所述的外框的吊脚、
所述的吊脚和所述的管芯衬垫形成大约15°以上的角度，来确保所述的外环的高度。
因此，由于吊脚和管芯衬垫的角度大(大约15°以上)，则能够防止吊脚附近密封材料的脱落。
(5)利用所述的方法制造本发明的半导体器件。
(6)本发明的电路衬底具有所述的半导体器件。
(7)本发明的电子仪器是具有所述的半导体器件的电子仪器。
图1是表示适用本发明实施例的引线框架的附图。图2是沿图1的II-II线剖开的剖面图。图3是沿图1的III-III线剖开的剖面图。图4(A)和图4(B)是说明适用本发明实施例半导体器件制造方法的附图。图5是说明适用本发明实施例半导体器件制造方法的附图。图6是说明适用本发明实施例半导体器件制造方法的附图。图7是说明适用本发明实施例半导体器件制造方法的附图。图8是表示适用本发明实施例的放载半导体器件的电路衬底的附图。图9是表示适用本发明实施例的具有半导体器件的电子仪器的附图。图10是表示适用本发明实施例的具有半导体器件的电子仪器的附图。
下面参照附图说明本发明的最佳实施例，但是本发明不限于本发明的实施例。
(引线框架)
图1是表示本实施例的引线框架的附图。图2是沿图1的II-II线剖开的剖面图。图3是沿图1的III-III线剖开的剖面图。图4(A)和图4(B)是说明模制工序的附图。
加工铜系列和铁系列板材形成引线框架10。该加工方法采用化学腐蚀和机械冲切方法。引线框架10具有外框12。外框12形成长方形的情况多，外框12的形状成为引线框架10的外形。
外框12至少形成一个孔穴(夹具孔穴)16。在孔穴16中，插入设置在模制用的第1压模中的引导销40(参看图4(A)。以此，能够简单地确定相对引线框架10的第1压模36的位置。在外框12两端部的各端，也可至少形成一个孔穴16。在这种情况，在外框12一端部(例如，在图1左侧端部)形成的孔穴16和在外框12另一端部(例如，在图1右侧端部)形成的孔穴16，最好形成在偏离外框12的长方向(例如图1的上下方向)的位置上。这样，不会弄错方向，能够把引线框架10设置在第1压模36上。
引线框架10至少具有一个(在图1仅仅表示一个，但是一般表示多个)管芯衬垫14是放载半导体芯片30(参照图4A)等电子部的部分，形成矩形(特别是正方形)的情况多。管芯衬垫14通过吊脚(连杆或悬吊引线)20连接外框12。
吊脚20如图3那样进行弯曲，管芯衬垫14从外框12开始移位。在管芯衬垫14，离开外框12的对面，载放半导体芯片30。也就是，在下面设置管芯衬垫14。
本实施例象图4(A)所示那样，在比第1压模36的凹部(在模制时形成模槽的区域)深度大的向下设置管芯衬垫14。也就是，从第1压模36夹持部分，使引线框架10的夹持部分(外框12，外部引线26和连接部分28中的至少一个)成为活动状态，来设定管芯衬垫14的向下深度D。最好设置引线框架10的活动距离h为0.1mm以上。这样，如图4(B)所示，通过第2压模38把引线框架10的夹持部分压在第1压模36的方向，因此能够把引线框架14压在第1压模36进行模压工序。因此，能够防止在在管芯衬垫14和第1压模36之间注入密封材料48。
还有，在外引线26从利用密封材料48形成的封装厚度的大致中间引出的情况下，如图4(A)和图4(B)所示，管芯衬垫14的向下设置量D和利用模制工序形成封装厚度T的关系最好是：
D＝(T/2)＋(0.1～0.2mm)
这样，如图4(A)所示，在第1压模36上设置引线框架14时，能够把引线框架14的夹持部分(外框12，外部引线26和连接部分28)活动在第1压模36上。
还有，本实施例如图4(A)或图4(B)所示，这样设定管芯衬垫14，使内引线24的位置比半导体芯片30的焊盘区(没有图示)高。吊脚20和管芯衬垫14的角度(吊脚20的弯曲度)α，优选是15°以上，更好是30°以上。这样，如图4(B)所示，在吊脚20以陡峭角度深深地注入密封材料48，则在吊脚20附近不能脱落密封材料。
引线框架10具有多个引线22。从外框12向管芯垫片14延伸，设置引线22。具体地说，引线22包括内引线24和外引线26。内引线24是用密封材料48(参看图8)在半导体器件上密封的部分，外引线26是从密封材料48引出的部分及和外部电气连接的部分。
外引线26和矩形的管芯垫片14的各边垂直，从外框12伸出。内引线24从外引线26向管芯垫片14的中央部分倾斜延伸。通过连接部分(ダムバ-)28连接相互邻接的引线22。具体地说，连接部分28，对于相互邻接的外引线，连接内引线24的接近部分。
本实施例的引线框架10，除了所述的构成外，众所周知的引线框架的构成也适用。
(半导体器件的制造方法)
图4(A)和图4(B)是说明本发明实施例的半导体器件的制造方法的附图。
首先，准备所述的引线框架10，把半导体芯片30固定在管芯垫片14上(焊接管芯工序)。例如，利用粘结剂32连接管芯垫片14和半导体芯片30。作为连接剂32，采用热固化性树脂为宜，也可以采用热传导率高的材料，例如，金属软膏(银膏等)。还有，在焊接芯片工序之前，如图3所示，先把吊脚20弯曲，也可以在焊接芯片工序之后再把吊脚20弯曲。
接着，进行焊接引线工序。例如，把引线34(参看图(4A)焊接在半导体芯片30的焊盘(没有图示)和内引线24(参看图1)上。在该工序，能够使用众所周知的引线焊接器。但是，本实施例因为设定内引线位置比半导体芯片30的焊盘高，所以能够相应这个位置来调整引线34环线的高度。
接着，进行模制工序。具体地说，如图4(A)所示，在模制用的第1压模(例如，金属压模)36上，设置放载半导体芯片30的引线框架10。然后，利用第1压模36和第2压模(例如，金属压模)38夹持引线框架10。在第1压模36和第2压模38，分别形成凹部，利用两个凹部形成压模的空腔。
第1压模36凹部的周围部分，用于夹持引线框架10一部分。在夹持第1压模36引线框架10一部分的部分，设置引导销40。在第2压模38凹部的周围部分(用于夹持引线框架的一部分)，形成避开引导销40的孔穴46。
引导销40具有形成锥形的尖端部42和与第1压模36垂直的基端部44。由于尖端部42的尖端变细，则容易插入引线框架10的孔穴16。基端部44，由于把它制成接近(稍微变小)引线框架10的孔穴16的尺寸，能够以小的间隙把基端部44插入孔穴16，进行固定引线框架10的位置。并且，基端部44和第1压模36垂直地竖立。因此，引线框架10的孔穴16附近部分活动在第1压模36上，能够决定引线框架10的位置。作为它的前提，引线框架10的活动距离必须是在基端部44的高度范围内。
这样设置引线框架10，使管芯衬垫14和第1压模36的凹部底面接触。并且，从夹持第1压模36的，引线框架10局部(具体地说包括外引线26，连接部分28，外框12等)的部分，把该引线框架10的夹持部分(第1压模36凹部的周围部分)变成活动状态。
引线框架10活动距离h，最好是大约0.1mm以上。这样，如图4(B)所示，利用第2压模(例如金属膜)38把引线框架10压在第1压模36上，因此，能够把管芯衬垫14压在第1压模36上进行模压工序。由此，能够防止使密封材料进入管芯衬垫14和第1压模36凹部底面之间。
当从用密封材料48密封的封装厚度的大致中间引出外引线26的情况时，如图4(A)和图4(B)所示，则管芯衬垫14的向下设置量D和用模制工序形成封装厚度T的关系最好是：
D＝(T/2)＋(0.1～0.2mm)
这样，如图4(A)所示，在第1压模设置引线框架10时，能够从第1压模活动引线框架10。
然后，利用密封材料(模制树脂)48密封半导体芯片30、引线34和内引线24。作为密封材料，多用热固化树脂。
本实施例，由于把管芯垫片14压在第1压模36凹部的底面进行模制工序，所以在管芯垫片14和第1压模36难以之间注入密封材料。结果，在管芯垫片14上难以作变动。
图5表示，固化密封材料48，从第1和第2压模36和38取出的引线框架10。还有，用从图1所示引线框架10背面所见的状态，表示图5所示的引线框架10。如图5所示，从密封材料48露出的管芯垫片14的一面。在这种状态，如果在引线22表面发生变动，就进行变动工序。
其次，如图6所示，进行第一修剪工序。也就是，连接引线22，切断连接部分28。切断连接部分，接着进行电解电镀工序，可在连接部分28断面上进行电镀。在本实施例，此时还没有切断吊脚20。
然后进行电解电镀工序。也就是，从引线框架10的密封材料48露出的部分，形成焊料(ロゥ)(例如焊锡)和锡等金属膜。
例如，多个外引线26和外框12相连，通过外框12电气连接，所以能够电解电镀。还有，管芯垫片14通过吊脚20和外框12连接，因为通过吊脚20电气连接，所以可能电解电镀。这样，由于形成金属膜，所以提高耐蚀性。还有，如果进行焊锡等焊料的电镀，则能够容易地进行外引线26和布线图形的连接，管芯垫片14和放热部件54(参看图8)的连接。
接着，如图7所示，进行第2修剪工序。也就是，从外框12切断外引线，除掉吊脚20。接着，如果需要，则进行加标记工序，然后进行成形工序。也就是，在电路衬底上以容易安装的形态弯曲外引线26。可以同时进行第2修剪工序和成形工序。以后，还进行检查等工序，经过以上工序，则能够制造半导体器件。
(半导体器件和电路衬底)
图8表示本发明的半导体器件。本实施例的半导体器件具有半导体芯片30，引线框架14和密封48材料。管芯垫片14的一面，从密封材料48中露出。
本实施例，如图3所示，因为吊环20的弯曲角度大(15度以上)，能够把吊脚20深深地插入密封材料48中，所以难于发生密封材料48的脱落。
在图8中，把半导体器件安装在电路衬底50上。电路衬底50，例如，一般采用玻璃环氧树脂衬底等有机系衬底。在电路衬底50上，例如由铜等形成所希望电路的布线图形52，连接布线图形52和半导体器件的外引线26。还有，在电路衬底50上，设置放热部件(散热支座)54，把放热部件54和半导体器件的管芯垫片14相互连接。这样，能够把半导体器件30产生的热量，通过管芯垫片14从放热部件54散发出去。本实施例半导体器件的其它构成，按照所述的引线框架14和半导体器件的制造方法进行说明。
并且，作为本发明的具有半导体器件的电子仪器，有如图9所示的笔记本型个人计算机100和如图10所示的移动电话200。

Claims (7)

1.半导体器件的制造方法，包括在第1和第2压模之间设置引线框架进行模制的工序，
上述的引线框架具有由上述第1和第2压模夹持的部分及设置在比上述第1压模的凹部深度大的向下的管芯衬垫，在所述第1压模的所述凹部底面上载有所述的管芯衬垫，从第1压模处以活动状态设置上述的夹持部分，用上述的第2压模把所述夹持部分压紧在上述的第1压模的方向，固定上述的引线框架。
2.按照权利要求1所述的半导体器件的制造方法
管芯衬垫14的向下设置量D和用所述的模制工序形成封装厚度T的关系是：
D＝(T/2)＋(0.1～0.2mm)
3.按照权利要求1或权利要求2所述的半导体器件的制造方法
在所述的第1压模设置引导销，在所述的引线框架形成孔穴，使所述的引导销和所述的孔穴相互配合，确定所述的引线框架的位置，
所述的引导销具有锥形的的尖端部和与所述的第1压模垂直竖立的基端部。
4.按照权利要求1到权利要求3中任何一个所述的半导体器件的制造方法
所述的引线框架具有外框和连接所述的管芯垫片与所述的外框的吊脚，
所述的吊脚以和所述的管芯垫片成15°以上的角度形成，来确保所述的向下设置量。
5.按照权利要求1到权利要求4中任何一个所述的半导体器件的制造方法制造的半导体器件。
6.具有按照权利要求5所述的半导体器件的电路衬底。
7.具有按照权利要求5所述的半导体器件的电子仪器。
CNB011259949A 2000-07-05 2001-07-04 半导体器件及其制造方法、电路衬底及电子仪器 Expired - Fee Related CN1184678C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP204014/2000 2000-07-05
JP2000204014A JP2002026044A (ja) 2000-07-05 2000-07-05 半導体装置及びその製造方法、回路基板並びに電子機器

Publications (2)

Publication Number Publication Date
CN1333559A true CN1333559A (zh) 2002-01-30
CN1184678C CN1184678C (zh) 2005-01-12

Family

ID=18701343

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB011259949A Expired - Fee Related CN1184678C (zh) 2000-07-05 2001-07-04 半导体器件及其制造方法、电路衬底及电子仪器

Country Status (4)

Country Link
US (1) US6617200B2 (zh)
JP (1) JP2002026044A (zh)
CN (1) CN1184678C (zh)
TW (1) TW519737B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103943514B (zh) * 2014-05-12 2016-08-24 成都先进功率半导体股份有限公司 一种防止引线框架振动的压紧装置

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004084317A2 (en) * 2003-03-20 2004-09-30 Firecomms Limited An optical sub-assembly for a transceiver
US6921974B2 (en) * 2003-03-28 2005-07-26 United Test & Assembly Center Ltd. Packaged device with thermal enhancement and method of packaging
US7109064B2 (en) * 2003-12-08 2006-09-19 Semiconductor Components Industries, L.L.C. Method of forming a semiconductor package and leadframe therefor
US7582951B2 (en) * 2005-10-20 2009-09-01 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages
US7714453B2 (en) 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8183680B2 (en) 2006-05-16 2012-05-22 Broadcom Corporation No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement
US7808087B2 (en) 2006-06-01 2010-10-05 Broadcom Corporation Leadframe IC packages having top and bottom integrated heat spreaders
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
US8183687B2 (en) * 2007-02-16 2012-05-22 Broadcom Corporation Interposer for die stacking in semiconductor packages and the method of making the same
US7872335B2 (en) * 2007-06-08 2011-01-18 Broadcom Corporation Lead frame-BGA package with enhanced thermal performance and I/O counts
JP2010140930A (ja) * 2008-12-09 2010-06-24 Denso Corp モールドパッケージの製造方法
CN104465588B (zh) 2013-09-25 2018-11-02 恩智浦美国有限公司 具有应力释放和散热器的半导体封装件
JP7253201B2 (ja) * 2019-08-22 2023-04-06 株式会社デンソー 液剤の塗布装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3672046A (en) * 1970-01-14 1972-06-27 Technitrol Inc The method of making an electrical component
JP3022393B2 (ja) * 1997-04-21 2000-03-21 日本電気株式会社 半導体装置およびリードフレームならびに半導体装置の製造方法
JP2907186B2 (ja) * 1997-05-19 1999-06-21 日本電気株式会社 半導体装置、その製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103943514B (zh) * 2014-05-12 2016-08-24 成都先进功率半导体股份有限公司 一种防止引线框架振动的压紧装置

Also Published As

Publication number Publication date
JP2002026044A (ja) 2002-01-25
US20020022304A1 (en) 2002-02-21
CN1184678C (zh) 2005-01-12
TW519737B (en) 2003-02-01
US6617200B2 (en) 2003-09-09

Similar Documents

Publication Publication Date Title
CN1184678C (zh) 半导体器件及其制造方法、电路衬底及电子仪器
CN1104045C (zh) 利用偏离连线和支撑块空腔制造双面连线集成电路封装
CN1146044C (zh) 具有弯成j-型引线端子的半导体器件
CN1191629C (zh) 引线框、半导体装置及其制造方法、电路基板和电子装置
CN102244057B (zh) 半导体封装及其制造方法
CN100576477C (zh) 形成引脚模块阵列封装的方法
CN1163478A (zh) 电子组件与其制造方法及其所用的引线架与金属模
US20070001276A1 (en) Semiconductor device and portable apparatus and electronic apparatus comprising the same
CN1197292A (zh) 一种半导体器件引线框架及引线接合法
CN1461053A (zh) 导线接合性增强的半导体器件组件
CN1751390A (zh) 包括无源器件的引线框架
CN1530978A (zh) 芯片式电容及其制造方法以及模制模具
CN1457094A (zh) 半导体器件及其制造方法
CN101060090A (zh) 半导体装置的制造方法
CN1309071C (zh) 引线框架以及制造该引线框架的方法
CN1961415A (zh) 灵活的引线框架结构以及形成集成电路封装件的方法
CN1559085A (zh) 半导体装置及其制造方法
CN1855450A (zh) 高散热性的半导体封装件及其制法
CN1192420C (zh) 半导体器件及其制造方法、电路基板及电子装置
TWI294680B (zh)
CN1126161C (zh) 半导体晶片的封装方法及其成品
CN1208821C (zh) 半导体晶片的封装方法及其成品
US20040119146A1 (en) Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
CN2779610Y (zh) 导线架型电气封装体
CN115206922A (zh) 带外露系杆的电子器件

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20050112

Termination date: 20130704