CN1312767C - 电源电路装置 - Google Patents

电源电路装置 Download PDF

Info

Publication number
CN1312767C
CN1312767C CNB028016270A CN02801627A CN1312767C CN 1312767 C CN1312767 C CN 1312767C CN B028016270 A CNB028016270 A CN B028016270A CN 02801627 A CN02801627 A CN 02801627A CN 1312767 C CN1312767 C CN 1312767C
Authority
CN
China
Prior art keywords
pin
circuit device
mosfet
interval
power circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB028016270A
Other languages
English (en)
Other versions
CN1462476A (zh
Inventor
土田满穗
池田宪史
西川円
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Components Industries LLC
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN1462476A publication Critical patent/CN1462476A/zh
Application granted granted Critical
Publication of CN1312767C publication Critical patent/CN1312767C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

现有技术的功率MOSFET是单块集成电路装置和复合元件等的电源电路装置，从封装引出的引脚是等间隔的5个管脚，不能充分保证成为高电位的第三管脚与相邻的其它管脚距离，不很安全。本发明使第三管脚与相邻的其它管脚的距离比其它管脚彼此的距离宽，而且，使第三管脚在上段、相邻的其它管脚在下段、它们以外的管脚在中段而进行成形。因此由于能充分确保高电位的第三管脚和相邻的其它管脚的距离，成为非常安全的结构。而且由于做成整体模制封装，顶部不外露，操作也很容易。

Description

电源电路装置
技术领域
本发明涉及电源电路装置，特别涉及使用从封装主体导入的对导线形状进行了改良的IC封装的电源电路装置。
背景技术
众所周知，现在采用IC芯片和导线(引脚)用引线接合法等连接，用树脂构成的封装主体为外装的IC封装。
图2表示对现有的IC封装有5根引脚的情况，图2(A)是俯视图，图2(B)是图2(A)的B-B剖面图，图2(C)是从箭头方向看图2(B)的侧视图。
包含功率MOSFET11的单块集成电路和复合元件等，为了在功率MOSFET11上安装IC12，一般使用5根管脚间隔(d3)相等的引脚。根据图2(A)，该封装主体13的一个侧壁上设置5根引脚14。此时，中心的第三管脚14c与MOSFET的漏极端子、第五管脚14e与源极端子相连，第一管脚14a、第二管脚14b和第四管脚14d连接在IC的控制端子上。由于通常MOSFET11的漏极端子是高电位，源极端子GND接地，为了使这两个端子形成非常大的电位差，使用第三管脚14c、第五管脚14e以使引脚14不邻接。
在图2(B)中表示安装该封装时的成形。如图所示，第一管脚14a、第三管脚14c和第五管脚14e向上方弯折，得到了相邻的第二管脚14b和第四管脚14d的沿表面距离(参照图2(C))。这是一种方法，用于抑制将这样构成的IC封装通过焊接安装在电路基板面上时相邻引脚彼此的短路和在印刷基板焊接连接时产生的焊接电桥。
一般在安装的情况下，引脚的间隔是等间隔(d3)内部元件的里面连接在中央的管脚上。即功率MOSFET是通过其里面的漏极电极用导电的粘接剂等直接粘接。功率MOSFET的封装一般是三个管脚，成为高电位的漏极充分得到了连接的端子(中央的端子)和相邻的其它端子的沿表面距离。然而，包含所述的功率MOSFET的单块集成电路和复合元件等，为了将IC实际安装在功率MOSFET上，一般使用5根等间隔的引脚。该情况由于还是中央的第三管脚与功率MOSFET的漏极电极相连接，在装载800伏等耐压的高功率MOSFET时，用等间隔的引脚不能充分保证与相邻的其它管脚的沿表面距离。也就是用焊接方法将这种结构的IC封装装在电路基板面上时，成为高电位的第三管脚和相邻的第二、第四管脚的沿表面距离小，存在容易由尘埃等引起短路的问题。而且在印刷基板上焊接连接时，由于焊料比引脚之间更宽，存在容易产生焊接电桥的问题。例如操作电压为700伏时，沿表面距离必须做成1.9mm。现有结构中即使把引脚做成上下弯曲的形状，在沿表面距离只能确保1.7mm时恐怕也不能满足安全标准。即现有的引脚结构不能充分确保沿表面距离。
而且，现有的封装以与第三管脚形成一体等方式连接的顶部14h部分虽然成为800伏等的高电位的漏极连接，但也做成裸露的结构，在产品操作方面存在不太安全的问题。
发明内容
本发明是鉴于有关课题作出的。
第一，本发明是电源电路装置，其包括MOSFET、密封该MOSFET的封装和从该封装主体的一个侧壁引出的多个引脚，并将所述MOSFET的漏极端子连接在该多个引脚中中央的引脚上，其特征在于：在所要求的沿表面距离设置间隔，该间隔是使成为高电位的所述中央的引脚的根部与相邻的其它引脚的根部的间隔，并且作得比所述其它引脚彼此的根部的间隔大。
所述封装是整体模制结构。
在所述的MOSFET上安装IC。
另外，通过以下的本发明是电源电路装置结构来解决所述问题，即，所述相邻的其它的引脚在下段、所述中央的引脚在上段和不相邻的其它的引脚在上段与下段之间的中段进行弯折。
所述封装是整体模制结构。
在所述的MOSFET上安装IC。
第三，通过以下的本发明是电源电路装置结构来解决所述问题，即，其包括MOSFET、密封该MOSFET的封装和从该封装主体的一个侧壁引出的五根引脚，将所述MOSFET的漏极端子连接在位于中央的第三引脚上，其特征在于：使成为高电位的第三引脚的根部和相邻的其它引脚的根部的间隔比所述其它引脚彼此的根部的间隔大，所述第三引脚和相邻的低电位的第二及第四引脚设置为所要求的的沿表面距离
在下段弯折所述第二及第四引脚，在上段弯折所述第三引脚，在上段和下段之间的中段弯折所述第一及第五引脚。
所述封装是整体模制结构。
在所述的MOSFET上安装IC。
即本发明通过扩大成为高电位的第三管脚和相邻的其它引脚的间隔而将引脚成形为上、中、下三个台阶，确保足够安全的沿表面距离。
本发明提供一种封装，由于通过将封装主体做成整体模制的结构，与第三管脚在同一工序形成的封装里面的框架没有露出，故作为漏极端子即使遇到高压也可以安全地操作。
附图说明
图1(A)是说明本发明的电源电路装置的俯视图，图1(B)是图1(A)的A-A剖面图，图1(C)是从箭头方向看图1(B)的侧视图；
图2(A)是说明现有技术的电源电路装置的俯视图，图2(B)是图2(A)的B-B剖面图，图2(C)是从箭头方向看图2(B)的侧视图。
具体实施方式
以5根引脚的封装为例，参照图1详细说明本发明具体实施方式。
图1(A)是俯视图，图1(B)是图1(A)的A-A剖面图，图1(C)是从箭头方向看图1(B)的侧视图。
本发明的电源电路装置由MOSFET1、IC2、封装3和5根的引脚4构成。
MOSFET1其中包含多个MOSFET的元件，里面是漏极电极，用导电的粘接剂固定在以与第三管脚4c形成一体等方式连接的顶部4h上(参照图1(B))。
IC2装在MOSFET1上，与MOSFET1的电源电极和漏极电极连接。而且各控制端子连接在第一管脚4a、第二管脚4b和第四管脚4d上(参照图1(B))。
封装3通过传递模塑法等，用绝缘树脂密封MOSFET1和IC2。由于封装3是整体模制结构，故直到MOSFET1的漏极电极固定粘接的导线的顶部4h的里面都用树脂覆盖。由于加高电压的顶部4h不露出，产品的操作非常安全。
5根中的引脚4从封装主体3的一个侧壁引出。在此，如图，从端部的管脚假设为第一管脚4a、第二管脚4b、第三管脚4c、第四管脚4d和第五管脚4e。位于中央的第三管脚4c以与顶部4h形成一体等连接，在顶部4h中连接MOSFET1的漏极电极，使第三管脚4c成为漏极端子；第五管脚4e成为源极端子；第一管脚4a、第二管脚4b及第四管脚4d成为IC2的控制端子。电位最高的第三管脚4c和相邻的第二管脚4b及第四管脚4d的间隔d2确保满足安全标准的沿表面距离，比其它管脚彼此的间隔，即第一管脚4a到第二管脚4b的间隔d1及第四管脚4d到第五管脚4e的间隔d1更宽。具体地讲，如假设第三管脚4c到第二管脚4b或第三管脚4c到第四管脚4d的间隔d2为2.54mm，第一管脚4a到第二管脚4b的间隔d1及第四管脚4d到第五管脚4e的间隔d1为0.5mm。例如动作电压为700伏时，安全的沿表面距离为1.9mm，800伏时为2.1mm，根据本发明的结构，成为高电压的第三管脚4c和第二管脚4b及第四管脚4d的间隔变得足够大。
而且，如图1(B)和图1(C)所示，将从封装3引出的引脚4在上下方向即相对顶部4h垂直的方向弯折、成形，使得其成为上段、下段、中段三个台阶。在此，以引出第二管脚4b和第四管脚4d的原状作为下段，使第三管脚4c在最高位置上成形作为上段，使第一管脚4a和第五管脚4e在位于上段和下段之间的位置成形作为中段。具体地讲，下段和中段的间隔h1为2.3mm，中段和上段的间隔h2为2.8mm。而且，根据成形的角度焊接的引脚4的前端部按照要求的距离可以在上下方向上加大。
本发明的特征在于引脚的配置。由于成为高电位的第三管脚和与其相邻的第二管脚和第四管脚的间隔比第一管脚和第二管脚及第四管脚和第五管脚的间隔宽，故相对顶部4h可确保在水平方向的沿表面距离。而且，由于将第三管脚在上段、第一和第五管脚在中段、第二和第四管脚在下段而进行成形，在相对顶部4h垂直的方向上也扩大了第三管脚和相邻的第二和第四管脚的沿表面距离。
如上所述，虽然在成形前的台阶上可以得到足够的沿表面距离，但由于往印刷基板上安装时焊料在印刷基板上扩大，为了防止由焊接电桥产生的短路和由尘埃产生的短路，最好尽可能地确保沿表面距离。也就是说，通过在将引脚间隔在水平方向分开的基础上进行3段成形，使电压最高的第三管脚在上段、相邻的第二、第四管脚在下段，在垂直的方向上也扩大了沿表面距离，防止了短路，实现了满足安全要求的封装。
由于封装是整体模制结构，在里面固定成为高电位的漏极电极的顶部4h的里面不外露，故容易保证产品的使用安全。
根据本发明，通过使成为高电位的第三管脚和与其相邻邦的其它引脚的间隔比其它的引脚彼此的间隔扩大，相对顶部4h可确保在水平方向上的沿表面距离。而且，由于第三管脚在上段、第一和第五管脚在中段、第二和第四管脚在下段而进行成形，在相对顶部垂直的方向上也隔离开，更扩大了第三管脚与相邻的第二和第四管脚的沿表面距离。只要沿表面距离加宽，就可以防止由在印刷基板上焊接电桥产生的短路和由尘埃等产生的短路。
具体地讲，如800伏的情况必须有2.1mm的沿表面距离，现有的等间隔的5根管脚只能确保沿表面距离为1.7mm，是不够安全的。但根据本发明的结构，由于第三管脚与相邻的第二和第四管脚的间隔被扩大到2.54mm，而且，在上段和下段得到5.8mm的距离，根据成形的角度，在引脚的前端部可以进一步扩大距离，故可确保足够安全的沿表面距离。
封装是整体模制结构。由于在里面固定成为高电位的漏极电极的顶部的里面不外露，故容易保证产品的使用安全。

Claims (10)

1.一种电源电路装置，其包括MOSFET、密封该MOSFET的封装和从该封装主体的一个侧壁引出的多个引脚，并将所述MOSFET的漏极端子连接在该多个引脚中中央的引脚上，
其特征在于：在所要求的沿表面距离设置间隔，该间隔是使成为高电位的所述中央的引脚的根部与相邻的其它引脚的根部的间隔，并且作得比所述其它引脚彼此的根部的间隔大。
2.如权利要求1所述的电源电路装置，其特征在于，所述封装是整体模制结构。
3.如权利要求1所述的电源电路装置，其特征在于，IC安装在所述MOSFET上。
4.如权利要求1所述的电源电路装置，其特征在于，所述相邻的其它的引脚在下段、所述中央的引脚在上段和不相邻的其它的引脚在上段与下段之间的中段进行弯折。
5.如权利要求4所述的电源电路装置，其特征在于，所述封装是整体模制结构。
6.如权利要求4所述的电源电路装置，其特征在于，IC安装在所述MOSFET上。
7.一种电源电路装置，其包括MOSFET、密封该MOSFET的封装和从该封装主体的一个侧壁引出的五根引脚，将所述MOSFET的漏极端子连接在位于中央的第三引脚上，
其特征在于：使成为高电位的第三引脚的根部和相邻的其它引脚的根部的间隔比所述其它引脚彼此的根部的间隔大，所述第三引脚和相邻的低电位的第二及第四引脚的根部设置为所要求的的沿表面距离。
8.如权利要求7所述的电源电路装置，其特征在于，使所述第二和所述第四引脚在下段、所述第三引脚在上段、第一和第五引脚在上段与下段之间的中段进行弯折。
9.如权利要求7所述的电源电路装置，其特征在于，所述封装是整体模制结构。
10.如权利要求7所述的电源电路装置，其特征在于，IC安装在所述MOSFET上。
CNB028016270A 2001-05-18 2002-05-17 电源电路装置 Expired - Fee Related CN1312767C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001149636 2001-05-18
JP149636/2001 2001-05-18
JP149636/01 2001-05-18

Publications (2)

Publication Number Publication Date
CN1462476A CN1462476A (zh) 2003-12-17
CN1312767C true CN1312767C (zh) 2007-04-25

Family

ID=18994775

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028016270A Expired - Fee Related CN1312767C (zh) 2001-05-18 2002-05-17 电源电路装置

Country Status (5)

Country Link
US (1) US6861732B2 (zh)
JP (1) JP4118143B2 (zh)
KR (1) KR100612165B1 (zh)
CN (1) CN1312767C (zh)
WO (1) WO2002095824A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6842877B2 (en) * 1998-12-18 2005-01-11 Tangis Corporation Contextual responses based on automated learning techniques
US7814155B2 (en) * 2004-03-31 2010-10-12 Google Inc. Email conversation management system
US7493303B2 (en) * 2004-08-04 2009-02-17 International Business Machines Corporation Method for remotely searching a local user index
US7496563B2 (en) * 2004-08-04 2009-02-24 International Business Machines Corporation Method for locating documents a user has previously accessed
CN100464405C (zh) * 2005-10-31 2009-02-25 台达电子工业股份有限公司 电源模块的封装方法及其结构
US8253225B2 (en) * 2008-02-22 2012-08-28 Infineon Technologies Ag Device including semiconductor chip and leads coupled to the semiconductor chip and manufacturing thereof
WO2012073306A1 (ja) * 2010-11-29 2012-06-07 トヨタ自動車株式会社 パワーモジュール
US9035437B2 (en) * 2013-03-12 2015-05-19 Infineon Technologies Austria Ag Packaged device comprising non-integer lead pitches and method of manufacturing the same
TWI536524B (zh) * 2014-01-10 2016-06-01 萬國半導體股份有限公司 抑制爬電現象的半導體裝置及製備方法
DE102017209904B4 (de) * 2017-06-13 2023-09-21 Infineon Technologies Ag Elektronisches Bauelement, Leadframe für ein elektronisches Bauelement und Verfahren zur Herstellung eines elektronischen Bauelements und eines Leadframes
CN112086409B (zh) * 2020-09-02 2022-07-22 东莞市柏尔电子科技有限公司 一种塑封型三极管及制作工艺

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4947234A (en) * 1986-09-23 1990-08-07 Siemens Aktiengesellschaft Semiconductor component with power MOSFET and control circuit
US5031024A (en) * 1989-09-05 1991-07-09 Kabushiki Kaisha Toshiba Resin sealing type semiconductor device having outer leads designed for multi-functions
US5814884A (en) * 1996-10-24 1998-09-29 International Rectifier Corporation Commonly housed diverse semiconductor die

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6459147B1 (en) * 2000-03-27 2002-10-01 Amkor Technology, Inc. Attaching semiconductor dies to substrates with conductive straps
JP3602453B2 (ja) * 2000-08-31 2004-12-15 Ｎｅｃエレクトロニクス株式会社 半導体装置
TW529145B (en) * 2001-11-19 2003-04-21 Chino Excel Technology Corp Semiconductor device free of bonding wire and method for encapsulating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4947234A (en) * 1986-09-23 1990-08-07 Siemens Aktiengesellschaft Semiconductor component with power MOSFET and control circuit
US5031024A (en) * 1989-09-05 1991-07-09 Kabushiki Kaisha Toshiba Resin sealing type semiconductor device having outer leads designed for multi-functions
US5814884A (en) * 1996-10-24 1998-09-29 International Rectifier Corporation Commonly housed diverse semiconductor die
US5814884C1 (en) * 1996-10-24 2002-01-29 Int Rectifier Corp Commonly housed diverse semiconductor die

Also Published As

Publication number Publication date
JP4118143B2 (ja) 2008-07-16
JPWO2002095824A1 (ja) 2004-09-09
KR100612165B1 (ko) 2006-08-14
CN1462476A (zh) 2003-12-17
KR20030060870A (ko) 2003-07-16
WO2002095824A1 (fr) 2002-11-28
US20040026770A1 (en) 2004-02-12
US6861732B2 (en) 2005-03-01

Similar Documents

Publication Publication Date Title
CN101626001B (zh) 半导体装置及其制造方法
US6700194B2 (en) Semiconductor device
CN103370788B (zh) 半导体装置及其制造方法
US8283763B2 (en) Power semiconductor module and fabrication method thereof
CN1312767C (zh) 电源电路装置
KR101443972B1 (ko) 일체형 전력 반도체 모듈
CN101556946B (zh) 形成半导体封装件的方法及其结构
CN102194806A (zh) 堆栈式双晶片封装及其制备方法
JP6816825B2 (ja) 半導体装置、電力変換装置および半導体装置の製造方法
CN109599372B (zh) 半导体装置
KR920001689A (ko) 반도체장치 및 그 제조방법
CN103681575A (zh) 无线多芯片模块以及用于制备集成电路以供倒装芯片组装在多芯片模块中的方法
CN108155168B (zh) 电子器件
CN115939119B (zh) 功率模块和电子设备
CN100583421C (zh) 用于垂直安装的半导体封装结构及方法
CN104508845A (zh) 经强化的led封装及为此的方法
CN105374759A (zh) 集成电路封装用陶瓷四边无引线扁平封装外壳
US4893169A (en) Lead frame and a process for the production of a lead with this lead frame
CN108878377B (zh) 功率模块及其制作方法以及空调器
JP4651652B2 (ja) 電源回路装置
CN110323142A (zh) 功率模块及其制造方法
US10971434B2 (en) Lead frame package having conductive surface with integral lead finger
CN110998832B (zh) 半导体装置以及半导体模块
CN214378418U (zh) 一种芯片的封装结构
US11626353B2 (en) Method of manufacturing semiconductor device and semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20161010

Address after: Arizona, USA

Patentee after: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Address before: Fribourg

Patentee before: Semiconductor component industry LLC

Effective date of registration: 20161010

Address after: Fribourg

Patentee after: Semiconductor component industry LLC

Address before: Osaka Japan

Patentee before: Sanyo Electric Co.,Ltd.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070425

Termination date: 20210517

CF01 Termination of patent right due to non-payment of annual fee