CN1298053C - 集成电路 - Google Patents

集成电路 Download PDF

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Publication number
CN1298053C
CN1298053C CNB028024761A CN02802476A CN1298053C CN 1298053 C CN1298053 C CN 1298053C CN B028024761 A CNB028024761 A CN B028024761A CN 02802476 A CN02802476 A CN 02802476A CN 1298053 C CN1298053 C CN 1298053C
Authority
CN
China
Prior art keywords
circuit
semiconductor chip
wire
decoding
decoding circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB028024761A
Other languages
English (en)
Chinese (zh)
Other versions
CN1465102A (zh
Inventor
乌谷宗宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niigato Precision Co., Ltd.
Ricoh Co Ltd
Original Assignee
NIIGATO PRECISION CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIIGATO PRECISION CO Ltd filed Critical NIIGATO PRECISION CO Ltd
Publication of CN1465102A publication Critical patent/CN1465102A/zh
Application granted granted Critical
Publication of CN1298053C publication Critical patent/CN1298053C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CNB028024761A 2001-07-23 2002-07-10 集成电路 Expired - Fee Related CN1298053C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001220875A JP2003037170A (ja) 2001-07-23 2001-07-23 集積回路
JP220875/2001 2001-07-23
JP220875/01 2001-07-23

Publications (2)

Publication Number Publication Date
CN1465102A CN1465102A (zh) 2003-12-31
CN1298053C true CN1298053C (zh) 2007-01-31

Family

ID=19054632

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028024761A Expired - Fee Related CN1298053C (zh) 2001-07-23 2002-07-10 集成电路

Country Status (5)

Country Link
JP (1) JP2003037170A (ko)
KR (1) KR100849963B1 (ko)
CN (1) CN1298053C (ko)
TW (1) TWI270196B (ko)
WO (1) WO2003010818A1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100040580A (ko) 2008-10-10 2010-04-20 성균관대학교산학협력단 적층 메모리 소자

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761694A (en) * 1995-11-30 1998-06-02 Cirrus Logic, Inc. Multi-bank memory system and method having addresses switched between the row and column decoders in different banks
US5941980A (en) * 1996-08-05 1999-08-24 Industrial Technology Research Institute Apparatus and method for parallel decoding of variable-length instructions in a superscalar pipelined data processing system
JP2000133000A (ja) * 1998-10-28 2000-05-12 Toshiba Corp メモリ混載ロジックlsi
JP2000251496A (ja) * 1999-02-23 2000-09-14 Hitachi Ltd 半導体集積回路装置
EP1059584A2 (en) * 1999-06-02 2000-12-13 Nec Corporation Method and apparatus for generating test pattern for circuit blocks
JP2001077311A (ja) * 1999-09-06 2001-03-23 Sharp Corp 半導体装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02207567A (ja) * 1989-02-07 1990-08-17 Hitachi Ltd 半導体集積回路及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761694A (en) * 1995-11-30 1998-06-02 Cirrus Logic, Inc. Multi-bank memory system and method having addresses switched between the row and column decoders in different banks
US5941980A (en) * 1996-08-05 1999-08-24 Industrial Technology Research Institute Apparatus and method for parallel decoding of variable-length instructions in a superscalar pipelined data processing system
JP2000133000A (ja) * 1998-10-28 2000-05-12 Toshiba Corp メモリ混載ロジックlsi
JP2000251496A (ja) * 1999-02-23 2000-09-14 Hitachi Ltd 半導体集積回路装置
EP1059584A2 (en) * 1999-06-02 2000-12-13 Nec Corporation Method and apparatus for generating test pattern for circuit blocks
JP2001077311A (ja) * 1999-09-06 2001-03-23 Sharp Corp 半導体装置

Also Published As

Publication number Publication date
CN1465102A (zh) 2003-12-31
JP2003037170A (ja) 2003-02-07
KR20040030412A (ko) 2004-04-09
TWI270196B (en) 2007-01-01
KR100849963B1 (ko) 2008-08-01
WO2003010818A1 (en) 2003-02-06

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Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: NIIGATA SEIMITSU CO., LTD.; RICOH CO., LTD.

Free format text: FORMER OWNER: NIIGATA SEIMITSU CO., LTD.

Effective date: 20070928

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20070928

Address after: Japan's Niigata Prefecture

Co-patentee after: Ricoh Co., Ltd.

Patentee after: Niigato Precision Co., Ltd.

Address before: Japan's Niigata Prefecture

Patentee before: Niigato Precision Co., Ltd.

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070131

Termination date: 20100710