CN1263618A - 使用非易失性元件的可编程逻辑器件中的配置控制 - Google Patents

使用非易失性元件的可编程逻辑器件中的配置控制 Download PDF

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CN1263618A
CN1263618A CN99800586A CN99800586A CN1263618A CN 1263618 A CN1263618 A CN 1263618A CN 99800586 A CN99800586 A CN 99800586A CN 99800586 A CN99800586 A CN 99800586A CN 1263618 A CN1263618 A CN 1263618A
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register
volatile elements
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pld
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CN1154940C (zh
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S·拉马默茜
J·费伊
W·J·塞琪
N·伯杰
G·S·贡韦尔
E·J·丹
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Atmel Corp
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516Test of programmable logic devices [PLDs]

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Abstract

使用一种边界扫描测试电路(JTAG)接口为一配置寄存器(150)内的一组配置锁存器(151)提供数据。配置寄存器(150)包含在作为测试数据寄存器(TDR)(180)的JTAG结构内。配置寄存器(150)内的每个配置位由配置锁存器(151)构成,且每个配置锁存器(151)具有在输出逻辑宏单元内用作配置控制信号(160)的输出。由一组串联的配置位非易失性元件的侦测锁存器(120)或由用于配置、建立原型和测试的JTAG测试数据输入(TDI)数据引脚(101)来选择性地提供配置寄存器的输入信号(149)。

Description

使用非易失性元件的可编程逻辑器件中的配置控制
技术领域
本发明涉及半导体集成电路,尤其涉及可编程逻辑器件的配置。
背景技术
使用非易失性元件的可编程逻辑器件(PLD)是众所周知的。在PLD的早期发展中,使用基本上由形成行列的导体格栅(每个交叉点处有可熔链接)构成的阵列。把数据输出编程为该器件的地址信号所需的组合功能。后来,设计了专用于产生积之和(SOP)逻辑的集成电路(IC)。非易失性存储元件以形成逻辑AND门(积项)的方式在IC内连接。通过把两个或多个AND门的输出作为输入连接到逻辑OR门,OR门的输出将构成一SOP逻辑功能。选择此SOP形式是因为,在本领域内众所周知可把任何复杂的组合功能简化到SOP形式。因此,如果在IC内可获得足够的这类AND和OR门,则可在此IC内实现任何这样的组合功能。
PLD的进一步发展包括添加配置位(configuration bit)(CB)来允许SOP功能的输出格式的可编程改变。这导致了输出逻辑宏单元(output logicmacrocell)(OLMC)的发展。OLMC由可被配置用于组合输出或输入或用于寄存输出的可编程逻辑电路制成。在寄存模式中,输出来自触发器。通过编程自动地设定OLMC组合模式配置。图4示出具有两个配置位的典型OLMC 500的方框图。第一配置位501确定OLMC是在寄存模式(通过触发器504)还是在组合模式下进行操作。第二配置位502确定输出是“active-LOW”还是“active-HIGH”。4选1多路复用器(multiplexer)505根据这两个配置位501和502的状态把其四个输入线之一连接到输出三态(tristate)缓冲器507。2选1多路复用器506把三态缓冲器507的输出508或触发器504的Q输出中的任一个通过缓冲器509连回到可编程阵列。在典型的PLD中,使用几个OLMC,每个SOP项用一个,所有的OLMC寄存器具有公共的时钟引脚(pin)。更多基于PLD的新产品已在每个OLMC中包含更多的配置位,以增强器件的灵活性而不增加积项的数目。除了输出极性和寄存对组合输出信号选择以外,这些CB进行的功能诸如:传送各个积项用于除了作为OR门输入外的使用、在可供选择的(alternative)时钟之间进行选择、设定和预设器件寄存器的源以及在可供选择的输出使能功能之间进行选择。
每个OLMC包括许多CB导致OLMC可以许多方式中的任一种方式来配置。(对于N个二进制级CB,高达2N的这种配置是可能的)。大量配置的难点之一是,IC制造商必须把每个OLMC编程到每个可能的配置(可能有2N个组合),并对每个配置进行测试以保证所有的配置进行正确地操作。虽然可通过对分别控制独立功能的CB进行编程和测试而稍稍减少测试量,对从非易失性元件构成的CB进行测试是非常昂贵的。例如,一些这样的非易失性元件的擦除和重新编程需要100毫秒或更长的时间。非易失性元件的编程所需的时间甚至比擦除长。由于测试高密度、高性能的PLD很费时,所以对器件的擦除和重新编程所需的任何附加的时间更增加了生产该器件的成本。因此,能把制造PLD的测试阶段中对CB进行擦除和重新编程所需的时间量减到最少是有益的。
在图5中示出可用来提供较快的CB重新编程装置的一个方法。在此方法中,把一双稳态配置锁存器(configuration latch)(CL)603包含在用于每个配置位(CB)604的IC中。然后,宏单元使用CL 603的输出来测试配置控制信号605。在IC最初上电时,使侦测使能信号(Sense Enable Signal)601脉动,使得CL 603的状态可由CB 604的非易失性元件来设定。接着,可通过升高复盖(override)使能信号(Override Enable Signal)602而由另一数据输入信号来设定CL 603,从而复盖先前存储在锁存器中的非易失性数据。可在几纳秒或更短的时间内设定简单的双稳态锁存器,因而这明显地减少了改变CB的逻辑状态所需的时间。通过使每个CB包括一个CL,测试CB操作所需的时间不再受到CB重新编程的限制,而要受到每个配置需要确立多少测试矢量及可以多快的速度应用这些矢量的限制。由于先进的测试设备可以极快地应用测试矢量,所以可明显地减少整个配置位测试的时间和成本。
然而,先前设计的这种CL的测试能力需要使用许多外部器件引脚来为锁存器提供输入数据。大量的引脚连接使测试硬件变得复杂,从而增加了这些硬件的开发和维修的时间和成本。已开发了许多旨在其它IC测试需求的方法,其中的一些方法使用最少量的外部器件引脚。在IEEE规范1149.1(通常叫做联合测试行动组织(JTAG)规范)中描述了一种这样的方法。图6示出实现JTAG测试所需的外部引脚连接和内部电路的方框图。此方法揭示了使用标准化4引脚(或5引脚)外部接口,利用指令寄存器(IR)701、测试接入端口(TAP)704、包含TAP状态机的TAP控制器703和测试数据寄存器(TDR)702来实现测试功能。公知的4(或5)引脚外部接口为测试接入端口(TAP)704。除了需要少量外部引脚以外,此JTAG方法还具有可用于大量和各种器件测试和操作功能的优点。由于此方法是标准化的,所以支持使用此方法的新测试特点的测试系统硬件和软件的开发相对简单,因而对器件制造商和器件用户来说都是便宜的。以下将提供有关实现JTAG方法的更多细节。
发明内容
因此,本发明的目的是设计一种系统,可由该系统利用可使配置位非易失性元件被复盖的锁存器对包含实现积项用的非易失性元件的PLD进行重新配置,器件接口使用最少数目的外部器件引脚。
在本发明中,使用串行数据流为一组配置锁存器(CL)提供数据。在较佳实施例中,使用JTAG接口为配置寄存器(CR)提供数据。CR包含在作为测试数据寄存器(TDR)的JTAG结构中。CR内的每个配置位(CB)由一CL构成,每个CL具有用作宏单元内的配置控制信号的输出。由一组串联的CB非易失性元件的侦测锁存器或由用于重新配置和测试的JTAG测试数据输入(TDI)数据引脚来选择性地提供CR的输入信号。
本发明预期的其它实施例包括:从各个CB非易失性元件到配置寄存器位的并行数据连接,在逻辑上组合在一起来产生配置控制信号的多重并行CR、CL和非易失性元件输出,以及增加一加到CB或CL的控制信号,从而在对CB编程或擦除或者在把数据输入到配置锁存器时把控制信号保持于固定的状态。此外,可使用本发明的系统来控制可编程位,这些可编程位不同于位于只包含实现积项用的非易失性元件的PLD内的宏单元内的那些可编程位(例如,保密位(security bit)、引出脚控制选项、全局逻辑配置控制位、速度/功率选项)。
在以下描述中详细地描述本发明的各实施例。
附图概述
图1示出在标准JTAG测试结构中实现的本发明的较佳实施例的方框图/示意图。
图2示出本发明的另一个实施例的方框图/示意图,只示出JTAG测试结构的配置寄存器部分。
图3示出在逻辑上组合本发明的框架内的配置位和配置锁存器输出信号的方框图/示意图。
图4示出已有技术中公知的典型输出逻辑宏单元的方框图/示意图。
图5示出已有技术中公知的至配置位的配置锁存器连接的方框图/示意图。
图6示出已有技术中公知的IEEE1149.1-1990中所定义的JTAG测试设置的方框图/示意图。
本发明的较佳实施方式
参考图1,使用通常公知边界扫描测试电路140的JTAG接口为配置寄存器(CR)150提供数据。
如上所述,边界扫描测试电路140的基本体系结构由指令寄存器185、测试接入端口(TAP)控制器194、测试数据寄存器180和测试接入端口构成。测试接入端口由IC封装上的四个或五个引脚构成,这些引脚专用于边界扫描且不被任何其它功能所共享。用简单的协议使用这些引脚而与单片边界扫描逻辑进行通信。这些引脚中的两个即测试时钟(TCK)192和测试模式选择(TMS)191来驱动该协议。(如果使用任选的测试复位(TRST)193,则可以第三引脚来驱动该协议。)测试接入端口的其余两个引脚用于以串行方式把数据移入或移出IC,这些两个引脚叫做测试数据输入(TDI)101和测试数据输出(TDO)190。TAP控制器194是位于IC小片上的具有16状态的简单有限状态机。TAP控制器194确认通信协议并产生边界扫描逻辑的其余部分所使用的内部控制信号。TAP控制器194由TCK 192和TMS 191(任选的TRST 193)测试引脚的信号来驱动。
指令寄存器185由TAP控制器194来控制且可置于加载(和卸载)串行移位数据的TDI 101和TDO 190之间。指令寄存器185用于设定一个或多个测试数据寄存器180的操作模式。(在以上所引用的IEEE标准1149.1中描述了用于增加用户定义指令的指令模式和规则)。每个指令寄存器单元包括一移位寄存器触发器和一并行输出锁存器。移位寄存器保存通过指令寄存器移动的指令位。锁存器保存当前指令。指令寄存器的最小尺寸为两个单元。寄存器的尺寸决定了可使用的指令码的尺寸,这是因为代码尺寸必须与寄存器的长度匹配。
测试数据寄存器180置于TDI引脚101和TDO引脚190之间。在JTAG元件上总需要有两个测试数据寄存器,旁路(bypass)寄存器和边界寄存器。使用边界寄存器来控制和观察IC的输入和输出引脚上的动作。旁路寄存器把扫描链缩短到单个单元,它在测试板上的其它边界扫描引脚时有用。附加的测试数据寄存器是任选的。测试数据由测试数据寄存器180移至多路复用器187,然后由输出缓冲器188移至TDO引脚190。对于全部细节,可参考以上所引用的IEEE标准1149.1,IEEE标准测试接入端口和边界扫描体系结构。
在本发明中,CR 150包含在作为测试数据寄存器180的JTAG结构内。CR 150中的每一位由配置锁存器(CL)151构成。每个CL 151具有用作宏单元内的配置控制信号160的输出。由一组串联的配置位非易失性元件的侦测锁存器120或由用于重新配置和测试的JTAG测试数据输入(TDI)数据引脚101来选择性地提供CR 150的输入数据信号149。
由一初始上电信号111来启动本系统,此初始上电信号111被通过OR门110,以产生非易失性元件的侦测信号(NV侦测信号)109。在初始上电时,非易失性元件的状态以并行方式侦测并存储在配置位侦测锁存器(CBSL)120(示为一系列独立的CB侦测锁存器121并与配置时钟(CC)153同步)中。把NV侦测信号109推进(process)到FET 107的栅极(它在FET 107上切换),继而通过FET 107把侦测锁存器输出信号131推进到配置寄存器输入149。配置时钟(CC)153被触发(toggle)K个时钟循环,这里K是以位为单位的配置寄存器的长度。这样,在上电时把存储在配置位侦测锁存器120中的非易失性元件的数据存入配置寄存器150。由于锁存器的速度此过程非常快。
在上电阶段后,可通过启动FET 105的栅极的复盖使能信号103来开始测试。这使得把JTAG TDI数据输入引脚101用作CR数据输入149。(注意,应在上电阶段结束后使用复盖使能信号103,从而避免在把复盖使能信号103发送到FET 105的同时把上电信号发送到FET 107的情况,这种情况将引起信号冲突。)然后,可使用JTAG TDI数据输入引脚101把测试配置位推进到配置寄存器150中用以实行测试。由于使用标准JTAG测试规范,所以可使用标准工业测试方法。(此外,对于如何实现测试的更多细节,可参考IEEE标准1149.1,IEEE标准测试接入端口和边界扫描体系结构。)
在测试结束后,可使用恢复信号113来开始上电期间进行的相同配置安装序列。这提供了把配置锁存器的状态设定为存储在配置位的非易失性元件中的那些状态而不必改变电源电平的方法。
本发明的一个优点是可以串行方式把不同的配置装入输出宏单元而不必对非易失性元件进行重新编程和擦除。因而,此过程比非易失性元件必须被擦除或重新编程的过程快得多。必须对非易失性元件进行擦除和重新编程花费了相当多的测试时间,因为在擦除和重新编程后,必须重新安装配置位来检查宏单元的功能。此外,本系统还避免了与非易失性元件的多重擦除有关的问题,诸如因介电材料的击穿而引起的过度损耗(excessive wear)。还可利用此过程来建立集成电路芯片的原型。
本发明的另一个实施例如图2所示。在该实施例中,由于各个配置位非易失性元件(CB)221至各配置寄存器位的并行数据连接使得不必使用配置位锁存器。图2示出相应于配置寄存器220的电路部分。假设配置寄存器220是JTAG测试结构中所定义(并如图1所述)的测试数据寄存器。
在通过上电信号211启动时,把NV侦测信号209发送到FET 205的栅极,以把配置位非易失性元件(CB)221安装到配置锁存器(CL)230。CL 230的输出被用作宏单元内的配置控制信号260。接着可用复盖使能信号203来启动测试,并可通过TDI测试引脚201来安装测试配置位。由电路230的配置锁存器部分依据JTAG规范来测试测试配置位,并通向TDO(测试数据输出)290的连接来退出配置寄存器220。在测试后,可用恢复信号213来重新加载配置锁存器230。如上所述,本实施例不需要配置位侦测锁存器。然而,需要使配置位221实际上位于配置锁存器230附近,以避免必须在很长的距离上来传送每个CB输出。
可把其它电路加到上述本发明的两个实施例来进行附加的操作。例如,如图3所示,配置锁存器330和配置位非易失性元件321(使用AND门380和OR门390)可在逻辑上组合在配置寄存器320内,以对宏单元产生配置控制信号360。
此外,除了控制宏单元内的位以外,还可把本发明的控制可编程位的方法用于其它目的。这些其它目的可包括控制引出脚控制选项、保密位、全局逻辑配置控制位或速度/功率选项。
此外,可把一控制信号加到配置位或加到配置锁存器,以在把数据输入配置锁存器期间或在对配置位进行编程或擦除时把配置控制信号保持在固定的状态。
最后,预期可把多个配置寄存器并联在上述结构中,以同时处理多个配置位。

Claims (7)

1.一种用于控制与可编程逻辑器件中的非易失性元件相连的寄存器的系统,其特征在于包括:
包括许多外部器件引脚和被定义为配置寄存器的至少一个测试数据寄存器的边界扫描测试电路,这些外部器件引脚之一被定义为测试数据输入引脚;
一组串联的配置位非易失性元件侦测锁存器(CBSL),CBSL存储非易失性元件的一组数据;
用于在施加第一信号时把来自非易失性元件的这组数据推进到配置寄存器的装置;以及
用于在施加第二信号时把来自测试数据输入引脚的一组测试数据信号推进到配置寄存器的装置。
2.如权利要求1所述的用于控制与可编程逻辑器件中的非易失性元件相连的寄存器的系统,其特征在于配置寄存器包括一系列串联的配置锁存器和一配置时钟,配置寄存器产生一输出信号。
3.如权利要求2所述的用于控制与可编程逻辑器件中的非易失性元件相连的寄存器的系统,其特征在于在输出逻辑宏单元内使用所述输出信号。
4.如权利要求3所述的用于控制与可编程逻辑器件中的非易失性元件相连的寄存器的系统,其特征在于测试数据输入引脚通过第一晶体管耦合到配置寄存器,CBSL通过第二晶体管耦合到配置寄存器。
5.如权利要求2所述的用于控制与可编程逻辑器件中的非易失性元件相连的寄存器的系统,其特征在于把一控制信号加到配置锁存器,从而输出信号保持在固定状态。
6.如权利要求1所述的用于控制与可编程逻辑器件中的非易失性元件相连的寄存器的系统,其特征在于外部器件引脚的数目为五个或更少。
7.如权利要求2所述的用于控制与可编程逻辑器件中的非易失性元件相连的寄存器的系统,其特征在于用于推进非易失性元件的这组数据的装置包括把配置时钟触发为许多循环,循环数目等于配置寄存器的位的长度。
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