CN1237856C - 多层电路的制造方法 - Google Patents

多层电路的制造方法 Download PDF

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CN1237856C
CN1237856C CNB998109975A CN99810997A CN1237856C CN 1237856 C CN1237856 C CN 1237856C CN B998109975 A CNB998109975 A CN B998109975A CN 99810997 A CN99810997 A CN 99810997A CN 1237856 C CN1237856 C CN 1237856C
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circuit board
sides
dielectric
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CN1318273A (zh
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K·梅尔
N·明策尔
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VAN DICO AG
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

本发明涉及一种用于在层压板芯体两面上制备有不同数量导电面的顺序结构的印刷电路板的方法，其特征在于下列工序：(A)用一种含有光敏聚合物或热可硬化聚合物的电介质涂复只有一面具有导电结构的电路板的两面；(B)通过含光敏聚合物的电介质的光照和接着用一种溶剂显影，或者通过激光打孔在含热硬化聚合物的电介质上形成接触孔(通孔)使有导电结构面的接触孔(通孔)结构化；(C)在所得板的两面上沉积一层铜；(D)如果还要实现另一非对称结构，则在正面形成电路结构，在背面完全蚀刻掉，或者在印刷电路板的两面再形成不对称或对称的结构，这些均可藉助蚀刻剂选择蚀刻实现；(E)如果还需实现另一非对称结构，则重复进行工序(A)至(D)，或者如果还要进行对称结构，则在(A)和接着的电介质层的两面结构化(F)之后完成(C)和(D)。

Description

多层电路板的制造方法
技术领域
本发明涉及一种制造多层印刷电路板的方法。
背景技术
布线密度较高的多层电路板最近主要用所谓的SBU-方法(“Sequential buied-up”(顺序构造法))制造。各导电线路之间的电联结(“贯通接触”)通常籍助钻孔制造，这些孔贯穿导电线路面并进行金属化。但机械钻的孔比较大(最小直径约为0.3mm)，因而限制了印刷电路板的布线密度。
DE-A 38 40 207报导了一种制造多层印刷电路板的方法，其中直径较小的贯通式接触是籍助光刻材料用光化学方法制造。
US专利5,451,271推介SBU-方法，其中先将光刻胶涂覆在各导电线路之间的贯通接触上，然后通过机械钻孔的和金属化的通孔化最外面的布线层形成导电联结。在这样形成的印刷电路板中两个外布线层作为供电导线，而信号布线导线则位于层压板的内部。
当然，US专利5,451,721中所描述的用于制备在层压板芯体的两面有不等数量的布线层的印刷电路板的方法只能有条件地适用，因为在不对称结构的实施方案中，特别是在采用厚度小于0.8mm的层压板芯体的情况下，须考虑到大的弯变形，其原因是只有一面涂覆有介电质的层会发生聚合收缩。此外，背面铜涂层的一次或多次镀铜会使印刷电路板两面的铜厚度不同。通常接着进行的双面同时蚀刻会使上面的薄铜层产生过度的蚀刻。
发明内容
本发明的目的在于提供一种用于制备顺序组构的印刷电路板的方法，该印刷电路板在其层压板芯体两面有不同数量的导电面，该方法不具有上面所述的缺点。
曾经发现，如果从层压板芯体出发，该芯板只在一面具有导体结构，在其两面涂覆电介质，但只将一面结构化，而将另一面完全硬化，这样可得到满意的结果。
因此，本发明的目的是提供一种用于制备顺序组构的印刷电路板的方法，该电路板在其层压板芯体两面有不同数量的导电面，其特征面具有导电结构的电路板的两面；
(B)通过含光敏聚合物的电介质的光照和接着用一种溶剂显影，或者通过激光打孔在含热硬化聚合物的电介质上形成接触孔(通孔)使有导电结构面的接触孔(通孔)结构化；
(C)在所得板的两面上沉积一层铜；
(D)如果还要实现另一非对称结构，则在正面形成电路结构，在背面完全蚀刻掉，或者在印刷电路板的两面不形成另外的结构或形成对称的结构，这些均可藉助抗蚀剂选择蚀刻实现；
(E)如果还需实现另一非对称结构，则重复进行工序(A)至(D)，或者如果还要进行对称结构，则在(A)和接着的电介质层的两面结构化(F)之后完成(C)和(D)。
附图说明
本发明将通过附图作进一步阐述。
图1表示绝缘的基片(1)，该基片宜为一种以玻璃纤维增强的环氧树脂，该基片只有一面具有导电结构(2)。
图2表示在工序(A)中，在这种单面印刷电路板的两面涂覆一种介电的硬化材料(3和4)后的结构式意图。
图3表示在工序(B)中籍助成图法在带电路结构的一面的拟作为贯通接触孔的位置(5)处去除电介质后的结构式意图。
图4表示印刷电路板通过已知的方法(例如，用KMnO4水溶液)蚀刻使其两面粗糙化，然后整个表面进行化学镀铜后的结构式意图。
图5表示在工序(D)中，两面上的铜层经选择蚀刻结构化后的结构式意图。
具体实施方式
在工序(A)中，在这种单面印刷电路板的两面涂覆一种介电的硬化材料(3和4，图2)。
涂覆按通常的方法进行，例如旋涂、浸涂、刮涂、帘注、丝网印刷、刷涂、喷涂、静电喷涂或反辊涂覆。
印刷电路板宜籍助帘注或丝网印刷涂覆。
介电材料可以溶液或干膜的形式涂覆。在采用溶液的情况下，溶剂接着用干燥去除。电介质的层厚应大于印刷电路板的铜导线的厚度。干燥层的厚度宜为20-150μm，优选30-80μm。
介电材料可为一种光敏聚合物(光致过程)，亦可采用一种热固聚合物(激光致过程)。在感光成孔(Photovia)法中可采用正光刻胶亦可采用负光刻胶。适宜的光刻胶材料是专业技术人员熟知的。作为例子，可举EP-A 689098所述的正光刻胶以及EP-A 605361报导的负光刻胶。
工序(A)中采用的印刷电路板可以是普通的多层电路，其贯通接触孔还未钻成或者已钻好的贯通接触孔用树脂封住。
在工序(B)(图3)中籍助成图法在带电路结构的一面的拟作为贯通接触孔的位置(5)处去除电介质。
在感光成孔法中，光刻胶涂层通过相应于要涂覆的导电线路结构的掩模进行光照和显影。为了达到完全交联，建议在工序(B)之后接着进行后热固化。
在采用负作用的光致电介质的情况下，宜在后热固化之前或之后补充进行双面的全面光照。
在整个印刷电路板的背面，未经结构化的介电材料在整个表面上完全硬化。在采用负光刻胶的情况下可通过整面光照存时还可后热硬化来进行。在正光刻胶的情况下，则印刷电路板背面不经预先的光照而进行整面热硬化。
如果不需要额外的导电面，而且在印刷电路板正面和背面之间无贯通接触点，则贯通接触点可在工艺工序(B)完成之后通过钻孔制成。
这样得到的印刷电路板通过已知的方法(例如，用KMnO4水溶液)蚀刻使其两面粗糙化，然后整个表面进行化学镀铜(图4)，即通过无电流电镀镀上薄铜层(6)。存时再进行干燥，以及铜层通过电流沉积强化。
在工序(D)中，两面上的铜层经选择蚀刻结构化(图5)，通常通过有抗蚀剂印刷电路板的双面涂层按图形进行光照、显影、去除游离的铜。这可在一种蚀刻过程(“板电镀过程”)或在电蚀过程(“图形电镀过程”)中实现。
如果需要额外的导电面，则可任意次重复工序(A)至(D)。

Claims (6)

1.一种用于在层压板芯体(1)两面上制备有不同数量导电面的顺序结构的印刷电路板的方法，该方法包括下列工序：
(A)用一种含有光敏聚合物或热可固化聚合物的电介质(3，4)涂覆只有一面具有导电结构(2)的电路板的两面，或者涂覆按照步骤(D)得到的电路板的两面，其中电介质的层厚必须大于印刷电路板的铜导线的厚度；
(B)通过含光敏聚合物的电介质(3)的曝光和接着用一种溶剂显影，或者通过激光打孔在含热固化聚合物的电介质(3)上形成接触孔，使被称为正面的有导电结构(2)的面上或者按照步骤(D)得到的电路板的面上的接触孔(5)结构化；
(C)在所得板的两面上沉积一层铜(6)；
(D)如果要实现另一非对称结构，则在正面形成电路结构，在另一被称为背面的面上将铜完全蚀刻掉；或者，如果不形成另外的结构或者形成另外的对称结构，则在印刷电路板的两面藉助抗蚀剂进行选择蚀刻；
(E)如果还需实现另一对称结构，则重复工序(A)至(D)，其中在工序(B)中，在两面上进行接触孔的结构化。
2.权利要求1的方法，其特征在于，在工序(A)中，印刷电路板用帘注或丝网印刷进行涂覆。
3.权利要求1的方法，其特征在于，在按照工序(B)的接触孔结构化之后进行后热固化使光敏聚合物完全交联。
4.权利要求3的方法，其特征在于，在采用负性光敏聚合物的情况下，在工序(B)的电介质曝光之后，在后热固化之前或之后进行双面的整面光照，使聚合物完全交联。
5.权利要求1的方法，其特征在于，在工序(C)中，先使板的表面粗糙化，再进行化学镀铜，然后进行电解镀铜。
6.权利要求1的方法，其特征在于，在工序(B)之后，再在印刷电路板上钻贯通孔。
CNB998109975A 1998-09-18 1999-09-09 多层电路的制造方法 Expired - Fee Related CN1237856C (zh)

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6869750B2 (en) * 1999-10-28 2005-03-22 Fujitsu Limited Structure and method for forming a multilayered structure
US6877653B2 (en) * 2002-02-27 2005-04-12 Advanced Semiconductor Engineering, Inc. Method of modifying tin to lead ratio in tin-lead bump
US7211289B2 (en) * 2003-12-18 2007-05-01 Endicott Interconnect Technologies, Inc. Method of making multilayered printed circuit board with filled conductive holes
US7293355B2 (en) * 2005-04-21 2007-11-13 Endicott Interconnect Technologies, Inc. Apparatus and method for making circuitized substrates in a continuous manner
US7827682B2 (en) 2005-04-21 2010-11-09 Endicott Interconnect Technologies, Inc. Apparatus for making circuitized substrates having photo-imageable dielectric layers in a continuous manner
US7627947B2 (en) * 2005-04-21 2009-12-08 Endicott Interconnect Technologies, Inc. Method for making a multilayered circuitized substrate
US7211470B2 (en) * 2005-09-01 2007-05-01 Endicott Interconnect Technologies, Inc. Method and apparatus for depositing conductive paste in circuitized substrate openings
US20110024898A1 (en) * 2009-07-31 2011-02-03 Ati Technologies Ulc Method of manufacturing substrates having asymmetric buildup layers
WO2011046769A1 (en) * 2009-10-14 2011-04-21 Lockheed Martin Corporation Protective circuit board cover
KR20110044369A (ko) * 2009-10-23 2011-04-29 삼성전기주식회사 트렌치기판 및 그 제조방법
US8947889B2 (en) 2010-10-14 2015-02-03 Lockheed Martin Corporation Conformal electromagnetic (EM) detector
CN102137551B (zh) * 2011-03-16 2012-07-25 蔡新民 一种高频四层电路板的制作方法
JP2014143221A (ja) * 2011-05-18 2014-08-07 Panasonic Corp 回路基板の製造方法、並びに、その製造方法で得られる回路基板

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63229897A (ja) * 1987-03-19 1988-09-26 古河電気工業株式会社 リジツド型多層プリント回路板の製造方法
DE3840207A1 (de) 1988-11-29 1990-05-31 Draegerwerk Ag Verfahren zur herstellung einer leiterplatte mit mehreren leiterbahnebenen und entsprechende multilayer-leiterplatte
JP2739726B2 (ja) 1990-09-27 1998-04-15 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 多層プリント回路板
US5532105A (en) * 1992-08-07 1996-07-02 Hitachi Chemical Company, Ltd. Photolithographically viahole-forming photosensitive element comprising two photosensitive layers for the fabrication process of multilayer wiring board
TW269017B (zh) 1992-12-21 1996-01-21 Ciba Geigy Ag
JP3624967B2 (ja) * 1995-06-01 2005-03-02 日立化成工業株式会社 多層プリント配線板の製造方法

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JP2002525882A (ja) 2002-08-13
ATE265131T1 (de) 2004-05-15
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EP1123644A1 (de) 2001-08-16
TW472515B (en) 2002-01-11
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CA2343173C (en) 2008-08-19
US6638690B1 (en) 2003-10-28
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