CN1228823C - 氧化硅薄膜的沉积 - Google Patents
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title claims abstract description 62
- 229910052814 silicon oxide Inorganic materials 0.000 title claims abstract description 38
- 230000008021 deposition Effects 0.000 title description 17
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 32
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- 229910052734 helium Inorganic materials 0.000 claims abstract description 27
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 26
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims abstract description 26
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000001301 oxygen Substances 0.000 claims abstract description 9
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- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- 239000004411 aluminium Substances 0.000 description 1
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- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
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- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
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Abstract
提供了一种用于集成电路制造中的氧化硅层的形成方法。氧化硅层通过使第一种气体混合物与第二种气体混合物反应形成。第一种气体混合物包含正硅酸四乙酯(TEOS)、氦气(He)和氮气(N2)。第二种气体混合物包含臭氧(O3)和任选的氧气(O2)。
Description
发明领域
本发明涉及氧化硅薄膜，它们在集成电路制造中的应用，以及形成氧化硅薄膜的方法。
背景技术
集成电路已经发展成可以在一个单一的芯片上包含上百万个元件(例如，晶体管、电容器和电阻器)的复杂器件。芯片设计的发展仍然不断要求更快的电路和更大的电路密度。对于更大电路密度的需要使得集成电路元件尺寸必须减小。
随着集成电路元件尺寸的减小(例如亚微米尺寸)，使用沟槽隔离法(trench isolation method)把半导体衬底的相邻有源半导体区域隔开。例如，浅沟槽隔离法需要在有源半导体区域之间形成沟槽区域。沟槽区域一般小于约2-3微米深并充满介电材料。
已经提出用氧化硅薄膜作为浅沟槽隔离方法中的介电材料，因为氧化硅是良好的绝缘体。氧化硅薄膜可以使用化学气相沉积(CVD)法形成。例如，二氧化硅可以通过使正硅酸四乙酯(TEOS)与臭氧(O3)反应形成。氦(He)或氮气(N2)一般作为TEOS的载气。
根据使用的TEOS载气的种类，可以使二氧化硅薄膜具有不同的性能(例如，湿腐蚀速度比(WERR)、沉积速度、收缩、沟槽间隙填充)。例如，在使用氦(He)作为TEOS的载气，形成具有低湿腐蚀速度比和低沉积速度的二氧化硅薄膜。然而，在使用氮气(N2)作为TEOS载气时，形成具有高湿腐蚀速度比和低沉积速度的二氧化硅薄膜。
因此，在本领域，对形成具有低温腐蚀速度比和高沉积速度的氧化硅薄膜的方法仍然存在需求。
发明内容
提供了一种形成在集成电路制造中使用的氧化硅层。该氧化硅层通过使第一种气体混合物与第二种气体混合物反应形成。第一种气体混合物包含正硅酸四乙酯(TEOS)、氦(He)和氮气(N2)。第二种气体混合物包含臭氧(O3)和任选的氧气(O2)。在第一种气体混合物中的氦(He)与氮气(N2)优选的是具有约1∶1-1∶3的氦∶氮气流量比。这种氦∶氮气流量比形成沉积速度增大以及湿腐蚀速度改善的氧化硅层，而不会影响其沟槽填充能力。
这种氧化硅层适合于集成电路制备过程。在一种集成电路制备方法中，氧化硅层被用作浅沟槽隔离的绝缘材料。对于这种实施方案，优选的工艺顺序包括提供其上在有源半导体区域之间形成沟槽区域的衬底。然后，把沟槽区域用通过使第一种气体混合物与第二种气体混合物反应形成的氧化硅层填充，第一种气体混合物包含正硅酸四乙酯(TEOS)、氦(He)和氮气(N2)，第二种气体混合物包含臭氧(O3)和任选的氧气(O2)。
附图简述
考虑结合附图的下列描述，可以更容易地理解本发明的内容，其中：
图1表示可以用于实施本发明的设备的示意说明；
图2a表示氧化硅沉积速度作为氮气流量和氦气流量的函数的三维图；
图2b表示氧化硅湿腐蚀速度比(WERR)作为氮气流量和氦气流量的函数的三维图；和
图3a-3c表示在引入氧化硅层作为浅沟槽隔离的集成电路制造的不同阶段的衬底的截面图。
发明详述
本发明是一种形成用于集成电路制造的氧化硅层的方法。氧化硅层通过使第一种气体混合物与第二种气体混合物反应而形成，其中，第一种气体混合物包含正硅酸四乙酯(TEOS)、氦(He)和氮气(N2)，第二种气体混合物包含臭氧(O3)和任选的氧气(O2)。氦(He)和氮气(N2)作为正硅酸四乙酯(TEOS)的载体的使用产生与常规方法沉积的氧化硅层相比已经改善性能的氧化硅层，即通过本发明的方法沉积的氧化硅层提高了沉积速度，并且改善了湿腐蚀速度比。
图1是可以用于根据本文所述的实施方案进行氧化硅薄膜形成的晶片加工系统10的示意图。系统10一般包括工艺室100、气体面板130、控制单元110、以及其它硬件，如电源和真空泵。本发明中所用的系统10在1998年12月4日提出的共同转让的美国专利申请系列号为No.09/211,998，题为“高温化学气相沉积室”中描述，该专利在本文中引作参考。这种系统10的突出特征在下面简要描述。系统10的实例包括低于大气压的化学气相沉积(SACVD)室，如PRODUCERTM室和PRECISION，可以从Applied Materials Inc.Santa Clara，California购得。
工艺室100一般装有支撑基座150，它用于支撑衬底，如半导体晶片190。该基座150一般使用位移机构在室100内的垂直方向上移动(未表示出)。根据具体方法，晶片在层沉积之前可以加热到某一希望的温度。例如，晶片支撑基座150通过埋入的加热器元件170来加热。基座150可以通过从交流电源106向加热器元件170施加电流来进行电阻加热。晶片190又被基座150加热。
温度传感器172，如热电偶，也埋在晶片支撑基座150中，用常规的方式监测基座150的温度。所测得的温度用在反馈电路中来控制加热元件170的电源106，使得晶片温度可以保持或控制在适合于特定加工用途的希望的温度。基座150任选地使用辐射热(未示出)来加热。
真空泵102用来对工艺室100抽真空，并保持室100内的合适的气体流量和压力。工艺气体通过莲蓬头120引入到室100中，莲蓬头120位于晶片支撑基座150上方。莲蓬头120连接到气体面板130，气体面板控制并提供在工艺顺序的不同步骤中使用的各种气体。
通过质量流量控制器(未示出)和控制单元110，如计算机，来进行通过气体面板130的气体流量的适当控制和调节。例如，气体面板130包括正硅酸四乙酯(TEOS)源132、氦(He)源133、氮气(N2)源134、和臭氧(O3)源135。还可以使用任选的氧气(O2)源136。莲蓬头120可以使来自气体面板130的工艺气体均匀地引入并分布在工艺室100中。
描述性地，控制单元110包含中央处理器(CPU)112、支持电路114和具有相关控制软件的存储器116。这种控制单元110担负晶片处理所要求的各种步骤的自动控制-如晶片输送、气体流量控制、温度控制、室抽真空、和其它步骤。在控制单元110与设备10的各个部件之间的双向联系通过许多统称为信号总线118的许多信号缆线处理，在图1中表示了部分信号总线。
加热基座150一般用铝制成，并且包含在基座150的晶片支撑表面151下一定距离包埋的加热元件170。加热元件170可以用包封在Incaloy套管中的镍-铬丝制成。通过适当调节供给到加热元件170的电流，晶片190和基座150在薄膜沉积过程中可以保持在相对恒定的温度。这可以通过反馈控制回路来实现，其中，通过包埋在基座150中的热电偶172连续监测基座150的温度。这一信息通过信号总线118输送到控制单元110，控制单元110对其产生响应向加热器电源发出必要的信号。随后在电源106中进行调节来保持和控制基座150在希望的温度(即适合于具体工艺应用的温度)。当工艺气体混合物排出莲蓬头120时，工艺气体在加热后的晶片190的表面191上反应，产生二氧化硅层在晶片190上的沉积。
氧化硅层的沉积
一般来说，可以用下列沉积工艺参数使用与图1所示类似的SACVD室来形成氧化硅层。工艺参数范围包括：晶片温度约为150-约850℃、室压力约为1乇-600乇、TEOS流量约500mgm(毫克/分)-1500mgm、氦流量约1000sccm-3000sccm、氮气流量约1000sccm-9000sccm、氧气中的臭氧浓度约12.5重量％，臭氧/氧气流量约1000sccm-6000sccm。氦(He)和氮气(N2)优选的是以约1∶1-1∶3的氦∶氮气流量比供给到沉积室。
其它沉积室也在本发明范围内，上面所列的参数可以根据用来形成氧化硅层的特定沉积室而变化。例如，其它沉积室可以具有更大或更小的体积，需要比购自Applied Materials，Inc.的沉积室所使用更大或更小的气体流量，并且其它沉积室可以构造成能容纳300毫米的衬底。
参见图2a，对于TEOS流量为1100sccm，把氧化硅沉积速度对氮气流量和氦流量的函数关系作三维图。如图2a所示，使用TEOS的混合氦氮载气与使用氦或氮气单独作为载气对比，增大了氧化硅的沉积速度。
参见图2b，对于TEOS流量为1100sccm，把氧化硅湿腐蚀速度比(WERR)(指的是热成氧化硅)对氮气流量和氦流量的函数关系作三维图。如图2b所示，与使用氦或氮气单独作为载气相比，增大氦流量并降低氮气流量降低使用TEOS的混合氦氮载气所沉积的氧化硅层的湿腐蚀速率比。可以认为降低所沉积的氧化硅层的湿腐蚀速度比是更好的氧化物质量的表征(例如，更高密度的薄膜)。
氧化硅沟槽隔离材料
图3a-3c表示在引入氧化硅层作为沟槽隔离材料的集成电路制造序列的不同阶段，衬底200的示意截面图。一般来说，衬底200指的是在其上进行加工的任何工件，衬底结构250用来一般表示与在衬底200上形成的其它材料层在一起的衬底。根据特定的工艺阶段，衬底200可以对应于硅衬底，或已经在衬底上形成的其它材料层。
例如，图3a表示沟槽结构250的截面图。沟槽结构包括有源半导体区域203和沟槽区域204。对于浅沟槽器件，沟槽区域204可以具有约2-3微米的深度，对于深沟槽器件，沟槽区域204可以具有约5-10微米的深度。
图3b表示在图3a的沟槽结构250上形成的氧化硅层205。氧化硅层205填充沟槽结构250的沟槽区域204中。氧化硅层204根据上述工艺参数在衬底结构250上形成。根据要填充的沟槽区域204的深度，氧化硅层的厚度是可以变化的。此后，参见图3c，在有源半导体区域203上形成的氧化硅层205的部分例如可以使用化学机械抛光法(CMP)去除。
虽然已经详细表示并描述了包括本发明的说明中的几个优选的实施方案，熟悉该领域的技术人员可以容易地设计许多仍然包括这些教导中的其它变化的实施方案。
Claims (11)
1.一种在衬底上形成氧化硅层的方法，包括：
把衬底放在沉积室中；
向沉积室中提供第一种气体混合物和第二种气体混合物，其中，第一种气体混合物包含正硅酸四乙酯、氦和氮气，且氦∶氮气的流量比在1∶1-1∶3的范围内，其中，第二种气体混合物包含臭氧；和
使第一种气体混合物与第二种气体混合物在沉积室中反应，在衬底上形成氧化硅层。
2.根据权利要求1的方法，其中，第二种气体混合物中还包含氧气。
3.根据权利要求1的方法，其中，所述衬底保持在150-850℃的温度。
4.根据权利要求1的方法，其中，所述沉积室保持在1乇-600乇的压力。
5.根据权利要求2的方法，其中，在第二种气体混合物中的臭氧浓度为12.5重量％。
6.根据权利要求1的方法，其中，正硅酸四乙酯以500mgm-1500mgm的流量向沉积室中提供，氦气以1000sccm-3000sccm的流量向沉积室中提供，氮气以1000sccm-9000sccm的流量向沉积室内提供。
7.一种器件的制备方法，包括：
在衬底上形成氧化硅层，其中，氧化硅层通过使包含正硅酸四乙酯、氦和氮气的第一种气体混合物与包含臭氧的第二种气体混合物在沉积室中反应形成，其中，在第一种气体混合物中的氦和氮气以1∶1-1∶3的氦∶氮气流量比向沉积室内提供。
8.根据权利要求7的方法，其中，第二种气体混合物还包含氧气。
9.根据权利要求7的方法，其中，所述衬底保持在150-850℃的温度。
10.根据权利要求7的方法，其中，所述沉积室保持在1乇-600乇的压力。
11.根据权利要求8的方法，其中，在第二种气体混合物中的臭氧浓度为12.5重量％。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/839,337 US6511924B2 (en) | 2001-04-20 | 2001-04-20 | Method of forming a silicon oxide layer on a substrate |
| US09/839,337 | 2001-04-20 |
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| CN1383194A CN1383194A (zh) | 2002-12-04 |
| CN1228823C true CN1228823C (zh) | 2005-11-23 |
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| US (1) | US6511924B2 (zh) |
| EP (1) | EP1253630B1 (zh) |
| JP (1) | JP2003031573A (zh) |
| KR (1) | KR20020082139A (zh) |
| CN (1) | CN1228823C (zh) |
| DE (1) | DE60218924T2 (zh) |
| TW (1) | TWI226381B (zh) |
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| US6730619B2 (en) * | 2000-06-15 | 2004-05-04 | Samsung Electronics Co., Ltd. | Method of manufacturing insulating layer and semiconductor device including insulating layer |
| US6887798B2 (en) * | 2003-05-30 | 2005-05-03 | International Business Machines Corporation | STI stress modification by nitrogen plasma treatment for improving performance in small width devices |
| WO2006029651A1 (en) * | 2004-09-16 | 2006-03-23 | S.O.I.Tec Silicon On Insulator Technologies | Method of manufacturing a silicon dioxide layer |
| KR20100032895A (ko) * | 2007-06-15 | 2010-03-26 | 어플라이드 머티어리얼스, 인코포레이티드 | 패턴 로딩 애플리케이션들을 위한 저온 ｓａｃｖｄ 프로세스들 |
| CN102446711A (zh) * | 2011-11-28 | 2012-05-09 | 上海华力微电子有限公司 | 一种mim电容中绝缘层的制作方法 |
| CN102446897A (zh) * | 2011-11-28 | 2012-05-09 | 上海华力微电子有限公司 | 一种金属-绝缘层-金属型电容 |
| CN103305808A (zh) * | 2013-06-13 | 2013-09-18 | 林嘉佑 | 二氧化硅薄膜的生产设备及其生产方法 |
| JP2015117156A (ja) * | 2013-12-18 | 2015-06-25 | 東京エレクトロン株式会社 | 基板処理装置及びオゾンガス濃度の異常検出方法 |
| KR102381344B1 (ko) | 2015-09-18 | 2022-03-31 | 삼성전자주식회사 | 캠형 가스 혼합부 및 이것을 포함하는 반도체 소자 제조 장치들 |
| US10858727B2 (en) | 2016-08-19 | 2020-12-08 | Applied Materials, Inc. | High density, low stress amorphous carbon film, and process and equipment for its deposition |
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| US4892753A (en) | 1986-12-19 | 1990-01-09 | Applied Materials, Inc. | Process for PECVD of silicon oxide using TEOS decomposition |
| WO1990015018A1 (en) | 1989-06-05 | 1990-12-13 | Sumitomo Precision Products Company Limited | Coated dielectric material for an ozone generator |
| US5316639A (en) | 1989-06-05 | 1994-05-31 | Sachiko Okazaki | Dielectric material used for an ozone generator and a method of forming a film to the dielectric material |
| KR0179554B1 (ko) | 1995-11-30 | 1999-04-15 | 김주용 | 반도체 소자의 소자분리절연막 형성방법 |
| US5869394A (en) | 1996-10-29 | 1999-02-09 | Mosel Vitelic, Inc. | Teos-ozone planarization process |
| US5817566A (en) | 1997-03-03 | 1998-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Trench filling method employing oxygen densified gap filling silicon oxide layer formed with low ozone concentration |
| US6551665B1 (en) | 1997-04-17 | 2003-04-22 | Micron Technology, Inc. | Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers |
| US5726090A (en) | 1997-05-01 | 1998-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gap-filling of O3 -TEOS for shallow trench isolation |
| US6121164A (en) * | 1997-10-24 | 2000-09-19 | Applied Materials, Inc. | Method for forming low compressive stress fluorinated ozone/TEOS oxide film |
| US6149987A (en) | 1998-04-07 | 2000-11-21 | Applied Materials, Inc. | Method for depositing low dielectric constant oxide films |
| US6245691B1 (en) * | 1998-05-29 | 2001-06-12 | Taiwan Semiconductor Manufacturing Company | Ozone-teos method for forming with attenuated surface sensitivity a silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer |
| TW429576B (en) * | 1998-10-14 | 2001-04-11 | United Microelectronics Corp | Manufacturing method for metal interconnect |
| US6197705B1 (en) | 1999-03-18 | 2001-03-06 | Chartered Semiconductor Manufacturing Ltd. | Method of silicon oxide and silicon glass films deposition |
| US6090675A (en) | 1999-04-02 | 2000-07-18 | Taiwan Semiconductor Manufacturing Company | Formation of dielectric layer employing high ozone:tetraethyl-ortho-silicate ratios during chemical vapor deposition |
| US6180490B1 (en) | 1999-05-25 | 2001-01-30 | Chartered Semiconductor Manufacturing Ltd. | Method of filling shallow trenches |
| KR100340207B1 (ko) * | 2000-06-15 | 2002-06-12 | 윤종용 | 절연막 및 그의 제조 방법 |
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- 2002-02-26 TW TW091103494A patent/TWI226381B/zh not_active IP Right Cessation
- 2002-03-14 CN CNB021032971A patent/CN1228823C/zh not_active Expired - Fee Related
- 2002-04-17 JP JP2002115098A patent/JP2003031573A/ja active Pending
- 2002-04-20 KR KR1020020021758A patent/KR20020082139A/ko not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| US6511924B2 (en) | 2003-01-28 |
| TWI226381B (en) | 2005-01-11 |
| DE60218924D1 (de) | 2007-05-03 |
| KR20020082139A (ko) | 2002-10-30 |
| US20020155730A1 (en) | 2002-10-24 |
| DE60218924T2 (de) | 2007-12-06 |
| EP1253630A1 (en) | 2002-10-30 |
| JP2003031573A (ja) | 2003-01-31 |
| CN1383194A (zh) | 2002-12-04 |
| EP1253630B1 (en) | 2007-03-21 |
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