CN1185232A - 半导体组件 - Google Patents

半导体组件 Download PDF

Info

Publication number
CN1185232A
CN1185232A CN96194071A CN96194071A CN1185232A CN 1185232 A CN1185232 A CN 1185232A CN 96194071 A CN96194071 A CN 96194071A CN 96194071 A CN96194071 A CN 96194071A CN 1185232 A CN1185232 A CN 1185232A
Authority
CN
China
Prior art keywords
semiconductor chip
circuit board
semiconductor
card
semiconductor subassembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN96194071A
Other languages
English (en)
Other versions
CN1131563C (zh
Inventor
宇佐美光雄
西邦彦
三上喜胜
铃木正胜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Showa Denko Materials Co ltd
Original Assignee
Hitachi Chemical Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd, Hitachi Ltd filed Critical Hitachi Chemical Co Ltd
Publication of CN1185232A publication Critical patent/CN1185232A/zh
Application granted granted Critical
Publication of CN1131563C publication Critical patent/CN1131563C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07728—Physical layout of the record carrier the record carrier comprising means for protection against impact or bending, e.g. protective shells or stress-absorbing layers around the integrated circuit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773—Antenna details
    • G06K19/07777—Antenna details the antenna being of the inductive type
    • G06K19/07779—Antenna details the antenna being of the inductive type the inductive antenna being a coil
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773—Antenna details
    • G06K19/07777—Antenna details the antenna being of the inductive type
    • G06K19/07779—Antenna details the antenna being of the inductive type the inductive antenna being a coil
    • G06K19/07783—Antenna details the antenna being of the inductive type the inductive antenna being a coil the coil being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12033—Gunn diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Credit Cards Or The Like (AREA)
  • Wire Bonding (AREA)
  • Bipolar Transistors (AREA)
  • Die Bonding (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

提供了一种半导体组件,它包括:电路板(1),它包含导体电路(4),该导体电路包含连接焊接区;半导体芯片(2),在其第1面上设有连接端;和安装在电路板上的、覆盖电路板的外壳(5),其中将导体电路的连接焊接区和半导体芯片的连接端配置成互相面对的关系,并用导电粘接剂进行互相连接,半导体芯片的中性平面基本上与半导体组件的总的中性平面重合。

Description

半导体组件
技术领域
本发明涉及一种既可靠又经济的半导体组件。
发明背景
半导体器件领域中的近来的发展是引人注目的，半导体器件的应用领域已在连续地扩展。与可认为是半导体器件的核心的半导体芯片的发展相同步，对于半导体芯片的封装已进行了很大的改进。
例如，已提出了各种不同的建议来改善诸如公用电话磁卡的预付卡、诸如机动车司机执照的个人身份卡和火车通行证的安全性和增加其方便性。
如在由Shadan Hojin Joho Shori Gakkai编辑的、由KK Ohm出版的“信息处理手册”(第1版，1990年5月30日，第302至304页)中所描述的那样，这种IC卡的特征在于由下述部分构成：具有导体电路的电路板；安装在该电路板上的半导体芯片；可选择的诸如电容器的电子元件；用于接收和传送进入或离开该电路板的信号的器件；和用于覆盖该电路板的外壳。
关于该IC卡的结构，如在由Shadan Hojin Joho Denshi Joho TsushinGakkai编辑的、由KK Ohm出版的“IC卡”(第1版，1990年5月25日，第33页)中所描述的那样，也已知，如图8所说明的，将半导体芯片通过使用粘接剂10固定到卡基板1上，并用键合引线11连接半导体芯片的连接端与该卡基板的连接端。
这里考虑的半导体芯片的厚度约从200至400微米，半导体芯片抗弯曲应力的能力不是很强，故需要控制加在半导体芯片上的应力。因而，必须限制半导体芯片的尺寸，和/或必须用抗弯曲应力的材料来制成外壳。
如日本专利公开(kokai)出版物第3-87299号中所公开的，也已知通过制备包括非常薄的LSI的IC模块和将该IC模块安装在封装体的表面上设置的凹槽内来制作IC卡，其中上述薄的LSI是通过将LSI研磨减薄同时使驱动器件保持不变来制备的。与使用安装在较厚的基板上的非常薄的LSI的IC卡相联系的一个固有的问题是缺乏可靠性，这是因为薄的LSI在卡基板经受弯曲变形时对于加到LSI芯片的正面和反面的张应力和压应力是易损坏的。
在日本专利公开(kokai)出版物第7-99267号中建议将该薄的IC放在IC卡厚度的中间部分作为克服这个问题的方法。按照该技术，如图9所示，将半导体芯片2安装在印刷电路板1上，使半导体芯片的连接端和印刷电路板的连接端暴露在一个共同的面上，用被印制的导电糊剂12使半导体芯片的连接端和印刷电端板的连接端互相进行电连接。
但是，按照该方法，在该方法中将半导体芯片安装在印刷电路板上，使半导体芯片的连接端和印刷电路板的连接端暴露在一个共同的面上，用被印制的导电糊剂使半导体芯片的连接端和印刷电路板的连接端互相进行电连接，当使IC卡经受弯曲变形时，应力趋向于集中在半导体芯片的连接端和印刷电路板的连接端之间的边界内，在导电糊剂中可能产生裂缝，其结果是存在电断路的很大的危险性。
发明简述
鉴于现有技术的这种问题，本发明的主要目的是提供这样一种半导体组件，该组件可提供很高的对于电断路的可靠性，该组件对于制造来说是经济的。
本发明的第二个目的是提供一种可经受重复弯曲变形的半导体组件。
本发明的第三个目的是提供适合用作IC卡的半导体组件。
本发明的这些和其他的目的可通过提供下述的半导体组件来达到，该组件包括：包含导体电路的电路板，该导体电路包含连接焊接区；在其第1面上设有连接端的、安装在电路板上的半导体芯片；覆盖该电路板的外壳；其中将导体电路的连接焊接区和半导体芯片的连接端以彼此面对的关系来配置，并用导电粘接剂互相连接，半导体芯片的中性平面基本上与半导体组件的总的中性平面重合。
导电粘接剂最好由各向异性的导电粘接膜来构成。该导体电路可通过例如用丝网印刷在电路板上淀积导电油墨或通过有选择地刻蚀在电路板上形成的一层诸如铜箔的金属箔来形成。该导体电路还可包括至少在电路板的一个面上形成的天线电路。
按照本发明，因为彼此面对地设置半导体芯片和电路板的导体电路的连接端，故可减少连接部分的厚度，与常规的基于引线键合工艺的方法或基于涂敷导电油墨的方法相反，可简化电连接的步骤。
通过将多层塑料膜、塑料薄片或涂敷了粘接剂的塑料薄片固定到电路板的上表面和下表面上以便将半导体芯片放置在组件的厚度的中点，可在该组件经受弯曲应力时使电连接处的应力集中为最小。
再有，通过对电路板的导体电路使用导电油墨，与迄今能做到的相比，可制造更经济和更平整的IC卡。
最好将一般由涂敷了粘接剂的膜构成的衬垫固定到电路板的一个面上，该膜设有用于在其中容纳半导体芯片的切口。这提供了一种方便的途径来界定用于在其中容纳半导体芯片的凹槽，而不会使该组件的外表面上出现任何不平整性。特别是通过将电子元件的半导体芯片的外轮廓和该衬垫中的切口的外周边之间的间隙设置在预定的范围内，可消除任何可能另外陷在该间隙内的气泡，可提供可靠的和具有平整表面的IC卡。
希望本发明中使用的半导体芯片尽可能地薄，可以是任何普通类型的而没有任何限制。
用于电路板的绝缘材料可由普通的塑料膜或塑料薄片，或用玻璃纤维增强的塑料薄片组成，上述塑料膜或塑料薄片如聚碳酸酯膜、聚乙烯膜、聚对苯二甲酸乙酯膜、聚酰亚胺膜和PVC膜。根据机械强度和成本，聚对苯二甲酸乙酯膜是比较理想的。从市场可购买到的材料包括Diafoil(商标名，Diafoil Hoekist KK)，Teijin Tetron膜(商标名，Teijin KK)和Toyobo Ester膜(商标名，Toyobo KK)。
可通过在用粘接剂层叠有铜层的膜上淀积抗蚀剂和用刻蚀除去铜层的不需要的部分，或在另一种方式下通过用丝网印刷在膜的表面上涂敷导电糊剂并固化该糊剂，从而在膜的表面上形成电路导体图形。
本发明中使用的导电粘接剂可由混合有诸如银粒子和铜粒子等导电粒子的聚酯树脂、苯酚树脂或环氧树脂构成。从市场可购买到的材料包括LS-3015HV，LS-1048，和ACP-105(商标名，由KK Asahi KagakuKenkyusho制造)，和FA-705A，XA-220，XA-412，D-723S，和XA-256M(商标名，由Fujikura Kasei KK制造)。
也可使用各向异性的导电粘接膜来代替这种粘接剂，从市场上能购买到的材料中可选择Anisolm(商标名，Hitachi Kasei Kogyo KK)。
能用于本发明的粘接剂可由聚酯树脂、环氧树脂或丙烯腈树脂组成。
在其上涂敷粘接剂的塑料膜，塑料薄片或玻璃纤维增强的塑料薄片可在其对应于安装半导体芯片和电子元件的位置的部分设置切口。
每个切口的尺寸可按照半导体芯片或电子元件的厚度来选择。例如，当半导体芯片或电子元件的厚度是从110至260微米时，在半导体芯片或电子元件的外轮廓和在衬垫内形成的切口的内轮廓之间的间隙最好是从50至500微米。再有，当半导体芯片或电子元件的厚度是从50至110微米时，间隙最好是从50至1000微米，当半导体芯片或电子元件的厚度是从0.5至50微米时，间隙最好是从50至2000微米。
如间隙大于预定范围，则已完成的卡的表面可能有大的不平整性。如间隙小于预定范围，则定位变得非常困难。
附图的简单描述
以下参照附图描述本发明，其中：
图1是示出本发明的一个实施例的剖面图；
图2是图1的组件的一部分的平面图；
图3是图1和图2中示出的衬垫的平面图；
图4是示出本发明的另一个实施例的、类似于图1的视图；
图5是示出本发明的又一个实施例的、类似于图1的视图；
图6是图5的电路板的正面的平面图；
图7是图5的电路板的反面的平面图；
图8是示出现有例的剖面图；
图9是示出另一现有例的剖面图；和
图10示出最小可容许的曲率半径和半导体芯片的厚度之间的关系图。
优选实施例的详细描述
实施例1
如图1和2中所示，通过使用一种导电糊剂3(FA-320，商标名，由KK Asahi Kagaku Kenkyusho制造)将厚度为30微米的半导体和其他电子芯片2(IC和电容器)固定到其上具有印刷电路4的电路板1的一个表面上。也可通过有选择地刻蚀一层铜箔来形成印刷电路4。将具有切口8的衬垫薄片7放置在电路板1的表面上。图3以平面图示出该衬垫7。将切口8的尺寸作成围绕每个芯片界定50至2000微米的间隙。在本实施例中，衬垫薄片7包括涂敷了25微米厚的粘接剂层71的25微米厚的聚对苯二甲酸乙酯膜72，和在图中未示出的1微米厚的底层。另外，通过利用层合机将由涂敷了20微米厚的粘接剂层51的125微米厚的聚对苯二甲酸乙酯膜52组成的、用作上盖的外壳5层叠在衬垫7上。一旦该层叠工艺完成，就将该芯片放置于厚度为516微米的IC卡的中性平面内。换言之，将半导体芯片2基本上放置在IC卡的厚度的中间部分。因为由于IC卡的弯曲变形而产生的压应力和张应力随离开中性平面的距离而线性地成比例地增加，故半导体芯片2基本上不受压应力和张应力的影响。当IC卡组件基本均匀时，这里定义的中性平面可以是几何学上的中性平面，但象在机械领域中熟知的那样，如果在IC卡的结构中在几何学中性平面附近存在任何不对称性，则上述中性平面也可偏离几何学上的中性平面。
实施例2
如图4中所示，将涂敷了20微米厚粘接剂层51的75微米厚的聚对苯二甲酸乙酯膜5 2构成的附加层层叠在实施例1的IC卡的上表面和下表面上，以制成厚度为516微米的IC卡。这样，在这种情况下，外壳5包括一对上层52和单一下层52。
实施例3
与实施例2类似，将涂敷了20微米厚粘接剂层51的188微米厚的聚对苯二甲酸乙酯膜52构成的附加层层叠在实施例1的IC卡的上表面和下表面上，以制成厚度为742微米的IC卡。
实施例4
使用30微米厚的芯片2来代替实施例1的50微米厚的芯片，使用由聚对苯二甲酸乙酯制成的50微米厚的衬垫7来制造厚度为346微米的IC卡。
实施例5
将涂敷了20微米厚粘接剂层51的75微米厚的聚对苯二甲酸乙酯膜52构成的附加层层叠在实施例4的IC卡的上表面和下表面上，以制造如图4中示出的厚度为536微米的IC卡。
实施例6
与实施例5类似，将一个覆盖膜，一个涂敷了20微米厚粘接剂层51的188微米厚的聚对苯二甲酸乙酯膜52构成的附加层层叠在实施例4的IC卡的上表面和下表面上，以制成厚度为762微米的IC卡。
实施例7
使用100微米厚的半导体芯片2来代替实施例1的芯片，使用由聚对苯二甲酸乙酯膜72制成的100微米厚的衬垫7来制造厚度为346微米的IC卡。切口8是这样设置的，使得围绕每个由IC和其他电子元件组成的芯片2界定50至1000微米的间隙。
实施例8
将涂敷了20微米厚粘接剂层51的75微米厚的聚对苯二甲酸乙酯膜52构成的附加层层叠在实施例7的IC卡的上表面和下表面上，以制造如图4中示出的厚度为586微米的IC卡。
实施例9
与实施例8类似，将涂敷了20微米厚粘接剂层51的188微米厚的聚对苯二甲酸乙酯膜52构成的附加层层叠在实施例7的IC卡的上表面和下表面上，以制成厚度为812微米的IC卡。
实施例10
使用200微米厚的芯片2来代替实施例1的芯片，使用由聚对苯二甲酸乙酯膜72制成的188微米厚的衬垫7来制造厚度为496微米的IC卡。切口8是这样设置的，使得围绕每个芯片2界定50至500微米的间隙。
实施例11
将涂敷了20微米厚的粘接剂层51的75微米厚的聚对苯二甲酸乙酯膜52构成的附加层层叠在实施例10的IC卡的上表面和下表面上，以制成图4中示出的厚度为686微米的IC卡。
实施例12
与实施例11类似，将涂敷了20微米厚粘接剂层51的188微米厚的聚对苯二甲酸乙酯膜52构成的附加层层叠在实施例10的IC卡的上表面和下表面上，以制造厚度为912微米的IC卡。
实施例13
使用500微米厚的芯片2来代替实施例1的芯片，使用由聚对苯二甲酸乙酯膜72制成的500微米厚的衬垫7来制造厚度为796微米的IC卡。
实施例14
将涂敷了20微米厚粘接剂层51的75微米厚的聚对苯二甲酸乙酯膜52构成的附加层层叠在实施例13的IC卡的上表面和下表面上，以制成图4中示出的厚度为986微米的IC卡。
实施例15
与实施例14类似，将涂敷了20微米厚粘接剂层51的188微米厚的聚对苯二甲酸乙酯膜52构成的附加层层叠在实施例10的IC卡的上表面和下表面上，以制造厚度为1,212微米的IC卡。
实施例16
参照图5至7，其中对应于以上的实施例的部分用相同的数字来表示，通过将由18微米厚导电层组成的天线电路41放置在75微米厚的聚对苯二甲酸乙酯膜层的两个表面上来形成印刷电路板1，通过使用以商标名为Anisolm销售的各向异性导电膜将厚度为50微米的半导体芯片和电容器芯片4a和4b安装在该印刷电路板1上，以形成IC卡的功能部分。
在75微米厚的聚对苯二甲酸乙酯膜层的每个面上形成天线线圈41和42，将该膜的上表面和下表面上的两个线圈经由预先在电路板1的预定部分设置的通孔43和44而互相连接。
将三层衬垫膜71放置在该功能部分上，将一对由涂敷了24微米厚粘接剂层的188微米和75微米厚的聚对苯二甲酸乙酯组成的覆盖膜层52通过使用层合机分别层叠在该组件的上表面和下表面上，从而在层叠工艺之后形成厚度为474微米的IC卡。
实施例17
使用一对由250微米和125微米厚的聚对苯二甲酸乙酯组成的覆盖膜层51分别代替实施例16的188微米厚的上覆盖膜和75微米厚的下覆盖膜，从而得到厚度为574微米的IC卡。
实施例18
对印刷电路板1使用125微米厚的聚对苯二甲酸乙酯膜来代替实施例16的75微米厚的膜，以改善印刷精度。另外，分别使用测量厚度分别为188微米和100微米的二层覆盖膜51作为上覆盖膜，使用125微米厚的膜代替75微米厚的下覆盖膜，从而得到厚度为720微米的IC卡。
实施例19
在实施例10和13中，在L-K＞500微米的条件下，其中K是芯片的尺寸，L是衬垫内的切口8的尺寸，在IC卡的表面产生超过100微米的表面不平整度。这些不平整度可归因于过大的内部间隙的尺寸，通过调整使得L-K＜500微米可将表面不平整度降低到80微米或更小。
实施例20
在实施例7中，在L-K＞1000微米的条件下，在IC卡的表面是产生超过100微米的表面不平整度。这些不平整度可归因于过大的内部间隙的尺寸，通过调整使得L-K＜1000微米可将表面不平整度降低到80微米或更小。
实施例21
在实施例4中，在L-K＞2000微米的条件下，在IC卡的表面是产生超过100微米的表面不平整度。这些不平整度可归因于过大的内部间隙的尺寸，通过调整使得L-K＜2000微米可将表面不平整度降低到80微米或更小。
对这样制备的IC卡在经受弯曲变形时的电连接的可靠性进行了测试。在一些情况下已观察到物理损伤，但当曲率半径为2.5至5mm时对50微米厚的IC芯片不发生电断路，当曲率半径为10至15mm时对100微米厚的IC芯片不发生电断路，当曲率半径为25至30mm时对200微米厚的IC芯片不发生电断路。图10是示出最小可容许的曲率半径和半导体芯片的厚度之间的关系图，该图是通过应用实施例1的配置从实验得到的。
为了比较，按照日本专利公开出版物第7-99267号的所述内容通过将半导体芯片安装在电路基板上来制备IC卡，其中使半导体芯片的连接端和该电路基板的连接端暴露在一个共同的面上和通过使用导电糊剂将这些连接端互相连接。其材料与实施例1中使用的材料相同，使最终厚度与按照本发明的组件的最终厚度一致。按照这些用于比较的IC卡，对于弯曲应力的相同范围，在20％至40％的情况下发生电断路，这一点证明了按照本发明制备的IC卡中的电连接的高的可靠性。因此，本发明的器件对于电连接是高可靠的，对于制造来说是经济的。
虽然已根据特定的实施例对本发明进行了描述，但在不偏离本发明的精神的情况下可进行修正和改变其细节。

Claims (10)

1.一种半导体组件，包括：
电路板(1)，包含导体电路，所述导体电路包含连接焊接区；
半导体芯片(2)，在其第1面上设有连接端，该半导体芯片安装在所述电路板上；和
外壳(5)，覆盖所述电路板；
其中将所述导体电路的连接焊接区和半导体芯片的所述连接端以彼此面对的关系来配置，并用导电粘接剂互相连接，半导体芯片的中性平面基本上与所述半导体组件的总的中性平面重合。
2.如权利要求1所述的半导体组件，其中所述导电粘接剂由各向异性的导电粘接膜来构成。
3.如权利要求1所述的半导体组件，其中所述导体电路可通过在所述电路板上淀积导电油墨来形成。
4.如权利要求1所述的半导体组件，其中所述导体电路可通过有选择地刻蚀在所述电路板上形成的一层金属箔来形成。
5.如权利要求1所述的半导体组件，其中所述导体电路还包括至少在所述电路板的一个面上形成的天线电路(41，42)。
6.如权利要求1所述的半导体组件，其中将由覆盖了粘接剂的膜组成的衬垫(7)固定到所述电路板的表面上，所述膜设有用于在其中容纳所述半导体芯片的切口(8)。
7.如权利要求6所述的半导体组件，其中在所述半导体芯片的周边部分和所述切口的周围边缘之间的间隙足够小，以避免任何不可接受的表面不平整性在所述组件中发展。
8.如权利要求1所述的半导体组件，其中在所述半导体芯片的周边部分和所述切口的周围边缘之间的间隙足够小，以使L-K＜2000微米，其中L是所述切口的尺寸，K是所述半导体芯片的对应的尺寸。
9.如权利要求1所述的半导体组件，其中所述外壳包括放置在所述电路板上的塑料膜。
10.如权利要求1所述的半导体组件，其中所述半导体芯片具有不大于200微米的厚度。
CN96194071A 1995-05-23 1996-05-22 半导体组件 Expired - Fee Related CN1131563C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP7123574A JPH08310172A (ja) 1995-05-23 1995-05-23 半導体装置
JP123574/95 1995-05-23
JP123574/1995 1995-05-23

Publications (2)

Publication Number Publication Date
CN1185232A true CN1185232A (zh) 1998-06-17
CN1131563C CN1131563C (zh) 2003-12-17

Family

ID=14863957

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96194071A Expired - Fee Related CN1131563C (zh) 1995-05-23 1996-05-22 半导体组件

Country Status (10)

Country Link
US (1) US6166911A (zh)
EP (1) EP0827633A1 (zh)
JP (1) JPH08310172A (zh)
CN (1) CN1131563C (zh)
AU (1) AU733309B2 (zh)
CA (1) CA2221931A1 (zh)
IN (1) IN190513B (zh)
MY (1) MY132328A (zh)
TW (1) TW317691B (zh)
WO (1) WO1996037917A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102005083A (zh) * 2009-08-31 2011-04-06 Ncr公司 安全电路板组件
US9560772B2 (en) 2007-09-04 2017-01-31 Robert Bosch Gmbh Electric circuit configuration having an MID circuit carrier and a connecting interface connected to it

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU1174197A (en) * 1996-12-26 1998-07-31 Hitachi Limited Semiconductor device and method of manufacturing the same
US6331722B1 (en) 1997-01-18 2001-12-18 Semiconductor Energy Laboratory Co., Ltd. Hybrid circuit and electronic device using same
FR2761498B1 (fr) * 1997-03-27 1999-06-18 Gemplus Card Int Module electronique et son procede de fabrication et carte a puce comportant un tel module
JPH1140522A (ja) 1997-07-17 1999-02-12 Rohm Co Ltd 半導体ウエハの製造方法、この方法により作製された半導体ウエハ、半導体チップの製造方法、およびこの方法により製造された半導体チップ、ならびにこの半導体チップを備えたｉｃカード
FR2769109B1 (fr) * 1997-09-26 1999-11-19 Gemplus Sca Dispositif electronique a puce jetable et procede de fabrication
WO1999032304A1 (en) * 1997-12-22 1999-07-01 Hitachi, Ltd. Semiconductor device
EP0942392A3 (en) * 1998-03-13 2000-10-18 Kabushiki Kaisha Toshiba Chip card
EP0967568B1 (de) * 1998-06-23 2006-08-30 Meto International GmbH Identifizierungselement
JP2000099678A (ja) * 1998-09-18 2000-04-07 Hitachi Ltd Ｉｃカード及びその製造方法
FR2784210B1 (fr) * 1998-10-02 2001-09-14 Gemplus Card Int Carte a puce sans contact comportant des moyens d'inhibition
US6429386B2 (en) * 1998-12-30 2002-08-06 Ncr Corporation Imbedded die-scale interconnect for ultra-high speed digital communications
FR2798225B1 (fr) * 1999-09-03 2001-10-12 Gemplus Card Int Micromodule electronique et procede de fabrication et d'integration de tels micromodules pour la realisation de dispositifs portatifs
JP2002318770A (ja) * 2001-04-20 2002-10-31 Nec Corp 受信メール自動振り分け装置、受信メール自動振り分け方法、および受信メール自動振り分けプログラム
ATE555911T1 (de) 2001-12-24 2012-05-15 L 1 Secure Credentialing Inc Verfahren zur vollfarb-markierung von id- dokumenten
CA2469956C (en) * 2001-12-24 2009-01-27 Digimarc Id Systems, Llc Contact smart cards having a document core, contactless smart cards including multi-layered structure, pet-based identification document, and methods of making same
US7824029B2 (en) 2002-05-10 2010-11-02 L-1 Secure Credentialing, Inc. Identification card printer-assembler for over the counter card issuing
US6664701B1 (en) * 2002-06-13 2003-12-16 Black & Decker Inc. Brush assembly
JP2004185208A (ja) * 2002-12-02 2004-07-02 Sony Corp Ｉｃカード
US7652359B2 (en) * 2002-12-27 2010-01-26 Semiconductor Energy Laboratory Co., Ltd. Article having display device
EP1614064B1 (en) 2003-04-16 2010-12-08 L-1 Secure Credentialing, Inc. Three dimensional data storage
EP1879254A4 (en) 2005-03-25 2010-01-27 Toray Industries PLANE ANTENNA AND METHOD FOR MANUFACTURING THE SAME
US20090033495A1 (en) * 2007-08-03 2009-02-05 Akash Abraham Moldable radio frequency identification device
DE102011115315A1 (de) * 2011-09-29 2013-04-04 Infineon Technologies Ag Chipkarten-Modul für eine Chipkarte
SG11201405887RA (en) * 2012-03-22 2014-11-27 Dainippon Printing Co Ltd Card and card production method

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60252992A (ja) * 1984-05-30 1985-12-13 Toshiba Corp Ｉｃカ−ド
JPS61123990A (ja) * 1984-11-05 1986-06-11 Casio Comput Co Ltd Ｉｃカ−ド
US4889980A (en) * 1985-07-10 1989-12-26 Casio Computer Co., Ltd. Electronic memory card and method of manufacturing same
JPH01267098A (ja) * 1988-04-20 1989-10-24 Matsushita Electric Ind Co Ltd Ｉｃカードおよびその製造方法
JPH0387299A (ja) * 1989-08-31 1991-04-12 Sharp Corp Ｉｃカード
JPH05278383A (ja) * 1992-04-03 1993-10-26 Kyodo Printing Co Ltd Ｉｃカード
JP2970411B2 (ja) * 1993-08-04 1999-11-02 株式会社日立製作所 半導体装置
EP0704928A3 (en) * 1994-09-30 1998-08-05 HID Corporation RF transponder system with parallel resonant interrogation and series resonant response
US5574470A (en) * 1994-09-30 1996-11-12 Palomar Technologies Corporation Radio frequency identification transponder apparatus and method
ATE167319T1 (de) * 1994-11-03 1998-06-15 Fela Holding Ag Basis folie für chip karte
US5671525A (en) * 1995-02-13 1997-09-30 Gemplus Card International Method of manufacturing a hybrid chip card
US5733814A (en) * 1995-04-03 1998-03-31 Aptek Industries, Inc. Flexible electronic card and method
FR2738932B1 (fr) * 1995-09-15 1997-11-28 Innovatron Ind Sa Collecteur d'onde en forme de bobinage imprime pour objet portatif electronique tel que carte ou badge sans contact

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9560772B2 (en) 2007-09-04 2017-01-31 Robert Bosch Gmbh Electric circuit configuration having an MID circuit carrier and a connecting interface connected to it
CN102005083A (zh) * 2009-08-31 2011-04-06 Ncr公司 安全电路板组件
CN102005083B (zh) * 2009-08-31 2014-04-16 Ncr公司 安全电路板组件

Also Published As

Publication number Publication date
WO1996037917A1 (en) 1996-11-28
TW317691B (zh) 1997-10-11
AU5778196A (en) 1996-12-11
US6166911A (en) 2000-12-26
AU733309B2 (en) 2001-05-10
IN190513B (zh) 2003-08-02
MY132328A (en) 2007-10-31
CA2221931A1 (en) 1996-11-28
EP0827633A1 (en) 1998-03-11
CN1131563C (zh) 2003-12-17
JPH08310172A (ja) 1996-11-26

Similar Documents

Publication Publication Date Title
CN1131563C (zh) 半导体组件
US4677528A (en) Flexible printed circuit board having integrated circuit die or the like affixed thereto
CN1183485C (zh) 芯片卡或类似电子装置的制造方法
CN1063579C (zh) 半导体装置
CN1146828C (zh) 无接点电子存储卡片及其制造方法
CN1295645C (zh) 非接触式数据载体的制造方法
US7229850B2 (en) Method of making assemblies having stacked semiconductor chips
CN100342536C (zh) 集成电子微组件及制造该微组件的方法
EP0766197A1 (en) Ic card and ic module
CN1780532A (zh) 制造刚性－柔性印刷电路板的方法
CN1134064C (zh) 半导体芯片用的载体元件
CN1420714A (zh) 薄型电路板及薄型电路板的制造方法
CN1467685A (zh) Ic卡及其制造方法
CN1622126A (zh) 用于制造ic卡的方法
CN1429063A (zh) 多层印制线路板及其制造方法、电子设备
CN1663331A (zh) 制造电路的方法
CN1214346C (zh) 无触点芯片卡,无触点支撑体及其制造方法
CN1238856A (zh) 芯片模块及制造芯片模块的方法
JP2000182017A (ja) 接触型非接触型共用ｉｃカードおよびその製造方法
CN1555576A (zh) 电子标签及其制造方法
CN1521842A (zh) 电子部件的安装体及其制造方法
CN1313966C (zh) Ic卡的制造方法
CN1351733A (zh) 一种采用廉价绝缘材料的便携式集成电路电子设备的制造方法
CN1849036A (zh) 薄型电路板及薄型电路板的制造方法
CN1147931C (zh) 半导体器件及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
REG Reference to a national code

Ref country code: HK

Ref legal event code: WD

Ref document number: 1009559

Country of ref document: HK

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20031217

Termination date: 20110522