CN118507426A

CN118507426A - Method for directly connecting field regions of stacked transistor, stacked transistor and device

Info

Publication number: CN118507426A
Application number: CN202410414514.5A
Authority: CN
Inventors: 吴恒; 郭睿; 卢浩然; 王润声; 黎明; 黄如
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2024-04-08
Filing date: 2024-04-08
Publication date: 2024-08-16

Abstract

The application provides a field direct connection method of a stacked transistor, the stacked transistor and a device. The field direct connection method comprises the following steps: forming an active structure on a substrate, the active structure comprising a first active structure and a second active structure, the first active structure being remote from the substrate relative to the second active structure; forming a first transistor based on the first active structure; rewinding the first transistor and removing the substrate to expose the second active structure; forming a second transistor based on the second active structure; etching the first transistor and the second transistor in a double-diffusion isolation region to form a first groove, wherein the double-diffusion isolation region is used for isolating two adjacent stacked transistors; and filling a metal material in the first groove to form an interconnection through hole structure, wherein the interconnection through hole structure is used for connecting the first metal interconnection layer of the first transistor and the second metal interconnection layer of the second transistor.

Description

Method for directly connecting field regions of stacked transistor, stacked transistor and device

Technical Field

The present application relates to the field of integrated semiconductors, and more particularly, to a field direct connection method for stacked transistors, and devices.

Background

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. The stacked transistor stacked transistor further improves the transistor integration density by integrating two or more layers of transistors in a vertical space, which is one of the important technologies for continuing the miniaturization of integrated circuit dimensions.

In the related art, when preparing a Field Direct Connection (FDC) structure of an upper transistor and a lower transistor in a stacked transistor, a field is added to a standard cell of the stacked transistor to make a FIELD DIRECT Contact (FDC) structure. However, this increases the area of the standard cell of the stacked transistor, which is disadvantageous for integration of the stacked transistor.

Disclosure of Invention

The application provides a field direct connection method of a stacked transistor, the stacked transistor and a device, which can effectively improve the integration level of the stacked transistor.

In a first aspect, an embodiment of the present application provides a method for directly connecting field regions of stacked transistors, the method including: forming an active structure on a substrate, the active structure comprising a first active structure and a second active structure, the first active structure being remote from the substrate relative to the second active structure; forming a first transistor based on the first active structure; rewinding the first transistor and removing the substrate to expose the second active structure; forming a second transistor based on the second active structure; etching the first transistor and the second transistor in a double-diffusion isolation region to form a first groove, wherein the double-diffusion isolation region is used for isolating two adjacent stacked transistors; and filling a metal material in the first groove to form an interconnection through hole structure, wherein the interconnection through hole structure is used for connecting the first metal interconnection layer of the first transistor and the second metal interconnection layer of the second transistor.

In one possible embodiment, after forming the first transistor based on the first active structure, the method further comprises: forming a first metal interconnection layer on the first transistor; etching the first transistor and the second transistor in the double diffusion isolation region to form a first recess, comprising: coating photoresist on the upper side of the second transistor to form a photoresist layer, wherein the photoresist layer covers the region except the double diffusion isolation region in the second transistor; and etching the first transistor and the second transistor by taking the photoresist layer as a mask until the first metal interconnection layer to form a first groove.

In one possible embodiment, after forming the first transistor based on the first active structure, the method further comprises: etching the first transistor in the double-diffusion isolation region to form a second groove; filling a metal material in the second groove to form a first interconnection through hole structure; after forming the second transistor based on the second active structure, the method further comprises: etching the second transistor in the double-diffusion isolation region to form a third groove; and filling a metal material in the third groove to form a second interconnection through hole structure, wherein the first interconnection through hole structure and the second interconnection through hole structure form an interconnection through hole structure.

In one possible embodiment, etching the first transistor in the double diffusion isolation region to form a second recess includes: coating photoresist on the upper side of the first transistor to form a photoresist layer, wherein the photoresist layer covers the region except the double diffusion isolation region in the first transistor; etching the first transistor until the shallow trench isolation structure is formed by taking the photoresist layer as a mask to form a second groove, wherein the shallow trench isolation structure is positioned at two sides of the active structure to isolate the first transistor and the second transistor; etching the second transistor in the double diffusion isolation region to form a third recess, comprising: coating photoresist on the upper side of the second transistor to form a photoresist layer, wherein the photoresist layer covers the region except the double diffusion isolation region in the second transistor; and etching the second transistor until the first interconnection through hole structure by taking the photoresist layer as a mask so as to form a third groove.

In one possible embodiment, the double diffusion isolation region includes a first diffusion isolation region on one side of the stacked transistor and/or a second diffusion isolation region on the other side of the stacked transistor.

In one possible embodiment, filling a metal material in the first recess to form an interconnect via structure includes: depositing an isolation material on the inner wall of the first groove to form an isolation layer; and filling a metal material in the first groove to form an interconnection through hole structure, wherein the interconnection through hole structure is isolated from the active structure through an isolation layer.

In one possible implementation, forming a first transistor based on a first active structure includes: epitaxially growing a first source-drain structure on the first active structure; forming a first source drain metal on the first source drain structure; forming a first gate structure based on the first active structure; forming a second transistor based on the second active structure, comprising: epitaxially growing a second source-drain structure on the second active structure; forming a second source-drain metal on the second source-drain structure; a second gate structure is formed based on the second active structure.

In one possible embodiment, the active structure is formed on a substrate, the method further comprising: providing a substrate; etching a first portion of the substrate to form an initial active structure; etching the initial active structure of the stacked transistor in the two side areas to form an active structure; an oxide material is deposited over the second portion of the substrate to form a shallow trench isolation structure having a height that is lower than a height of the active structure.

In one possible embodiment, rewinding the first transistor and removing the substrate to expose the second active structure comprises: rewinding the first transistor and removing the substrate; and thinning the shallow trench isolation structure to a preset height so as to expose the second active structure, wherein the thinned shallow trench isolation structure is used for isolating the first transistor and the second transistor.

In a second aspect, an embodiment of the present application provides a stacked transistor, which is manufactured by the method described in the first aspect and any embodiment thereof, including: a first transistor; the first transistor and the second transistor are arranged in a back-to-back manner; the first active structure of the first transistor and the second active structure of the second transistor form an active structure, an interconnection through hole structure is formed in the double-diffusion isolation region of the first transistor and the double-diffusion isolation region of the second transistor, and the first metal interconnection layer of the first transistor is connected with the second metal interconnection layer of the second transistor through the interconnection through hole structure.

In a third aspect, an embodiment of the present application provides a semiconductor device, including: a stacked transistor as described in the second aspect above.

In a fourth aspect, an embodiment of the present application provides an electronic device, including: a circuit board and the semiconductor device according to the third aspect, the semiconductor device being provided to the circuit board.

The technical scheme provided by the application can comprise the following beneficial effects:

In the embodiment of the application, a first transistor is formed through a first active structure, the first transistor is reworked, after a second transistor is formed based on an exposed second active structure, the first transistor and the second transistor are etched in a double-diffusion isolation region to form an interconnection through hole structure, and the interconnection through hole structure is used for connecting a first metal interconnection layer of the first transistor and a second metal interconnection layer of the second transistor. That is, the scheme of the application is to manufacture an interconnection through hole structure (FDC structure) in the double diffusion isolation region, so that more space is not required to be occupied, the area of a standard unit of the stacked transistor is not increased, and the integration level of the stacked transistor is effectively improved. In addition, because the area of the double diffusion isolation region is larger, the interconnection through hole structure manufactured in the double diffusion isolation region can be made wider, the resistance is reduced, and meanwhile, the requirement on the lithography precision is reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic flow chart of an embodiment of a field direct connection method of stacked transistors;

FIG. 2 is a schematic top view of a stacked transistor according to an embodiment of the present application;

Fig. 3 to 17 are schematic views illustrating a first process for manufacturing a stacked transistor according to an embodiment of the present application;

Fig. 18 is a schematic diagram of a first structure of a stacked transistor according to an embodiment of the present application;

fig. 19 to 28 are schematic views illustrating a second process for manufacturing a stacked transistor according to an embodiment of the present application;

fig. 29 is a schematic diagram of a second structure of stacked transistors in an embodiment of the application;

FIG. 30 is a schematic top view of another stacked transistor according to an embodiment of the present application;

fig. 31 is a schematic diagram of a third structure of a stacked transistor according to an embodiment of the present application;

fig. 32 is a schematic diagram of a fourth structure of stacked transistors in an embodiment of the application;

fig. 33 is a schematic diagram of a fifth structure of a stacked transistor in an embodiment of the application;

fig. 34 is a schematic diagram of a sixth structure of a stacked transistor in an embodiment of the application.

The figures above:

10. Stacking transistors; 11. a first transistor (front side transistor); 111. a first fin structure (first active structure); 112. a first source drain structure; 113. a first interlayer dielectric layer; 114. a first gate structure; 115. a first source drain metal; 116. a first metal interconnect layer; 12. a second transistor (back side transistor); 121. second fin structure (second active structure; 122, second source-drain structure; 113, second interlayer dielectric layer; 124, second gate structure; 125, second source-drain metal; 126, second metal interconnect layer; 20, substrate; 21, initial fin structure (initial active structure); 210, fin structure (active structure); 22, shallow trench isolation structure; 23, first dummy gate structure; 24, first spacer; 25, first source-drain recess; 26, insulating layer; 27, carrier wafer; 28, second spacer; 29, mask; 30, first recess; 31, isolation layer; 32, interconnect via structure; 33, second recess; 34, first isolation layer; 35, first interconnect via structure; 36, second isolation layer; 37, second interconnect via structure; 38, BOX layer).

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits.

In one embodiment, the fabrication process of the stacked transistor has two schemes, the first is a monolithic scheme and the second is a sequential scheme.

In the first approach, N-channel field effect transistors (N FIELD EFFECT transistors, NFETs) and P-channel field effect transistors (P FIELD EFFECT transistors, PFETs) are fabricated on the same substrate, and substrate bonding techniques are not employed. This determines that the same layer transistors must be of the same type, i.e., NFET or PFET. And the transistors on the upper layer and the lower layer are strictly in the same plane space, and no alignment deviation exists. The advantage of this solution is a better integration density. Drawbacks of this approach include the following two points: (1) The process is complex, and a large number of process technologies need to be developed and optimized; (2) Each layer of transistors has a fixed polarity, and two layers of transistors must be relied upon to form a basic Complementary Metal Oxide Semiconductor (CMOS) circuit, which has poor design flexibility.

The second approach is based on substrate bonding and layer-by-layer processing. Specifically, the two transistors are vertically stacked by bonding a substrate on top of the fabricated lower transistor to prepare an upper transistor. However, this approach requires tight temperature control during the thermal process of processing the upper layer transistors, avoiding affecting the lower layer transistors and the interconnect lines. The scheme has the advantages that the device structure, the channel crystal orientation and even the channel material adopted by the upper layer transistor and the lower layer transistor can be correspondingly optimized to obtain better and more matched device performance due to substrate bonding. This solution currently presents the following technical challenges: (1) preparation of a high-quality upper transistor active layer; (2) thinning and defect control of the upper bonded substrate; (3) The upper and lower layer transistors have alignment errors and have extremely high requirements on photoetching precision.

However, in some schemes for preparing stacked transistors, when forming the field direct structure of the upper and lower transistors, it is necessary to form a new field region outside the original standard cell of the stacked transistor by fin cutting (fin cut), i.e., to add a gate structure, and to form the FDC in the region between the gate structure and the adjacent gate structure, which increases the width of the standard cell by one contact poly pitch (contacted poly pitch, CPP), which is disadvantageous for integration of the stacked transistor and downsizing of the integrated circuit. Where one CPP represents the horizontal length between the left edge (right edge or center) of a gate structure and the left edge (right edge or center) of an adjacent gate structure.

Based on the above-mentioned problems, the embodiments of the present application provide a field direct connection method of stacked transistors, which can effectively improve the integration level of the stacked transistors and the size of the integrated circuit.

In the embodiment of the application, the stacked transistor can be applied to semiconductor devices such as memories, processors and the like.

In an embodiment, the stacked transistor may include at least two transistors, for example, a first transistor and a second transistor, which are stacked, the first transistor being formed based on a first active structure, the second transistor being formed based on a second active structure, and the first active structure and the second active structure being formed through the same process, so it may be understood that the first transistor and the second transistor are self-aligned. Furthermore, the stacked transistor further includes an interconnect via structure fabricated in the double diffusion isolation (doublediffusion break, DDB) region for connecting the first metal interconnect layer of the first transistor with the second metal interconnect layer of the second transistor to enable metal interconnection between the upper and lower layers of transistors.

In an embodiment of the present application, the first transistor and the second transistor in the stacked transistor may be transistors of the same type, and the types of the transistors may include, but are not limited to: a fin field effect transistor (FIN FIELD EFFECT transistor, finFET), a full-around gate transistor (gate-all-around FIELD EFFECT transistor, GAAFET), and a planar transistor (planar transistor), etc.

Fig. 1 is a schematic flow chart of an embodiment of a field direct connection method of a stacked transistor according to the present application, and as shown in fig. 1, the field direct connection method of the stacked transistor includes the following steps.

Step S110: an active structure is formed on a substrate structure.

The active structure comprises a first active structure and a second active structure, and the first active structure is far away from the substrate relative to the second active structure.

In some embodiments, the implementation procedure of step S110 may be: providing a substrate; etching a first portion of the substrate to form an initial active structure; etching the initial active structure of the stacked transistor in the two side areas to form an active structure; an oxide material is deposited over the second portion of the substrate to form a shallow trench isolation (shallow trench isolation, STI) structure having a height that is lower than a height of the active structure.

The substrate may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or the like.

In one embodiment, the SOI substrate comprises a three-layer structure: a thin top silicon (thin top silicon) layer, a Buried Oxide (BOX) layer, and a bottom silicon wafer (base silicon) layer that acts as a support. That is, a BOX layer is disposed between the top silicon and the bottom silicon substrate, and the SOI substrate can realize dielectric isolation of components in the integrated circuit, and eliminate parasitic latch-up in the bulk silicon CMOS circuit. The integrated circuit prepared by the SOI substrate has the advantages of small parasitic capacitance, high integration density, high speed, simple process, small short channel effect, particular suitability for low-voltage and low-power consumption circuits and the like.

In one embodiment, the thickness of the BOX layer in the SOI substrate may range from 10nm to 200nm. It is understood that the thickness of the BOX layer in the SOI substrate may also have other values, as embodiments of the present application are not specifically limited in this regard.

After providing the substrate, a number of initial active structures upstanding from the substrate may be formed on the substrate, with the first portion of the substrate also being etched to form the initial active structures.

In an embodiment, the process of etching the first portion of the substrate to form the initial active structure may be: forming an epitaxial layer on the surface of the substrate through an epitaxial growth process; the epitaxial layer is etched to a depth into the epitaxial layer or to the substrate surface or to a depth into the substrate to form a plurality of initial active structures.

Here, each of the initial active structures includes a first initial active structure and a second initial active structure, the first initial active structure being farther from the substrate than the second initial active structure.

The etching process may be at least one of dry etching, wet etching, reactive ion etching, and the like, for example.

After forming the initial active structure, the initial active structure in the two side regions of the stacked transistor may be etched to form the active structure. And carrying out fin on the initial active structure at the boundary of the standard cell to form a double-diffusion isolation region. The two sides of the active structure are empty, which can isolate the stacked transistor from the adjacent stacked transistor.

Accordingly, the active structure includes a first active structure and a second active structure, the first active structure being further from the substrate than the second active structure.

In the case of a fin field effect transistor, the active structure is a fin structure (fin). In the case of a fully-around gate transistor, the active structure is a nanoplate (nanosheet). In the case of a planar transistor, the active structure is a bulk planar structure.

It can be appreciated that in the embodiment of the present application, since the upper and lower transistors in the stacked transistor share the active structure, that is, the first active structure of the lower transistor and the second active structure of the upper transistor are formed by the same etching process. Because the initial active structure is etched, the operation of forming the active structure is equivalent to only thinning the width of the active structure and not changing the height of the active structure, and therefore, when the initial active structure is formed on the substrate, a larger etching depth can be adopted to obtain an active structure with higher height. For example, the initial active structure resulting from the etching may be made to have a height greater than 100 nanometers (nm).

After forming the active structure, an oxide material may be deposited on the second portion of the substrate and the surface of the active structure to form a shallow trench isolation structure that encapsulates the second active structure.

It will be appreciated that oxide material may be deposited on the surfaces of the substrate and the active structure and a chemical mechanical planarization process may be employed to remove the top surface of the oxide material until the top surface of the active structure is exposed, thereby forming a shallow trench isolation structure having a top surface level with the top surface of the active structure, and further etching back the shallow trench isolation structure to a depth such that the shallow trench isolation structure wraps around the second active structure, exposing the first active structure. This is so as to subsequently perform the operation of forming the first transistor based on the exposed first active structure in step S120.

The oxide material forming the shallow trench isolation structure may be any of the following, for example: silicon nitride (SiN, si3N 4), silicon dioxide (SiO 2), silicon oxycarbide (SiCO), or the like.

Step S120: a first transistor is formed based on the first active structure.

By means of a first one of the active structures, a front-side transistor, i.e. a first transistor, of the stacked transistors can be prepared.

In some embodiments, the implementation procedure of step S120 may be: epitaxially growing a first source-drain structure on the first active structure; forming a first source drain metal on the first source drain structure; a first gate structure is formed based on the first active structure.

It will be appreciated that after the shallow trench isolation structure is formed, semiconductor material may also be deposited in the gate region of a first transistor in the stacked transistors to form a first dummy gate structure; forming first spacers (spacers) on both sides of the first dummy gate structure; and forming a first source drain structure on the first dummy gate structure and the first active structure on two sides of the first spacer.

In an embodiment, the semiconductor material forming the first dummy gate structure may be polysilicon, amorphous silicon, or the like.

The first spacer is used for isolating the first source-drain structure and the first grid structure. The structure of the first spacer may be set according to actual requirements, which is not particularly limited in the embodiment of the present application.

Illustratively, the first spacer may have a single layer structure, and be entirely made of the same material, such as porous carbon silicon oxide (SiCOH).

In some embodiments, the implementation process of forming the first source-drain structure on the first dummy gate structure and the first active structure on both sides of the first spacer may be: etching a first active structure of the first transistor in the source drain region to form a first source drain groove, and performing source drain epitaxial growth at the first source drain groove to form a first source drain structure.

For example, a strained material such as silicon germanium or silicon carbide may be formed in the source-drain recess by selective epitaxial growth to fill the source-drain recess of the first transistor, and then a first source-drain structure may be formed on the strained material by a heavy doping process.

After forming the first source-drain structure, a metal material may be deposited on the first source-drain structure to form a first source-drain metal.

For convenience of explanation, the first source-drain structure in the embodiment of the present application is referred to as simply, and specifically refers to the first source structure and/or the first drain structure. In addition, the first source-drain metal, the first source-drain groove, the second source-drain structure, the second source-drain metal, the second source-drain groove and the like are similar to those of the first source-drain structure, wherein 'source-drain' is abbreviated as 'source electrode and/or drain electrode'.

In some embodiments, after forming the first source-drain structure, an interlayer dielectric may be further deposited on the first source-drain structure, and the interlayer dielectric may be thinned to a top layer of the first source-drain structure, so as to form a first interlayer dielectric layer, and then a first source-drain metal may be formed in the first interlayer dielectric layer.

For example, an insulating material (such as silicon dioxide SiO 2) may be deposited over the first source-drain structure and the first active structure, and planarized to form a first interlayer dielectric layer, which may cover the first source-drain structure and the first active structure.

The planarization process may be, for example, a chemical-mechanical planarization (CMP) process or the like.

It should be noted that, the first source-drain structure, the first source-drain metal and the first interlayer dielectric layer may be formed by standard steps of a semiconductor manufacturing process, which is not limited in particular in the embodiment of the present application.

After the first source-drain metal is formed, a gate structure of the first transistor, i.e., a first gate structure, may be formed.

In some embodiments, the first dummy gate structure formed in the foregoing manner may be removed by an etching process to obtain a first gate recess, an insulating material is deposited in the first gate recess to form a first gate dielectric layer, and a metal material is deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together form a first gate structure, and the first transistor is manufactured.

It should be noted that the first gate structure may be formed by standard steps of the semiconductor manufacturing process, which is not described in detail in the embodiments of the present application.

By way of example, the first gate dielectric layer may be formed of a silicon oxide layer plus a K-value hafnium oxide layer, and the thickness of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

By way of example, the first gate electrode layer may be composed of multiple layers of electrode materials, each layer of electrode material including, but not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

It should be noted that, the two operations of forming the first source drain metal and forming the first gate structure do not distinguish the sequence, that is, the first source drain metal may be formed first and then the first gate structure may be formed first, or the first gate structure may be formed first and then the first source drain metal may be formed first, which is not limited in the embodiment of the present application. The above embodiments are described taking the first source-drain metal and then forming the first gate structure as an example.

In addition, in some embodiments, after the first transistor is completed, a first metal interconnection layer may be further formed on the first transistor.

It will be appreciated that a first metal interconnect layer may be formed by performing subsequent processes (e.g., dielectric deposition between interconnect lines, metal line formation, lead-out pad formation, etc.) on the first transistor.

In some embodiments, the first metal interconnect layer comprises: the first interconnection sub-layer is in direct contact with the first source-drain metal and the first interconnection through hole structure and can be also understood as M0 metal; the second interconnect sublayer is in direct contact with the first interconnect sublayer and can also be understood as the M1 metal.

Step S130: the first transistor is reworked and the substrate is removed to expose the second active structure.

In some embodiments, the implementation procedure of step S130 may be: rewinding the first transistor and removing the substrate; and thinning the shallow trench isolation structure to a preset height so as to expose the second active structure, wherein the thinned shallow trench isolation structure is used for isolating the first transistor and the second transistor.

It is appreciated that after forming the first transistor comprising the first source drain structure, the first source drain metal, the first gate structure, and the first metal interconnect layer, the first transistor is bonded to the carrier wafer. And then, the first transistor is turned over, and the substrate is removed, so that the second active structure is exposed, and the second transistor is conveniently prepared by using the second active structure.

In one embodiment, an insulating material (e.g., silicon oxide) may be deposited over the first metal interconnect layer to form a first insulating layer and bond the first insulating layer to the carrier wafer.

In one embodiment, the substrate may be removed after rewinding using a polishing process or a chemical mechanical planarization process.

After the substrate is removed, the top layer of the second active structure is flush with the top layer of the shallow trench isolation structure, so that the shallow trench isolation structure can be thinned to a preset height, and the peripheral side of the second active structure is exposed, so that a second transistor is formed according to the second active structure exposed on the peripheral side.

The preset height can be set according to actual requirements, which is not limited in the embodiment of the present application.

Step S140: a second transistor is formed based on the second active structure.

After the front-side transistor is reworked, the back-side transistor, i.e. the second transistor, in the stacked transistor may be prepared based on the exposed second active structure.

In some embodiments, the implementation procedure of step S140 may be: epitaxially growing a second source-drain structure on the second active structure; forming a second source-drain metal on the second source-drain structure; a second gate structure is formed based on the second active structure.

In some embodiments, after forming the second source-drain structure, an interlayer dielectric may be further deposited on the second source-drain structure, thinned to a top layer of the second source-drain structure to form a second interlayer dielectric layer, and then a second source-drain metal is formed in the second interlayer dielectric layer.

The preparation methods of the second source-drain structure, the second interlayer dielectric layer, the second source-drain metal and the second gate structure of the second transistor are the same as those of the first source-drain structure, the first interlayer dielectric layer, the first source-drain metal and the first gate structure of the first transistor, and are not described herein again.

It should be noted that, because the second source-drain structure is epitaxially grown based on the second active structure, the first source-drain structure is epitaxially grown based on the first active structure, and the first active structure and the second active structure are self-aligned structures, the second source-drain structure and the first source-drain structure are self-aligned structures, so that symmetry of the stacked transistor structure is effectively improved.

Step S150: the first transistor and the second transistor are etched in the double diffusion isolation region to form a first recess.

Wherein the double diffusion isolation region is used for isolating two adjacent stacked transistors.

In some embodiments, the implementation procedure of step S150 may be: coating photoresist on the upper side of the second transistor to form a photoresist layer, wherein the photoresist layer covers the region except the double diffusion isolation region in the second transistor; and etching the first transistor and the second transistor by taking the photoresist layer as a mask until the first metal interconnection layer to form a first groove.

It can be understood that a photoresist is coated over the second transistor, and after the photoresist is exposed and developed, i.e., a photoresist layer is formed, a notch is formed at a predetermined position, where the notch corresponds to the double diffusion isolation region, and then the first transistor and the second transistor are etched using the photoresist layer as a mask, stopping at the first metal interconnection layer of the first transistor, and forming a first recess.

In some embodiments, the double diffusion isolation region includes a first diffusion isolation region on one side of the stacked transistor and/or a second diffusion isolation region on the other side of the stacked transistor.

Thus, the first recess may be one recess on one side of the stacked transistor, one recess on the other side of the stacked transistor, or two recesses on both sides of the stacked transistor.

Step S160: and filling a metal material in the first groove to form an interconnection through hole structure.

Wherein the interconnection through hole structure is used for connecting the first metal interconnection layer of the first transistor and the second metal interconnection layer of the second transistor

In some embodiments, the implementation procedure of step S160 may be: depositing an isolation material on the inner wall of the first groove to form an isolation layer; and filling a metal material in the first groove to form an interconnection through hole structure, wherein the interconnection through hole structure is isolated from the active structure through an isolation layer.

After forming the first recess, the previous mask may be removed and then an isolation material may be deposited on the inner wall of the first recess to form an isolation layer (liner) for protecting the metal material in the first recess from contact with the silicon material of the active structure. And then etching to remove the isolation layer at the bottom of the first groove. And then filling a metal material in the first groove to form an interconnection through hole structure.

The isolation material may be, for example, an insulating material such as silicon nitride (SiN) or silicon oxide (SiOx).

It should be noted that, in the embodiment of the present application, when the interconnect via structure is directly etched from the back, there are three etching methods, where the first etching method etches the first diffusion isolation region located at one side of the stacked transistor to obtain an interconnect via structure; etching a second diffusion isolation region on the other side of the stacked transistor to obtain an interconnection through hole structure; and thirdly, etching the first diffusion isolation region and the second diffusion isolation region which are positioned at two sides of the stacked transistor to obtain two interconnection through hole structures.

After forming the interconnect via structure, a second metal interconnect layer may be formed over the second transistor and the interconnect via structure.

The implementation process of forming the second metal interconnection layer may refer to the related content of forming the first transistor on the first transistor in step S120, which is not described herein.

It is understood that the first metal interconnect layer may be directly connected to the second metal interconnect layer by an interconnect via structure within the double diffusion isolation region.

In the above solution, the interconnect via structure is directly etched at the back side transistor, in some embodiments, interconnect via structures may be formed on both the front side transistor and the back side transistor, and the metal interconnect layer of the front side transistor and the metal interconnect layer of the back side transistor are connected through the interconnect via structures on the front side and the back side, which is described below:

In some embodiments, after the first transistor is formed in step S120, the first transistor may be further etched in the double diffusion isolation region to form a second recess; and filling metal materials in the second grooves to form the first interconnection through hole structure.

In some embodiments, the process of etching the first transistor in the double diffusion isolation region to form the second recess may be: coating photoresist on the upper side of the first transistor to form a photoresist layer, wherein the photoresist layer covers the region except the double diffusion isolation region in the first transistor; and etching the first transistor until the shallow trench isolation structure by taking the photoresist layer as a mask so as to form a second groove.

It can be understood that the photoresist is coated above the first transistor, and after the photoresist is exposed and developed, that is, after the photoresist layer is formed, a notch at a preset position is formed, the notch corresponds to the double diffusion isolation region, and then the photoresist layer is used as a mask to etch the first transistor, and stop at the shallow trench isolation structure to form the second groove.

The second groove may be one groove located at one side of the stacked transistor, one groove located at the other side of the stacked transistor, or two grooves located at two sides of the stacked transistor.

After the second recess is formed, a metal material is filled in the second recess to form a first interconnect via structure. In the implementation process of forming the first interconnection via structure, reference may be made to the step S160 of filling the metal material in the first groove to form the interconnection via structure, which is not described herein.

After forming the first interconnect via structure, a first metal interconnect layer may be formed over the first transistor and the first interconnect via structure.

In some embodiments, after forming the second transistor in step S140, the second transistor may be further etched in the double diffusion isolation region to form a third recess; and filling a metal material in the third groove to form a second interconnection through hole structure, wherein the first interconnection through hole structure and the second interconnection through hole structure form an interconnection through hole structure.

In some embodiments, the process of etching the second transistor in the double diffusion isolation region to form the third recess may be: coating photoresist on the upper side of the second transistor to form a photoresist layer, wherein the photoresist layer covers the region except the double diffusion isolation region in the second transistor; and etching the second transistor until the first interconnection through hole structure by taking the photoresist layer as a mask so as to form a third groove.

It can be understood that a photoresist is coated over the second transistor, and after the photoresist is exposed and developed, i.e., the photoresist layer is formed, a notch is formed at a predetermined position, where the notch corresponds to the double diffusion isolation region, and then the second transistor is etched using the photoresist layer as a mask, stopping at the first interconnect via structure, and forming a third recess.

The third groove may be one groove located at one side of the stacked transistor, one groove located at the other side of the stacked transistor, or two grooves located at two sides of the stacked transistor.

After forming the third recess, filling a metal material in the third recess to form a second interconnection via structure. Wherein the first and second interconnect via structures constitute an interconnect via structure. The implementation process of forming the second interconnection via structure may refer to filling the metal material in the first groove in step S160 to form the interconnection via structure, which is not described herein.

After forming the second interconnection via structure, a second metal interconnection layer may be formed on the second transistor and the second interconnection via structure. In this way, the first metal interconnect layer can be directly connected to the second metal interconnect layer by the first interconnect via structure and the second interconnect via structure communicating within the double diffusion isolation region.

The following describes a field direct connection method of a stacked transistor according to an embodiment of the present application, taking an active structure in the stacked transistor as a fin structure as an example. Fig. 2 is a schematic top view of a stacked transistor according to an embodiment of the application. For ease of understanding, only fin structures, gate structures, source-drain structures, M0 metal in the metal interconnect layer, one-sided interconnect via structures, fin cut regions, and cell boundary regions (cell boundary) are shown in top view. Fig. 3 to 17 are schematic views illustrating a first process of manufacturing a stacked transistor according to an embodiment of the present application, and fig. 18 is a schematic view illustrating a first structure of the stacked transistor according to an embodiment of the present application. Wherein (a) in fig. 3 to 18 is a cross-sectional view along a cross-sectional direction (i.e., A-A 'direction) of the interconnect via structure, and (B) in fig. 3 to 18 is a cross-sectional view along a cross-sectional direction (i.e., B-B' direction) of the fin structure.

In one example, the first fabrication process of stacked transistor 10 may include the steps of:

The first step: the fin formation is completed on the substrate 20 by standard methods, forming the initial fin structure 21, resulting in the structure shown in fig. 3.

And a second step of: for the structure shown in fig. 3, the initial fin structure 21 at the boundary of the stacked transistor cell is fin cut to form fin structure 210, resulting in the structure shown in fig. 4.

It can be appreciated that the initial fin structure at the cell boundary is etched to form DDB isolation. As shown in fig. 4, the broken lines on the left and right sides in fig. 4 indicate boundaries of the stacked transistor cells, and fin structures on the boundaries on both sides of the stacked transistor are empty, so that the stacked transistor can be isolated from the adjacent stacked transistor.

And a third step of: for the structure shown in fig. 4, filling and etching back of the shallow trench isolation structure 22 is performed to obtain the structure shown in fig. 5.

Here, the shallow trench isolation structure 22 wraps around a portion of the fin structure close to the substrate 20, i.e., the second fin structure 121 (second active structure), exposing a portion of the fin structure away from the substrate 20, i.e., the first fin structure 111 (first active structure).

Fourth step: polysilicon material is deposited in the gate region on the substrate shown in fig. 5 to form a first dummy gate structure 23, and a first spacer 24 is formed on the sidewall of the first dummy gate structure 23, and the first active structure at the source drain region is etched to a predetermined height to form a first source drain recess 25 in the source drain region, resulting in the structure shown in fig. 6.

Fifth step: a first source-drain structure 112 is formed at the first source-drain recess 25, and an interlayer dielectric is deposited on the first source-drain structure 112 to form a first interlayer dielectric layer 113, resulting in the structure shown in fig. 7.

Sixth step: the first dummy gate structure 23 is removed and a first gate structure 114 is formed in the gate region, resulting in the structure shown in fig. 8.

Seventh step: a first source drain metal 115 is formed over the first source drain structure 112 resulting in the structure shown in fig. 9.

It can be appreciated that the first interlayer dielectric layer 113 on the first source drain structure 112 is etched, and the etched recess is filled with a metal material, so as to form the first source drain metal 115.

Eighth step: the subsequent processing of the front-side transistor is completed on the structure shown in fig. 9, forming a first metal interconnect layer 116, resulting in the structure shown in fig. 10.

It will be appreciated that the first metal interconnect layer may be formed by performing a subsequent process (e.g., dielectric deposition between interconnect lines, metal line formation, lead-out pad formation, etc.) on the front-side transistor.

Ninth step: oxide is deposited over the structure shown in fig. 10 to form an insulating layer 26, and a carrier wafer 27 is bonded to insulating layer 26 over insulating layer 26 and then reworked to yield the structure shown in fig. 11.

Tenth step: the substrate 20 in the structure shown in fig. 11 is removed using a chemical mechanical planarization process, eventually stopping at the shallow trench isolation structure 22, resulting in the structure shown in fig. 12.

Eleventh step: etching the shallow trench isolation structure 22 shown in fig. 12 to a depth to expose the second fin structure 121 (second active structure); based on the second fin structure, the second spacer 28, the second source-drain structure 122, the second interlayer dielectric layer 123, the second gate structure 124, and the second source-drain metal 125 are formed by the same process as in the fourth to sixth steps, resulting in the structure shown in fig. 13.

Twelfth step: the FDC layer photoresist is deposited as a mask 29 resulting in the structure shown in fig. 14.

Wherein the mask in fig. 14 exposes the diffusion isolation region on the right side of the stacked transistor, alternatively the mask may also expose the diffusion isolation region on the left side of the stacked transistor. FDCs are also known as interconnect via structures.

Thirteenth step: under the protection of the FDC layer mask 29, the underlying material is etched, stopping at the first metal interconnect layer (VG) of the front side transistor 11, forming openings for the FDC, i.e. forming the first recess 30, resulting in the structure shown in fig. 15.

Fourteenth step: mask 29 is removed and a thin layer of insulating material is deposited on the inner walls of first recess 30 as a spacer 31 (liner) to protect the metal material in the FDC from contact with the silicon material in the fin structure, and then the bottom spacer is etched away to obtain the structure shown in fig. 16.

Fifteenth step: a metal material is deposited into the first recess 30 (FDC opening) to form an interconnect via structure 32, resulting in the structure shown in fig. 17.

Sixteenth step: a back side transistor back interconnect is completed over the structure shown in fig. 17, forming a second metal interconnect layer 126, resulting in the structure shown in fig. 18.

Thus, a first structure of the completed stacked transistor is prepared.

It follows that the first metal interconnect layer 116 of the front side transistor 11 may be directly connected to the second metal interconnect layer 126 of the back side transistor 12, in particular the M0 metal in the first metal interconnect layer 116 may be connected to the M0 metal in the second metal interconnect layer 126, by the interconnect via structure 32 in the double diffusion isolation region. Since (b) in fig. 18 is a cross-sectional view along the cross-sectional direction of the fin structure, the M0 metal in the first metal interconnect layer 116 and the M0 metal in the second metal interconnect layer 126 cannot be seen in (b), and if it is a cross-sectional view along the cross-sectional direction of the M0 metal of the metal interconnect layer, it can be seen that the M0 metal in the first metal interconnect layer 116 is connected with the M0 metal in the second metal interconnect layer 126.

In the first structure described above, the interconnect via structure is an interconnect via structure located in the right side region of the stacked transistor, alternatively, may be an interconnect via structure located in the left side region of the stacked transistor.

Fig. 19 to 28 are schematic views illustrating a second process of manufacturing a stacked transistor according to an embodiment of the present application, and fig. 29 is a schematic view illustrating a second structure of the stacked transistor according to an embodiment of the present application. Here, (a) in fig. 19 to 29 is a sectional view along a sectional direction (i.e., A-A 'direction) of the interconnect via structure, and (B) in fig. 19 to 29 is a sectional view along a sectional direction (i.e., B-B' direction) of the fin structure.

In one example, the second fabrication process of stacked transistor 10 may include the steps of:

The first step: the same process as in the first to seventh steps of the first preparation process was employed to obtain the structure shown in fig. 19.

Eighth step: the FDC layer photoresist is deposited as a mask 29 to yield the structure shown in fig. 20.

Wherein the mask in fig. 20 exposes the diffusion isolation region on the right side of the stacked transistor, alternatively the mask may also expose the diffusion isolation region on the left side of the stacked transistor. FDCs are also known as interconnect via structures.

Ninth step: under the protection of the FDC layer mask 29, the underlying material is etched, stopping at the shallow trench isolation structure 22, forming openings for FDC in the front side transistor 11, i.e. forming the second recess 33, resulting in the structure shown in fig. 21.

Tenth step: the mask 29 is removed and a thin layer of insulating material is deposited on the inner walls of the second recess 33 as a first isolation layer 34 (liner) protecting the metal material in the FDC from contact with the silicon material in the fin structure. The bottom spacer is then etched away, resulting in the structure shown in fig. 22.

Eleventh step: a metal material is deposited into the second recess 33 (FDC opening) to form a first interconnect via structure 35, i.e., FDC front side partial molding, resulting in the structure shown in fig. 23.

Twelfth step: the subsequent interconnection of the front side transistor 11 is completed on the structure shown in fig. 23, forming a first metal interconnection layer 116, resulting in the structure shown in fig. 24.

Thirteenth step: oxide is deposited over the structure shown in fig. 24 to form an insulating layer 26, and a carrier wafer 27 is bonded to insulating layer 26 over insulating layer 26 and then reworked to yield the structure shown in fig. 25.

Fourteenth step: the substrate 20 in the structure shown in fig. 25 is removed using a chemical mechanical planarization process, eventually stopping at the shallow trench isolation structure 22, resulting in the structure shown in fig. 26.

Fifteenth step: etching the shallow trench isolation structure 22 shown in fig. 26 to a depth to expose the second fin structure 121 (second active structure); based on the second fin structure, the second spacer 28, the second source-drain structure 122, the second interlayer dielectric layer 123, the second gate structure 124 and the second source-drain metal 125 are formed by the same process as the fourth to sixth steps in the first manufacturing process, resulting in the structure shown in fig. 27.

Sixteenth step: the second spacer 36 and the second interconnect via structure 37 are fabricated on the back side using the same process, resulting in the structure shown in fig. 28.

It will be appreciated that the second interconnect via structure 37 communicates with the first interconnect via structure 35.

Seventeenth step: the subsequent interconnection of the back side transistor 12 is completed on the structure of fig. 28, forming a second metal interconnect layer 126, resulting in the structure shown in fig. 29.

Thus, a second structure of the completed stacked transistor is prepared.

In the second structure described above, the first interconnect via structure and the second interconnect via structure are one interconnect via structure that is located in the right region of the stacked transistor and communicates up and down, or alternatively, one interconnect via structure that is located in the left region of the stacked transistor and communicates up and down.

In the above two preparation schemes, the interconnection through hole structure is formed in the diffusion isolation region at one side of the stacked transistor, that is, only one interconnection through hole structure is formed at one side of the stacked transistor.

Fig. 30 is a schematic top view of another stacked transistor according to an embodiment of the present application. For ease of understanding, only fin structures, gate structures, source-drain structures, M0 metal in the metal interconnect layer, two-sided interconnect via structures, fin cut regions, and cell boundary regions (cell boundary) are shown in top view. Fig. 31 is a schematic diagram of a third structure of a stacked transistor according to an embodiment of the present application; fig. 32 is a schematic diagram of a fourth structure of a stacked transistor in an embodiment of the application. Here, (a) in fig. 31 to 32 is a cross-sectional view along a cross-sectional direction (i.e., A-A 'direction) of the interconnect via structure, and (B) in fig. 31 to 32 is a cross-sectional view along a cross-sectional direction (i.e., B-B' direction) of the fin structure.

Next, a third structure of the stacked transistor will be described, referring to the method for manufacturing the first structure, unlike the method for manufacturing the first structure, in the twelfth step, the mask 29 exposes the double diffusion isolation regions on both sides of the stacked transistor, so that the first recess 30 and the interconnect via structure 32 in the subsequent step each include two structures on both sides of the stacked transistor, resulting in the structure shown in fig. 31.

Next, a fourth structure of the stacked transistor will be described, referring to the method of manufacturing the second structure described above, unlike the method of manufacturing the second structure, the mask 29 exposes the double diffusion isolation regions on both sides of the stacked transistor in the second and tenth steps, so that the second recess 33, the first interconnect via structure 35, the third recess 26, and the second interconnect via structure 27 in the subsequent steps each include two structures on both sides of the stacked transistor, resulting in the structure shown in fig. 32.

In addition, the embodiment of the application also provides a stacked transistor taking the SOI as the substrate. Fig. 33 is a schematic diagram of a fifth structure of a stacked transistor in an embodiment of the application. The structure shown in fig. 33 is a structure of a stacked transistor obtained by the above-described manufacturing method of the second structure, and as shown in fig. 33, in the case where an SOI substrate is used as the substrate, the intermediate BOX layer 38 can be seen as an isolation structure between the front-side transistor and the back-side transistor.

In addition, in some embodiments, embodiments of the present application may also isolate the front side transistor from the back side transistor by an intermediate dielectric isolation (MIDDLEDIELECTRIC ISOLATION, MDI) layer located between the front side transistor and the back side transistor. Referring to the above-described method for manufacturing the second structure, unlike the method for manufacturing the second structure, when the initial fin structure 21 is formed in the first step, a first material and a second material may be sequentially deposited on the substrate 20 to form a first material layer and a second material layer; the second material layer, the first material layer, and a portion of the substrate 20 are etched to form an initial fin structure, the etched first material layer may serve as a sacrificial layer, and the etched second material layer forms a portion of the initial fin structure away from the substrate, so that the initial fin structure 21 includes the etched second material layer (initial first fin structure), the first material layer (sacrificial layer), and a portion of the substrate (initial second fin structure). After the first source-drain structure is formed in the fifth step, the sacrificial layer may be removed, and the recess formed after the sacrificial layer is removed may be filled with an isolation material to form an intermediate dielectric isolation (MIDDLEDIELECTRIC ISOLATION, MDI) layer, and then the remaining steps may be continued. Thus, the MDI layer may act as an isolation structure between the front side transistor and the back side transistor. The MDI layer of the stacked transistor formed based on this manufacturing method may be, for example, the BOX layer in fig. 33.

The isolation material forming the MDI layer may be, for example, a low-K gate dielectric (low-K DIELECTRIC, lowK), or may be another type of isolation material, which is not limited in this embodiment of the present application.

In an example, the first material may be a silicon germanium (SiGe) material and the second material may be a silicon material, i.e., the first fin structure and the second fin structure may be formed of a silicon material and the sacrificial layer may be formed of a silicon germanium material.

The following describes a stacked transistor provided in the embodiment of the present application by taking an active structure in the stacked transistor as a nano-sheet as an example. Fig. 34 is a schematic diagram of a sixth structure of a stacked transistor in an embodiment of the application. The A-A 'direction in fig. 34 is the tangential direction along the interconnect via structure and the B-B' direction is the tangential direction along the nanoplatelets. In fig. 34, fig. 34 (a) is a top view of the stacked transistor, and only the nanoplatelets, the gate structure, the source-drain structure, the M0 metal of the metal interconnect layer, the interconnect via structures on both sides, the fin cut region, and the cell boundary region (cell boundary) are shown in the top view for easy understanding. Fig. 2 (B) is a cross-sectional view of the stacked transistor in the A-A 'direction, and fig. 2 (c) is a cross-sectional view of the stacked transistor in the B-B' direction. The structure shown in fig. 34 is a structure of a stacked transistor obtained by the above-described method for manufacturing the second structure.

Further, the stacked transistor provided by the embodiment of the application can be detected by using a detection analysis instrument, for example: scanning electron microscope (scanning electron microscope, SEM), transmission electron microscope (transmission electron microscope, TEM), scanning transmission electron microscope (scanning transmission electron microscopy, STEM), and the like. Taking TEM as an example, the embodiment of the present application may detect the structure of the stacked transistor by using a TEM section.

An embodiment of the present application provides a semiconductor device including: stacked transistors as in the above embodiments. For specific limitation of the stacked transistor, reference may be made to the above stacked transistor, and detailed description thereof is omitted herein.

An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device includes the above-described stacked transistor. For specific limitation of the stacked transistor, reference may be made to the above stacked transistor, and detailed description thereof is omitted herein.

In the description of the embodiments of the present application, the descriptions of the terms "one embodiment," "an example," "a particular example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A field direct connection method of stacked transistors, comprising:

forming an active structure on a substrate, the active structure comprising a first active structure and a second active structure, the first active structure being remote from the substrate relative to the second active structure;

forming a first transistor based on the first active structure;

rewinding the first transistor and removing the substrate to expose the second active structure;

forming a second transistor based on the second active structure;

etching the first transistor and the second transistor in a double-diffusion isolation region to form a first groove, wherein the double-diffusion isolation region is used for isolating two adjacent stacked transistors;

and filling a metal material in the first groove to form an interconnection through hole structure, wherein the interconnection through hole structure is used for connecting the first metal interconnection layer of the first transistor and the second metal interconnection layer of the second transistor.

2. The method of claim 1, wherein after the forming a first transistor based on the first active structure, the method further comprises:

Forming the first metal interconnection layer on the first transistor;

The etching the first transistor and the second transistor in the double diffusion isolation region to form a first groove comprises:

coating photoresist above the second transistor to form a photoresist layer, wherein the photoresist layer covers the area except the double diffusion isolation area in the second transistor;

And etching the first transistor and the second transistor by taking the photoresist layer as a mask until the first metal interconnection layer so as to form the first groove.

3. The method of claim 1, wherein after the forming a first transistor based on the first active structure, the method further comprises:

Etching the first transistor in the double-diffusion isolation region to form a second groove;

filling a metal material in the second groove to form a first interconnection through hole structure;

after the forming a second transistor based on the second active structure, the method further comprises:

etching the second transistor in the double-diffusion isolation region to form a third groove;

And filling a metal material in the third groove to form a second interconnection through hole structure, wherein the first interconnection through hole structure and the second interconnection through hole structure form the interconnection through hole structure.

4. The method of claim 3, wherein said etching the first transistor within the double diffusion isolation region to form a second recess comprises:

coating photoresist above the first transistor to form a photoresist layer, wherein the photoresist layer covers the area except the double diffusion isolation area in the first transistor;

Etching the first transistor until a shallow trench isolation structure is formed by taking the photoresist layer as a mask to form the second groove, wherein the shallow trench isolation structure is positioned at two sides of the active structure to isolate the first transistor and the second transistor;

the etching the second transistor in the double diffusion isolation region to form a third groove comprises:

and etching the second transistor by taking the photoresist layer as a mask until the first interconnection through hole structure so as to form the third groove.

5. The method of any of claims 1 to 4, wherein the double diffusion isolation region comprises a first diffusion isolation region on one side of the stacked transistor and/or a second diffusion isolation region on the other side of the stacked transistor.

6. The method of claim 1, wherein filling the first recess with a metal material to form an interconnect via structure comprises:

Depositing an isolation material on the inner wall of the first groove to form an isolation layer;

and filling a metal material in the first groove to form the interconnection through hole structure, wherein the interconnection through hole structure is isolated from the active structure through the isolation layer.

7. The method of claim 1, wherein forming a first transistor based on the first active structure comprises:

epitaxially growing a first source-drain structure on the first active structure;

forming a first source drain metal on the first source drain structure;

forming a first gate structure based on the first active structure;

the forming a second transistor based on the second active structure includes:

epitaxially growing a second source-drain structure on the second active structure;

Forming a second source-drain metal on the second source-drain structure;

and forming a second gate structure based on the second active structure.

8. The method of claim 1, wherein the forming an active structure on a substrate, the method further comprising:

Providing a substrate;

etching the first part of the substrate to form an initial active structure;

etching the initial active structure of the stacked transistor in the two side areas to form the active structure;

An oxide material is deposited on the second portion of the substrate to form a shallow trench isolation structure having a height that is lower than a height of the active structure.

9. The method of claim 8, wherein the rewinding the first transistor and removing the substrate to expose the second active structure comprises:

rewinding the first transistor and removing the substrate;

And thinning the shallow trench isolation structure to a preset height so as to expose the second active structure, wherein the thinned shallow trench isolation structure is used for isolating the first transistor and the second transistor.

10. A stacked transistor prepared using the method of any one of claims 1 to 9, comprising:

a first transistor;

a second transistor, the first transistor and the second transistor being arranged in opposition;

The first active structure of the first transistor and the second active structure of the second transistor form an active structure, an interconnection through hole structure is formed in the double-diffusion isolation region of the first transistor and the double-diffusion isolation region of the second transistor, and the first metal interconnection layer of the first transistor and the second metal interconnection layer of the second transistor are connected through the interconnection through hole structure.

11. A semiconductor device, comprising: the stacked transistor of claim 10.