CN118299331A

CN118299331A - Preparation method of stacked fork plate transistor, stacked fork plate transistor and device

Info

Publication number: CN118299331A
Application number: CN202410248616.4A
Authority: CN
Inventors: 吴恒; 刘煜; 卢浩然; 葛延栋; 王润声; 黎明; 黄如
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2024-03-05
Filing date: 2024-03-05
Publication date: 2024-07-05

Abstract

The application provides a preparation method of a stacked fork plate transistor, the stacked fork plate transistor and a device, wherein the method comprises the following steps: forming an active structure on a substrate; the active structure comprises a front active structure and a back active structure; forming a front-side transistor based on the front-side active structure; rewinding and removing the substrate; forming a back side transistor based on the back side active structure; the front side transistor and the back side transistor are self-aligned; the dielectric fork plate structure of the stacked fork plate transistor penetrates through the front active structure and the back active structure, the front active structure is divided into two parts which are symmetrically arranged by the dielectric fork plate structure, the back active structure is divided into two parts which are symmetrically arranged by the dielectric fork plate structure, the dielectric fork plate structure is formed by non-uniform deposition, and an air gap is formed inside the dielectric fork plate structure. The application can effectively reduce the capacitance.

Description

Preparation method of stacked fork plate transistor, stacked fork plate transistor and device

Technical Field

The present application relates to the field of semiconductors, and in particular, to a method for manufacturing a stacked fork transistor, and a device.

Background

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors further increase transistor integration density by integrating two or more layers of transistors in vertical space is one of the important technologies continuing the scaling of integrated circuits.

When the fork plate transistor is prepared by adopting the traditional monolithic scheme, the following technical difficulties exist: since the dielectric layer in the fork-plate transistor is typically filled with nitride, its k value is relatively large, which introduces additional capacitance.

Disclosure of Invention

The application provides a preparation method of a stacked fork plate transistor, the stacked fork plate transistor and a device, so that capacitance is effectively reduced.

In a first aspect, an embodiment of the present application provides a method for manufacturing a stacked fork plate transistor, where the method includes: forming an active structure on a substrate; the active structure comprises a front active structure and a back active structure; forming a front-side transistor based on the front-side active structure; rewinding and removing the substrate; forming a back side transistor based on the back side active structure; the front side transistor and the back side transistor are self-aligned; the dielectric fork plate structure of the stacked fork plate transistor penetrates through the front active structure and the back active structure, the front active structure is divided into two parts which are symmetrically arranged by the dielectric fork plate structure, the back active structure is divided into two parts which are symmetrically arranged by the dielectric fork plate structure, the dielectric fork plate structure is formed by non-uniform deposition, and an air gap is formed inside the dielectric fork plate structure.

In some possible embodiments, forming an active structure on a substrate includes: depositing semiconductor material in a first region on a substrate to form a pair of oppositely disposed first sidewall structures; a space is arranged between the pair of first side wall structures; etching the substrate by taking the first side wall structure as a mask to form a first groove; non-uniformly depositing a dielectric material in the first recess to form a dielectric fork plate structure having an air gap; the substrates are symmetrically arranged at two sides of the medium fork plate structure; removing the first side wall structure, and depositing a semiconductor material in a second area on the substrate to form a second side wall structure; the second side wall structure covers the surface of the dielectric fork plate structure and part of the surface of the substrate positioned on two sides of the dielectric fork plate structure; and etching the substrate by taking the second side wall structure as a mask to form a front active structure and a back active structure.

In some possible embodiments, forming a front-side transistor based on the front-side active structure includes: forming a front dummy gate structure, a front spacer, a front source drain structure and a front interlayer dielectric layer of the front transistor in sequence based on the front active structure; removing the front side dummy gate structure to expose a front side gate region of the front side transistor; depositing an isolation material in a first portion of the front gate region to form a front gate isolation structure; the front grid isolation structure corresponds to the dielectric fork plate structure; depositing a metal material in the front gate region except for the first portion to form a front gate structure; the front grid electrode structures are symmetrically arranged on two sides of the front grid electrode isolation structure; and performing a subsequent process on the front-side interlayer dielectric layer to form a front-side metal interconnection layer of the front-side transistor.

In some possible embodiments, forming a back side transistor based on a back side active structure includes: forming a back dummy gate structure, a back spacer, a back source drain structure and a back interlayer dielectric layer of the back transistor in sequence based on the back active structure; removing the back dummy gate structure to expose a back gate region of the back transistor; depositing an isolation material in a second portion of the back gate region to form a back gate isolation structure; the back grid isolation structure corresponds to the dielectric fork plate structure; depositing a metal material in the back gate region except for the second portion to form a back gate structure; the back grid electrode structures are symmetrically arranged on two sides of the back grid electrode isolation structure; and performing a back-end process on the back-end interlayer dielectric layer to form a back-end metal interconnection layer of the back-end transistor.

In some possible embodiments, forming an active structure on a substrate includes: depositing a semiconductor material in a third region on the substrate to form a third side wall structure; the third side wall structure covers a part of the surface of the substrate; and etching the substrate by taking the third side wall structure as a mask to form a front active structure and a back active structure.

In some possible embodiments, forming a front-side transistor based on the front-side active structure includes: forming a front dummy gate structure, a front spacer, a front source drain structure and a front interlayer dielectric layer of the front transistor in sequence based on the front active structure; removing the front side dummy gate structure to expose a front side gate region of the front side transistor; depositing a metal material in the front gate region to form a front gate structure; and performing a subsequent process on the front-side interlayer dielectric layer to form a front-side metal interconnection layer of the front-side transistor.

In some possible embodiments, forming a back side transistor based on a back side active structure includes: forming a back dummy gate structure, a back spacer, a back source drain structure and a back interlayer dielectric layer of the back transistor in sequence based on the back active structure; sequentially etching the back interlayer dielectric layer, the back active structure, the front active structure and the front interlayer dielectric layer to form a second groove; the second groove divides the front active structure into two parts which are symmetrically arranged, and the second groove divides the back active structure into two parts which are symmetrically arranged; non-uniformly depositing a dielectric material in the second recess to form a dielectric fork plate structure having an air gap; removing the back dummy gate structure to expose a back gate region of the back transistor; depositing a metal material in the back gate region to form a back gate structure; and performing a back-end process on the back-end interlayer dielectric layer to form a back-end metal interconnection layer of the back-end transistor.

In some possible embodiments, the substrate includes a top substrate, an intermediate sacrificial layer, and a bottom substrate, stacked in order, the top substrate for forming the front-side active structure, the bottom substrate for forming the back-side active structure; before forming the front-side transistor based on the front-side active structure, the method further comprises: depositing an insulating material on the substrate to form a shallow trench isolation structure; the shallow slot isolation structure wraps the front active structure, the middle sacrificial layer and the back active structure; a portion of the shallow trench isolation structure surrounding the front-side active structure is removed to expose the front-side active structure.

In some possible embodiments, the above method further comprises: removing the intermediate sacrificial layer to form a third groove; depositing an insulating material in the third recess to form an intermediate isolation layer; the intermediate isolation layer is used for isolating the front-side active structure and the back-side active structure.

In a second aspect, an embodiment of the present application provides a stacked fork plate transistor, including: a front side transistor; a back side transistor; the front side transistor and the back side transistor are self-aligned; a dielectric fork plate structure; the dielectric fork plate structure penetrates through the front active structure of the front transistor and the back active structure of the back transistor, the front active structure is divided into two parts which are symmetrically arranged by the dielectric fork plate structure, the back active structure is divided into two parts which are symmetrically arranged by the dielectric fork plate structure, the dielectric fork plate structure is formed by adopting non-uniform deposition, and an air gap is formed inside the dielectric fork plate structure.

In some possible embodiments, the stacked fork plate transistor further comprises: a front gate isolation structure; the front grid isolation structures are arranged on the surface, far away from the back transistor, of the dielectric fork plate structure, and the front grid structures of the front transistors are symmetrically arranged on two sides of the front grid isolation structures; a back gate isolation structure; the back grid isolation structures are arranged on the surface, far away from the front side transistors, of the dielectric fork plate structures, and the back grid structures of the back side transistors are symmetrically arranged on two sides of the back grid isolation structures.

In some possible embodiments, the dielectric fork plate structure penetrates through the front gate structure of the front-side transistor, and the front gate structure is symmetrically arranged at two sides of the dielectric fork plate structure; the dielectric fork plate structure penetrates through the back grid electrode structure of the back transistor, and the back grid electrode structure is symmetrically arranged on two sides of the dielectric fork plate structure.

In a third aspect, an embodiment of the present application provides a semiconductor device including: stacked fork plate transistors as in the above embodiments.

In a fourth aspect, an embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board.

In the application, the dielectric fork plate structure with the air gap is arranged in the front active structure and the back active structure, so that the capacitance can be effectively reduced.

Further, the capacitor is reduced, so that the circuit speed is improved, the delay is reduced, and the circuit performance is improved.

Further, the combination of the stacked transistor and the fork plate transistor can reduce the space between the symmetrically placed devices on two sides of the dielectric fork plate structure, and improve the integration density of the transistor.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic flow chart of a method for manufacturing a stacked fork-plate transistor according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a first structure of a stacked fork-plate transistor according to an embodiment of the present application;

FIGS. 3A-3D are schematic diagrams illustrating a first process for fabricating a stacked fork plate transistor according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a second structure of a stacked fork plate transistor according to an embodiment of the present application;

FIGS. 5A and 5B are schematic diagrams illustrating a second process for fabricating a stacked fork plate transistor in accordance with an embodiment of the present application;

The figures above:

10. Stacking fork plate transistors; 11. a front side transistor; 111. a front-side active structure; 112. a front spacer; 113. a front source drain structure; 114. a front interlayer dielectric layer; 115. a front side gate dielectric layer; 116. a front gate structure; 117. a front side metal interconnect layer; 12. a back side transistor; 121. a back active structure; 122. a back spacer; 123. a back source drain structure; 124. a back interlayer dielectric layer; 125. a back gate dielectric layer; 126. a back gate structure; 127. a backside metal interconnect layer; 13. an insulating layer; 14. a carrier wafer; 21. a substrate; 211. a base substrate; 212. an intermediate sacrificial layer; 213. a top substrate; 22. a first side wall structure; 23. a first groove; 24. a dielectric fork plate structure; 25. an air gap; 26. a second side wall structure; 27. shallow trench isolation structure; 271. shallow groove isolation layer; 311. a front dummy gate structure; 312. a back dummy gate structure; 32. a third groove; 33. an intermediate isolation layer; 341. a front inner side wall; 342. a back inner wall; 411. a front gate isolation structure; 412. a back gate isolation structure; 51. a third side wall structure; 52. and a second groove.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.

Currently, a certain separation distance must be maintained between two types of transistors, namely an N-type metal oxide semiconductor (NMOS) and a P-type metal oxide semiconductor (PMOS), which constitute Complementary Metal Oxide Semiconductor (CMOS) logic, to limit capacitance that impairs device performance and affects power consumption, and to reduce interference between adjacent transistors. This spacing limits the scaling of nanoplatelet-based logic. Fork plate transistors (forksheet) are one way to break this limitation, and forksheet is constructed by placing transistors in pairs on either side of a dielectric wall (DIELECTRIC WALL).

However, forksheet is fabricated based on a monolithic scheme, the polarity of the transistors is single, the upper layer transistor and the lower layer transistor cannot be optimized respectively, when the number of the transistors stacked on a single chip is large, the problem of thermal budget and compatibility of the CMOS process also need to be considered, and if a new process is developed, the complexity of the fabrication process is increased.

In addition, the dielectric layer forksheet is typically filled with nitride, which has a relatively large k value, and introduces additional capacitance.

In order to solve the above technical problems, an embodiment of the present application provides a method for manufacturing a stacked fork plate transistor, so as to effectively reduce capacitance.

In the embodiment of the application, the stacked fork plate transistor can be applied to semiconductor devices such as memories, processors and the like.

In some embodiments, the stacked fork plate transistors may include a front side transistor and a back side transistor. The stacked fork plate transistor comprises a dielectric fork plate structure, wherein the dielectric fork plate structure penetrates through a front active structure of the front transistor, the front active structure of the front transistor is divided into two symmetrical parts, and similarly, the dielectric fork plate structure penetrates through a back active structure of the back transistor, and the back active structure of the back transistor is divided into two symmetrical parts. The dielectric fork plate structure is formed by non-uniformly depositing a dielectric material, and an air gap is formed inside the dielectric fork plate structure to reduce capacitance.

In some embodiments, since the dielectric fork plate structure penetrates through the front active structure of the front transistor, which is equivalent to penetrating through the active region of the front transistor, the active region of the front transistor is divided into two parts symmetrically disposed at two sides of the dielectric fork plate structure, and due to the separation of the active regions, the front transistor can be divided into two symmetrical transistors, such as a first front transistor and a second front transistor. Likewise, the back side transistor may be divided into two symmetrical transistors, such as a first back side transistor and a second back side transistor.

In the embodiment of the application, the active region is a combination of a source region, a drain region and a channel region.

In some possible embodiments, the stacked fork plate transistor may further include: a front gate isolation structure; the front grid isolation structures are arranged on the surface, far away from the back transistor, of the dielectric fork plate structure, and the front grid structures of the front transistors are symmetrically arranged on two sides of the front grid isolation structures; a back gate isolation structure; the back grid isolation structures are arranged on the surface, far away from the front side transistors, of the dielectric fork plate structures, and the back grid structures of the back side transistors are symmetrically arranged on two sides of the back grid isolation structures.

It will be appreciated that when the dielectric fork plate structure only penetrates the front side active structure and the back side active structure, a front side gate isolation structure may be provided in the front side gate structure, the front side gate isolation structure being used to isolate the gate structure in the first front side transistor from the gate structure in the second front side transistor. Accordingly, a back gate isolation structure is provided in the back gate structure, the back gate isolation structure being used to isolate the gate structure in the first back transistor from the gate structure in the second back transistor.

It will be appreciated that the dielectric fork plate structure may extend through not only the front side active structure and the back side active structure, but also the front side gate structure and the back side gate structure, where the dielectric fork plate structure is used to isolate the gate structure in the first front side transistor from the gate structure in the second front side transistor, and the dielectric fork plate structure is used to isolate the gate structure in the first back side transistor from the gate structure in the second back side transistor.

In the embodiment of the application, the front side transistor and the back side transistor in the stacked fork plate transistor can be the same type of transistor, such as any one of the following: nanoflake field effect transistors, fin field effect transistors, planar transistors, and the like. Wherein, as fork plate transistors, the first and second front-side transistors of the front-side transistors may be the same type of transistors (e.g., NFETs or PFETs) or may be different types of transistors (e.g., NFETs and PFETs); accordingly, the first back side transistor and the second back side transistor in the back side transistors may be the same type of transistor or may be different types of transistors; the embodiment of the application does not particularly limit the types of the plurality of transistors in the stacked fork plate transistor.

Fig. 2 is a schematic diagram of a stacked fork transistor formed by a nano-chip field effect transistor, and a method for manufacturing the stacked fork transistor according to an embodiment of the present application is described below with reference to the structure of the stacked fork transistor shown in fig. 2.

Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing a stacked fork transistor according to an embodiment of the present application, and referring to fig. 1, the method for manufacturing a stacked fork transistor may include:

S101, forming an active structure on a substrate; the active structures include a front-side active structure and a back-side active structure.

It is appreciated that the front-side active structures in the front-side transistors and the back-side active structures in the back-side transistors may be formed by etching the substrate.

In some embodiments, the substrate may include a top substrate, an intermediate sacrificial layer, and a bottom substrate, which are stacked in this order.

It will be appreciated that the process of preparing the substrate may comprise: a layer of sacrificial layer material is epitaxially grown on an original substrate (namely a bottom substrate) to form an intermediate sacrificial layer; next, a top substrate is formed by epitaxially growing the same semiconductor material as the bottom substrate over the intermediate sacrificial layer. The substrate formed by the preparation method comprises a top substrate, an intermediate sacrificial layer and a bottom substrate which are stacked in sequence. Wherein the top substrate is used for preparing the front-side transistor and the bottom substrate is used for preparing the back-side transistor.

In some embodiments, the material of the intermediate sacrificial layer may be a silicon germanium (SiGe) material, or may be another semiconductor material, which is not particularly limited in this embodiment of the present application.

In some embodiments, when the types of stacked fork plate transistors are different, the arrangement of the substrates is correspondingly different. For example, when the stacked fork plate transistor is any one of a fin field effect transistor and a planar transistor, the bottom substrate and the top substrate may be a silicon (Si) material.

In some embodiments, when the stacked fork plate transistor is a nanoflake field effect transistor, both the top substrate and the bottom substrate are of a stacked configuration (i.e., a stack of alternating depositions of silicon and silicon germanium); at this time, the germanium content in the silicon germanium material used in the top and bottom substrates is different from the germanium content in the silicon germanium material used in the intermediate sacrificial layer (i.e., siGe 1 is used to make the top and bottom substrates and SiGe 2 is used to make the intermediate sacrificial layer). Thus, the selective etching of the intermediate sacrificial layer can be completed in the subsequent preparation process.

In some embodiments, when the stacked fork plate transistor is a nano-plate field effect transistor, the thickness of the silicon layer located at the lowest of the bottom substrate may be greater than the thickness of the other silicon layers in the stack, and the substrate is formed by sequentially depositing material layers of different materials based on the lowest silicon layer of the bottom substrate (see (a) in fig. 3A).

In some embodiments, the height of the top substrate may be designed according to practical requirements, such as 50nm, the height of the bottom substrate is greater than the top substrate, and the height of the intermediate sacrificial layer is less than the height of the top substrate.

And S102, forming a front-side transistor based on the front-side active structure.

It will be appreciated that after the front-side active structure and the back-side active structure are formed, the front-side active structure is placed up and the back-side active structure is placed down. Other structures in the front side transistor (e.g., front side source drain structure, front side interlayer dielectric layer, front side gate structure, etc.) may be formed based on the front side active structure.

S103, rewinding and removing the substrate.

It will be appreciated that after the front side transistor is formed, the back side active structure is exposed by a reverse process to place the lowermost silicon layer in the bottom substrate upward and then removing the lowermost silicon layer in the bottom substrate before the back side transistor is fabricated.

In some possible embodiments, before the step S103, the method may further include: depositing an insulating material on the surface of the front-side transistor to form an insulating layer; and bonding the insulating layer with the carrier wafer.

It can be appreciated that the bonded carrier wafer can provide physical support for the inverted front-side transistor after rewinding, so as to effectively prevent the front-side transistor from being broken due to external force in the process of preparing the back-side transistor.

And S104, forming a back side transistor based on the back side active structure.

Wherein the front side transistor and the back side transistor are self-aligned.

It is understood that other structures in the back side transistor (e.g., back side source drain structure, back side interlayer dielectric layer, back side gate structure, etc. of the back side transistor) may be formed based on the back side active structure.

In the embodiment of the application, the active region of the front-side transistor and the active region of the back-side transistor are self-aligned because the front-side active structure and the back-side active structure are formed by the same process; the self-alignment of the active region further causes the front-side and back-side transistors to also be self-aligned.

In the embodiment of the application, the dielectric fork plate structure of the stacked fork plate transistor penetrates through the front active structure and the back active structure, the front active structure is divided into two symmetrically arranged parts by the dielectric fork plate structure, the back active structure is divided into two symmetrically arranged parts by the dielectric fork plate structure, the dielectric fork plate structure is formed by adopting non-uniform deposition, and an air gap (air gap) is formed inside the dielectric fork plate structure.

It can be appreciated that the dielectric fork plate structure divides the front active structure into two symmetrically disposed portions and the back transistor into two symmetrically disposed portions by penetrating the front active structure and the back active structure. Further, the dielectric fork plate structure divides the active area of the front side transistor into two symmetrical parts and divides the active area of the back side transistor into two symmetrical parts. Correspondingly, the first front-side transistor and the second front-side transistor are symmetrically arranged on two sides of the dielectric fork plate structure, and the first back-side transistor and the second back-side transistor are symmetrically arranged on two sides of the dielectric fork plate structure. By a deposition method of non-uniform deposition, a dielectric fork plate structure with air gaps can be obtained.

In the embodiment of the application, the k value of the gap clearance is smaller, so that the capacitance can be effectively reduced and the running speed of a circuit can be improved by introducing the air clearance into the dielectric fork plate structure.

In the embodiment of the application, two sequential schemes for preparing the medium fork plate structure are included in the process of preparing the stacked fork plate structure. The first sequence scheme is as follows: the dielectric fork plate structure is formed prior to forming the front-side active structure and the back-side active structure. The second sequence scheme is as follows: in the process of forming the back side transistor, a dielectric fork plate structure is formed. Next, a method of manufacturing the stacked fork-plate transistor will be described in detail according to the two sequential schemes described above.

In some possible embodiments, in the case of using the first order scheme, the step S101 may include: depositing semiconductor material in a first region on a substrate to form a pair of oppositely disposed first sidewall structures; a space is arranged between the pair of first side wall structures; etching the substrate by taking the first side wall structure as a mask to form a first groove; non-uniformly depositing a dielectric material in the first recess to form a dielectric fork plate structure having an air gap; the substrates are symmetrically arranged at two sides of the medium fork plate structure; removing the first side wall structure, and depositing a semiconductor material in a second area on the substrate to form a second side wall structure; the second side wall structure covers the surface of the dielectric fork plate structure and part of the surface of the substrate positioned on two sides of the dielectric fork plate structure; and etching the substrate by taking the second side wall structure as a mask to form a front active structure and a back active structure.

It will be appreciated that the number of first sidewall structures is two, and that a pair of first sidewall structures are disposed opposite one another on the substrate (see fig. 3A) with a space therebetween. The second sidewall structure is disposed over the dielectric fork plate structure and the substrate (see fig. 3A).

In one example, a hard mask material is deposited on a substrate to form a hard mask layer on the substrate; and coating photoresist on the hard mask layer, and photoetching the hard mask layer after developing the photoresist to form a pair of first side wall structures which are oppositely arranged. After the pair of first side wall structures are formed, etching the substrate by taking the first side wall structures as masks, and stopping etching until the etching is stopped on the lowest silicon layer of the bottom substrate so as to form a first groove; the first recess divides the portion of the substrate on the lowermost silicon layer except the bottom substrate into two symmetrical portions. A pair of first sidewall structures is removed, a dielectric material is non-uniformly deposited in the first recess and a chemical-mechanical planarization (CMP) process is performed, the CMP stopping to the surface of the substrate to form a dielectric fork plate structure with an air gap. Depositing a hard mask material on the substrate and the dielectric fork plate structure to form a hard mask layer; coating photoresist on the hard mask layer, developing the photoresist, and photoetching the hard mask layer to form a second side wall structure; the second sidewall structure covers a portion of the dielectric fork plate structure and the substrate. After the second side wall structure is formed, etching the substrate by taking the second side wall structure as a mask, stopping etching until the etching is stopped on the lowest silicon layer of the bottom substrate, wherein the substrate which is not etched is a front active structure and a back active structure; the substrate above the middle sacrificial layer is a front active structure, and the substrate below the middle sacrificial layer is a back active structure.

In the embodiment of the present application, the semiconductor material forming the first sidewall structure, the second sidewall structure and the third sidewall structure is a hard mask material, and may be any of the following materials: silicon nitride (SiN), silicon dioxide (SiO 2), titanium nitride (TiN), and the like.

In the embodiment of the present application, the dielectric material forming the dielectric fork plate structure may be any one of the following materials: alumina, zirconia, silicon nitride, and the like.

In some possible embodiments, in the case of using the first order scheme, the step S102 may include: forming a front dummy gate structure, a front spacer, a front source drain structure and a front interlayer dielectric layer of the front transistor in sequence based on the front active structure; removing the front side dummy gate structure to expose a front side gate region of the front side transistor; depositing an isolation material in a first portion of the front gate region to form a front gate isolation structure; the front grid isolation structure corresponds to the dielectric fork plate structure; depositing a metal material in the front gate region except for the first portion to form a front gate structure; the front grid electrode structures are symmetrically arranged on two sides of the front grid electrode isolation structure; and performing a subsequent process on the front-side interlayer dielectric layer to form a front-side metal interconnection layer of the front-side transistor.

It will be appreciated that after the front-side active structure is formed, other structures in the front-side transistor (e.g., front-side dummy gate structures, front-side spacers, front-side source drain structures, front-side interlayer dielectric layers, front-side metal interconnect layers, etc.) may be fabricated according to standard steps for fabricating the transistor.

In one example, after the front-side active structure is formed, the front-side gate region of the front-side transistor is opened by a photolithographic process, and polysilicon is deposited in the front-side gate region to form a front-side dummy gate structure. And depositing an insulating material on the surface of the front dummy gate structure to form a front spacer. A portion of the front-side active structure is removed by etching to provide a source drain recess for the front-side transistor. And forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the front transistor by using the front spacer as a mask through selective epitaxial growth so as to fill the source-drain groove of the front transistor, and then forming a front source-drain structure on the strained material through a heavy doping process. And then, depositing insulating materials (such as silicon dioxide (SiO ₂)) on the front-side active structure and the front-side source drain structure to form a front-side interlayer dielectric layer, wherein the front-side interlayer dielectric layer can cover the front-side active structure and the front-side source drain structure. And removing the front dummy gate structure to expose the front gate region. An insulating material (e.g., high-K material) is deposited in the front gate region and over the dielectric fork plate structure to form a front gate isolation structure. And removing the silicon germanium material layer in the front active structure, wherein the front active structure after the silicon germanium material layer is removed is a plurality of nano-sheet structures. An insulating material is deposited on the surface of the nano-sheet structure in the front gate region to form a front gate dielectric layer. And filling a metal material in the front grid region to form the front grid structure. The front grid electrode structures are symmetrically distributed on two sides of the front grid electrode isolation structure. And performing dielectric deposition, metal line formation, lead-out pad formation and the like among the interconnection lines on the front interlayer dielectric layer to form a front metal interconnection layer of the front transistor.

In the embodiment of the application, the front gate structure is divided into two parts by the front gate isolation structure, one part is the gate structure in the first front transistor, the other part is the gate structure in the second front transistor, and the front gate isolation structure is used for isolating the gate structure in the first front transistor and the gate structure in the second front transistor.

It should be noted that, since the front-side transistor is a fork-plate transistor, when the front-side source-drain structure is formed, the strained material can be controlled to grow on two sides of the dielectric fork-plate structure respectively, and the finally formed front-side source-drain structure is symmetrically arranged on two sides of the dielectric fork-plate structure, one part is used as the source-drain structure in the first front-side transistor, and the other part is used as the source-drain structure in the second front-side transistor.

In some possible embodiments, in the case of using the first order scheme, the step S104 may include: forming a back dummy gate structure, a back spacer, a back source drain structure and a back interlayer dielectric layer of the back transistor in sequence based on the back active structure; removing the back dummy gate structure to expose a back gate region of the back transistor; depositing an isolation material in a second portion of the back gate region to form a back gate isolation structure; the back grid isolation structure corresponds to the dielectric fork plate structure; depositing a metal material in the back gate region except for the second portion to form a back gate structure; the back grid electrode structures are symmetrically arranged on two sides of the back grid electrode isolation structure; and performing a back-end process on the back-end interlayer dielectric layer to form a back-end metal interconnection layer of the back-end transistor.

It will be appreciated that after the formation of the back active structure, other structures in the back transistor (e.g., back dummy gate structures, back spacers, back source drain structures, back interlayer dielectric layers, back metal interconnect layers, etc.) may be fabricated according to standard steps for fabricating transistors.

In one example, after the back active structure is formed and placed up, the back gate region of the back transistor is opened by a photolithographic process, and polysilicon is deposited in the back gate region to form a back dummy gate structure. And depositing an insulating material on the surface of the back dummy gate structure to form a back spacer. A portion of the back side active structure is removed by etching to provide a source drain recess for the back side transistor. And forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the back transistor by using the back spacer as a mask through selective epitaxial growth so as to fill the source-drain groove of the back transistor, and then forming a back source-drain structure on the strained material through a heavy doping process. Next, an insulating material (e.g., silicon dioxide (SiO ₂)) is deposited over the back-side active structure and the back-side source-drain structure to form a back-side interlayer dielectric layer, which may cover the back-side active structure and the back-side source-drain structure. And removing the back dummy gate structure to expose the back gate region. An insulating material (e.g., high-K material) is deposited in the back gate region and over the dielectric fork plate structure to form a back gate isolation structure. And removing the silicon germanium material layer in the back active structure, wherein the back active structure after the silicon germanium material layer is removed is a plurality of nano sheet structures. An insulating material is deposited on the surface of the nanoplatelet structure in the back gate region to form a back gate dielectric layer. And filling a metal material in the back gate region to form a back gate structure. The back grid electrode structures are symmetrically distributed on two sides of the back grid electrode isolation structure. And performing dielectric deposition, metal line formation, lead-out pad formation and the like among the interconnection lines on the back interlayer dielectric layer to form a back metal interconnection layer of the back transistor.

In some possible embodiments, in the case of using the second order scheme, the step S101 may include: depositing a semiconductor material in a third region on the substrate to form a third side wall structure; the third side wall structure covers a part of the surface of the substrate; and etching the substrate by taking the third side wall structure as a mask to form a front active structure and a back active structure.

It can be appreciated that the third region in the second sequential scheme is located at the same position as the second region in the first sequential scheme, and the third sidewall structure is the same as the second sidewall structure.

In one example, a hard mask material is deposited on a substrate to form a hard mask layer; coating photoresist on the hard mask layer, developing the photoresist, and photoetching the hard mask layer to form a third side wall structure; the third sidewall structure covers a portion of the substrate. After the third side wall structure is formed, etching the substrate by taking the third side wall structure as a mask, stopping etching until the etching is stopped on the lowest silicon layer of the bottom substrate, wherein the substrate which is not etched is a front active structure and a back active structure; the substrate above the middle sacrificial layer is a front active structure, and the substrate below the middle sacrificial layer is a back active structure.

In some possible embodiments, in the case of using the second order scheme, the step S102 may include: forming a front dummy gate structure, a front spacer, a front source drain structure and a front interlayer dielectric layer of the front transistor in sequence based on the front active structure; removing the front side dummy gate structure to expose a front side gate region of the front side transistor; depositing a metal material in the front gate region to form a front gate structure; and performing a subsequent process on the front-side interlayer dielectric layer to form a front-side metal interconnection layer of the front-side transistor.

In one example, after the front-side active structure is formed, the front-side gate region of the front-side transistor is opened by a photolithographic process, and polysilicon is deposited in the front-side gate region to form a front-side dummy gate structure. And depositing an insulating material on the surface of the front dummy gate structure to form a front spacer. A portion of the front-side active structure is removed by etching to provide a source drain recess for the front-side transistor. And forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the front transistor by using the front spacer as a mask through selective epitaxial growth so as to fill the source-drain groove of the front transistor, and then forming a front source-drain structure on the strained material through a heavy doping process. And then, depositing an insulating material (such as silicon dioxide) on the front-side active structure and the front-side source drain structure to form a front-side interlayer dielectric layer, wherein the front-side interlayer dielectric layer can cover the front-side active structure and the front-side source drain structure. Removing the front dummy gate structure to expose the front gate region; and removing the silicon germanium material layer in the front active structure, wherein the front active structure after the silicon germanium material layer is removed is a plurality of nano-sheet structures. An insulating material is deposited on the surface of the nano-sheet structure in the front gate region to form a front gate dielectric layer. And filling a metal material in the front grid region to form the front grid structure. And performing dielectric deposition, metal line formation, lead-out pad formation and the like among the interconnection lines on the front interlayer dielectric layer to form a front metal interconnection layer of the front transistor.

In some possible embodiments, in the case of using the second order scheme, the step S104 may include: forming a back dummy gate structure, a back spacer, a back source drain structure and a back interlayer dielectric layer of the back transistor in sequence based on the back active structure; sequentially etching the back interlayer dielectric layer, the back active structure, the front active structure and the front interlayer dielectric layer to form a second groove; the second groove divides the front active structure into two parts which are symmetrically arranged, and the second groove divides the back active structure into two parts which are symmetrically arranged; non-uniformly depositing a dielectric material in the second recess to form a dielectric fork plate structure having an air gap; removing the back dummy gate structure to expose a back gate region of the back transistor; depositing a metal material in the back gate region to form a back gate structure; and performing a back-end process on the back-end interlayer dielectric layer to form a back-end metal interconnection layer of the back-end transistor.

In one example, after the back active structure is formed and placed up, the back gate region of the back transistor is opened by a photolithographic process, and polysilicon is deposited in the back gate region to form a back dummy gate structure. And depositing an insulating material on the surface of the back dummy gate structure to form a back spacer. A portion of the back side active structure is removed by etching to provide a source drain recess for the back side transistor. And forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the back transistor by using the back spacer as a mask through selective epitaxial growth so as to fill the source-drain groove of the back transistor, and then forming a back source-drain structure on the strained material through a heavy doping process. Next, an insulating material (e.g., silicon dioxide (SiO ₂)) is deposited over the back-side active structure and the back-side source-drain structure to form a back-side interlayer dielectric layer, which may cover the back-side active structure and the back-side source-drain structure. And coating photoresist on the back interlayer dielectric layer and the back dummy gate structure, developing the photoresist and forming a photoetching pattern, and etching the back interlayer dielectric layer, the back dummy gate structure, the back source drain structure, the back active structure, the front source drain structure, the front active structure, the front gate structure and the front interlayer dielectric layer according to the photoetching pattern to form a second groove. The second groove divides the semiconductor structure which is not manufactured into two symmetrical parts. Dielectric material is unevenly deposited in the second recess to form a dielectric fork plate structure having an air gap. And removing the back dummy gate structure, exposing the back gate region, and removing the silicon germanium material layer in the back active structure, wherein the back active structure after the silicon germanium material layer is removed is a plurality of nano-sheet structures. An insulating material is deposited on the surface of the nanoplatelet structure in the back gate region to form a back gate dielectric layer. And filling a metal material in the back gate region to form a back gate structure. And performing dielectric deposition, metal line formation, lead-out pad formation and the like among the interconnection lines on the back interlayer dielectric layer to form a back metal interconnection layer of the back transistor.

In the second sequential scheme, the dielectric fork plate structure penetrates from the back interlayer dielectric layer to the front interlayer dielectric layer, and the stacked fork plate transistor is divided into two symmetrical parts, such as: a first stacked fork plate transistor (including a first front side transistor and a first back side transistor) and a second stacked fork plate transistor (including a second front side transistor and a second back side transistor). In a second sequential scheme, the dielectric fork plate structure divides the front-side gate structure into two symmetrical parts (one part is the gate structure in the first front-side transistor and the other part is the gate structure in the second front-side transistor) and is used for isolating the gate structure in the first front-side transistor and the gate structure in the second front-side transistor. Correspondingly, the dielectric fork plate structure is also used to isolate the gate structure in the first back side transistor from the gate structure in the second back side transistor.

In some possible embodiments, the substrate includes a top substrate, an intermediate sacrificial layer, and a bottom substrate, disposed in a stacked order, the top substrate being used to form the front-side active structure, the bottom substrate being used to form the back-side active structure. Prior to the step S102, the method may further include: depositing an insulating material on the substrate to form a shallow trench isolation structure; the shallow slot isolation structure wraps the front active structure, the middle sacrificial layer and the back active structure; a portion of the shallow trench isolation structure surrounding the front-side active structure is removed to expose the front-side active structure.

It is appreciated that after forming the front-side active structure and the back-side active structure, an insulating material is deposited over the front-side active structure and the back-side active structure, and CMP is performed, with CMP stopping to a surface of the front-side active structure remote from the back-side active structure, to form a shallow trench isolation structure (shallow trench isolation, STI) that encapsulates the front-side active structure and the back-side active structure. And then, removing a part of the shallow trench isolation structure which wraps the front-side active structure, and exposing the front-side active structure so as to prepare the front-side transistor.

In some possible embodiments, the above method further comprises: removing the intermediate sacrificial layer to form a third groove; an insulating material is deposited in the third recess to form an intermediate isolation layer.

The middle isolation layer is used for isolating the front active structure and the back active structure.

It will be appreciated that the intermediate sacrificial layer is removed after the front-side dummy gate structure is formed, so that the front-side dummy gate structure can support the front-side active structure. And removing the intermediate sacrificial layer to form a third groove positioned between the front active structure and the back active structure, and filling an insulating material in the third groove to form an intermediate isolation layer.

It should be noted that the middle isolation layer and the front spacer may be made of the same insulating material, and further, the middle isolation layer and the front spacer may be formed in the same process.

In some possible embodiments, after the step S103, the method may further include: and removing the part of the shallow trench isolation structure wrapping the back active structure to expose the back active structure and forming a shallow trench isolation layer.

It will be appreciated that before the back side transistor is fabricated, the back side active structure needs to be exposed, the shallow trench isolation structure may be removed by etching, and during the etching process, the shallow trench isolation structure with a predetermined thickness is reserved, and the reserved portion of the shallow trench isolation structure (i.e., the shallow trench isolation layer) is located between the front side transistor and the back side transistor. The shallow trench isolation layer is used to isolate the front side transistor from the back side transistor.

In the embodiment of the application, the front side transistor is prepared before the film is rewound, the back side transistor is prepared after the film is rewound, namely, the active area and the front side grid structure of the front side transistor are formed before the film is rewound, and the active area and the back side grid structure of the back side transistor are formed after the film is rewound, so that the front side transistor and the back side transistor can be respectively and independently manufactured, and the process optimization of the front side transistor and the back side transistor is realized.

In the following, a front-side transistor and a back-side transistor are taken as examples of nano-chip field effect transistors, and the stacked fork-plate transistor provided by the embodiment of the application is described. Fig. 2 is a schematic diagram of a first structure of a stacked fork-plate transistor according to an embodiment of the present application. In fig. 2, (a) is a design layout of the stacked fork plate transistor, and for convenience of understanding, only a nano-sheet structure, a gate structure and a source-drain structure are shown in the design layout; (b) Cut-away views of stacked fork-plate transistors taken along the cut-away direction (i.e., the A-A' direction) of the gate structure; (c) A cross-sectional view of the stacked fork plate transistor along a cross-sectional direction (i.e., the B-B' direction) of the source-drain structure; (d) Cut-away views of stacked fork-plate transistors are made along the cut-away direction (i.e., the C-C' direction) of the nanoplate structure.

Referring to fig. 2, stacked fork plate transistors include front side transistors, back side transistors, and dielectric fork plate structures. The front side transistor comprises a first front side transistor and a first back side transistor, the back side transistor comprises a second front side transistor and a second back side transistor, the first front side transistor and the first back side transistor are self-aligned, and the second front side transistor and the second back side transistor are self-aligned; the first front-side transistor and the second front-side transistor are symmetrically arranged on two sides of the dielectric fork plate structure, and the first back-side transistor and the second back-side transistor are symmetrically arranged on two sides of the dielectric fork plate structure. The dielectric fork plate structure penetrates through the front active structure and the back active structure, divides the front active structure into two symmetrically arranged parts, and divides the back active structure into two symmetrically arranged parts.

Referring to fig. 2, the stacked fork transistor further includes a front-side gate isolation structure, which divides the front-side gate structure into two symmetrically arranged parts and is used to isolate the gate structure in the first front-side transistor from the gate structure in the second front-side transistor. Correspondingly, the stacked fork plate transistor further comprises a back gate isolation structure which is divided into two parts symmetrically arranged and used for isolating the gate structure in the first back transistor and the gate structure in the second back transistor.

The process of fabricating the stacked fork-plate transistor 10 shown in fig. 2 will be described below in connection with the fabrication method of the first sequential scheme described above. The stacked fork-plate transistor 10 shown in fig. 2 can be manufactured by the process shown in fig. 3A to 3D, and fig. 3A to 3D are schematic diagrams illustrating a first manufacturing process of the stacked fork-plate transistor according to the embodiment of the present application.

In an example, taking stacked fork-plate transistor 10 as a nano-sheet field effect transistor, a first process for preparing stacked fork-plate transistor 10 may include the steps of:

it should be noted that the different steps (i.e., different processes) in the following examples may show the manufacturing process of the stacked fork plate transistor 10 with A-A ' direction, B-B ' direction, C-C ' direction, or different combinations of the above directions, respectively, according to the structural changes.

The first step: a substrate 21 is provided (see (a) in fig. 3A).

The preparation method of the substrate 21 comprises providing a Si layer, alternately depositing SiGe 1 material and Si material on the Si layer to form a laminated layer with a preset thickness, wherein the laminated layer is a bottom substrate 211; next, a SiGe 2 material is deposited on the bottom substrate 211, forming an intermediate sacrificial layer 212; finally, siGe 1 material and Si material are alternately deposited on the intermediate sacrificial layer 212 to form a stack of a predetermined thickness, which is a top substrate 213.

And a second step of: depositing a hard mask material on the top substrate 213, forming a hard mask layer covering an upper surface (not shown) of the top substrate 213; next, a photoresist is coated on the hard mask layer, and after the photoresist is developed, a portion of the hard mask layer is removed by photolithography, and finally a pair of first sidewall structures 22 are formed (see (b) in fig. 3A).

And a third step of: the top substrate 213, the intermediate sacrificial layer 212, and the bottom substrate 211 are sequentially etched using the pair of first sidewall structures 22 as a mask, and the etching is stopped to the upper surface of the lowermost substrate of the bottom substrate 211, forming a first recess 23 (see (c) in fig. 3A).

Fourth step: a pair of first sidewall structures 22 is removed (see (d) in fig. 3A).

Fifth step: in the first recess 23 and on the top substrate 213, dielectric material is unevenly deposited, and a portion of the dielectric material on the top substrate 213 is removed by a CMP process, and CMP is stopped to the surface of the top substrate 213, the dielectric material remaining in the first recess forms a dielectric fork plate structure 24, and an air gap 25 is provided inside the dielectric fork plate structure 24 (see (e) in fig. 3A).

Sixth step: depositing a hard mask material on the top substrate 213, forming a hard mask layer that covers the top substrate 213 and the upper surface of the dielectric fork plate structure 24 (not shown in the figures); next, a photoresist is coated on the hard mask layer, and after the photoresist is developed, a portion of the hard mask layer is removed by photolithography, and finally the second sidewall structure 26 is formed (see (f) in fig. 3A).

Seventh step: the top substrate 213, the intermediate sacrificial layer 212, and the bottom substrate 211 are sequentially etched using the second sidewall structure 26 as a mask, and the etching is stopped to the upper surface of the lowermost substrate of the bottom substrate 211, forming the front active structure 111 and the back active structure 121 (see (g) in fig. 3A).

Eighth step: the second sidewall structures 26 are removed and an insulating material is deposited on the top substrate 213 and on the lowermost substrate of the bottom substrate 211 and a CMP process is performed, which stops on the surface of the front-side active structure 111 remote from the back-side active structure 121, forming shallow trench isolation structures 27 (see (h) in fig. 3A).

Wherein shallow trench isolation structure 27 wraps around front-side active structure 111, intermediate sacrificial layer 212, and back-side active structure 121.

Ninth step: the shallow trench isolation structure 27 surrounding the front-side active structure 111 and the intermediate sacrificial layer 212 is removed by etching, exposing the front-side active structure 111 (see (i) in fig. 3A).

As shown in (a) to (i) of fig. 3A, the fabrication process of the stacked fork plate transistor 10 is shown in the A-A' direction.

Tenth step: the front-side gate region of the front-side transistor 11 is opened by photolithography and polysilicon is deposited in the front-side gate region to form a front-side dummy gate structure 311 of the front-side transistor 11 (see (a) in fig. 3B).

Eleventh step: the intermediate sacrificial layer 212 is removed under the supporting action of the front dummy gate structure 311 to form a recess (i.e., a third recess 32) (see (B) in fig. 3B).

Twelfth step: an insulating material is deposited in the third recess 32 and on the sidewalls of the front dummy gate structure 311 to form the intermediate isolation layer 33 and the front spacers 112 (see (c) in fig. 3B).

As shown in (a) to (C) in fig. 3B, the fabrication process of the stacked fork plate transistor 10 is shown in the A-A 'direction and the C-C' direction.

Thirteenth step: the front-side interior sidewalls 341 and the front-side source drain structures 113 are grown following standard procedures (see (a) in fig. 3C).

Fourteenth step: depositing an insulating material on the front-side source drain structure 113 to form a front-side interlayer dielectric layer 114; removing the front dummy gate structure 311 to expose the front gate region; removing the SiGe 1 material layer in the front-side active structure 111 (the front-side active structure 111 after the SiGe 1 material layer is removed is a nano-sheet structure); depositing an insulating material on the surface of the front-side active structure 111 to form a front-side gate dielectric layer 115; depositing an isolation material on the dielectric fork plate structure 24 to form a front gate isolation structure 411; a metal material is deposited in the front gate region to form front gate structure 116 (see (b) in fig. 3C).

Fifteenth step: a subsequent process is performed over the front side interlayer dielectric layer 114 and the front side gate structure 116 to form a front side metal interconnect layer 117 (see (C) in fig. 3C).

As shown in (a) of fig. 3C, the fabrication process of the stacked fork plate transistor 10 is shown in the B-B 'direction and the C-C' direction. As shown in (b) and (C) of fig. 3C, the fabrication process of the stacked fork plate transistor 10 is shown in the A-A 'direction and the C-C' direction.

Sixteenth step: depositing an insulating material on the front side metal interconnect layer 117 to form an insulating layer 13; bonding the carrier wafer 14 to the insulating layer 13; the front-side transistor 11 is rewound so that the bottom substrate 211 is placed upward (see (a) in fig. 3D).

Seventeenth step: the lowermost Si layer of the bottom substrate 211 is removed by a wafer thinning process and a CMP process (see (b) in fig. 3D).

Eighteenth step: removing the shallow trench isolation structure 27 wrapping the back active structure 121 to expose the back active structure 121 and form a shallow trench isolation layer 271; based on the back active structure 121, a back dummy gate structure 312, a back spacer 122, a back sidewall spacer 342, a back source drain structure 123, a back interlayer dielectric layer 124, a back gate dielectric layer 125, a back gate isolation structure 412, a back gate structure 126, and a back metal interconnect layer 127 (see (c) in fig. 3D) are formed in the back transistor 12 (see twelfth to fifteenth steps for specific processes).

As shown in (a) and (b) of fig. 3D, the fabrication process of the stacked fork plate transistor 10 is shown in the A-A 'direction and the C-C' direction. As shown in (C) of fig. 3D, the fabrication process of the stacked fork plate transistor 10 is shown in the A-A ', B-B ' and C-C ' directions.

Thus, the stacked fork-plate transistor 10, in which the front-side transistor 11 and the back-side transistor 12 are nanoflake field-effect transistors, is prepared according to the first sequential scheme.

In the case of the A-A' direction (refer to the (b) diagram in fig. 2), the first front side transistor and the second front side transistor are used to represent transistors distributed on both sides of the dielectric fork structure, and the present application is not limited to the positions of the first front side transistor and the second front side transistor in the front side transistors. For example, the first front side transistor may be located on the left or right side of the dielectric fork plate structure, and the second front side transistor may be located on the right or left side of the dielectric fork plate structure, respectively. The positions of the first back side transistor and the second back side transistor in the back side transistor are similar to the positions of the first front side transistor and the second front side transistor in the front side transistor, and the embodiments of the present application will not be described in detail.

Fig. 4 is a schematic diagram of a second structure of a stacked fork transistor according to an embodiment of the present application. In fig. 4, (a) is a design layout of the stacked fork plate transistor, and for convenience of understanding, only a nano-sheet structure, a gate structure and a source-drain structure are shown in the design layout; (b) Cut-away views of stacked fork-plate transistors taken along the cut-away direction (i.e., the A-A' direction) of the gate structure; (c) A cross-sectional view of the stacked fork plate transistor along a cross-sectional direction (i.e., the B-B' direction) of the source-drain structure; (d) Cut-away views of stacked fork-plate transistors are made along the cut-away direction (i.e., the C-C' direction) of the nanoplate structure.

Referring to fig. 4, stacked fork plate transistors include front side transistors, back side transistors, and dielectric fork plate structures. The front side transistor comprises a first front side transistor and a first back side transistor, the back side transistor comprises a second front side transistor and a second back side transistor, the first front side transistor and the first back side transistor are self-aligned, and the second front side transistor and the second back side transistor are self-aligned; the first front-side transistor and the second front-side transistor are symmetrically arranged on two sides of the dielectric fork plate structure, and the first back-side transistor and the second back-side transistor are symmetrically arranged on two sides of the dielectric fork plate structure. The dielectric fork plate structure penetrates through the front active structure and the back active structure, penetrates through the front grid structure and the back grid structure, divides the front grid structure into two parts which are symmetrically arranged, and divides the back grid structure into two parts which are symmetrically arranged.

The process of fabricating the stacked fork-plate transistor 10 shown in fig. 4 will be described below in connection with the fabrication method of the second sequential scheme described above. The stacked fork-plate transistor 10 shown in fig. 4 can be prepared by the process shown in fig. 5A and 5B, and fig. 5A and 5B are schematic diagrams of a second preparation process of the stacked fork-plate transistor according to the embodiment of the present application.

In an example, taking stacked fork-plate transistor 10 as a nano-sheet field effect transistor, a second process for fabricating stacked fork-plate transistor 10 may include the steps of:

The first step: a substrate 21 is provided. Depositing a hard mask material on the top substrate 213, forming a hard mask layer that covers the top substrate 213 and the upper surface of the dielectric fork plate structure 24 (not shown in the figures); next, a photoresist is coated on the hard mask layer, and after the photoresist is developed, a portion of the hard mask layer is removed by photolithography, and finally a third sidewall structure 51 is formed (see (a) of fig. 5A).

And a second step of: the top substrate 213, the intermediate sacrificial layer 212, and the bottom substrate 211 are sequentially etched using the third sidewall structure 51 as a mask, and the etching is stopped to the upper surface of the lowermost substrate of the bottom substrate 211, forming the front active structure 111 and the rear active structure 121 (see (b) in fig. 5A).

And a third step of: shallow trench isolation structures 27 are formed. After the front active structure 111 is exposed, a front dummy gate structure 311, an intermediate isolation layer 33, a front spacer 112, a front sidewall inside wall 341, a front source drain structure 113, a front interlayer dielectric layer 114, a front gate dielectric layer 115, a front gate structure 116, and a front metal interconnect layer 117 are formed based on the front active structure 111. After rewinding, the back dummy gate structure 312, the back spacer 122, the back sidewall spacer 342, the back source drain structure 123, and the back interlayer dielectric layer 124 are formed based on the back active structure 121 (see (a) in fig. 5B) (see tenth to fifteenth steps of the first manufacturing method for specific processes).

Fourth step: photoresist (not shown) is coated on the back dummy gate structure 312 and the back interlayer dielectric layer 124, and after the photoresist is developed, the back interlayer dielectric layer 124, the back dummy gate structure 312, the back active structure 121, the shallow trench isolation layer 271, the middle isolation layer 33, the front active structure 111, the front interlayer dielectric layer 114 and the front gate structure 116 are etched by photolithography to form the second recess 52; next, the photoresist is removed (see (B) in fig. 5B).

Fifth step: dielectric material is non-uniformly deposited in the second recess 52 forming a dielectric fork plate structure 24 with an air gap 25 (see (c) in fig. 5B).

Sixth step: the back dummy gate structure 312 is removed, exposing the back gate region, and a metal material is deposited in the back gate region to form the back gate structure 126. A back-side process is performed on the back-side gate structure 126 and the back-side interlayer dielectric layer 124 to form a back-side metal interconnect layer 127 (see fig. 4 for specific structure).

Thus, the stacked fork-plate transistor 10, in which the front-side transistor 11 and the back-side transistor 12 are nanoflake field-effect transistors, is prepared according to the second sequential scheme.

In the embodiment of the present application, an etching method or a thermal decomposition method may be used instead of the non-uniform deposition method to form the dielectric fork plate structure with the air gap, which is not particularly limited in the embodiment of the present application.

In the embodiment of the application, the dielectric fork plate structure with the air gap is arranged in the front active structure and the back active structure, so that the capacitance can be effectively reduced.

Further, the stacked fork plate transistor provided by the embodiment of the application can be detected by using a detection analysis instrument, for example: scanning electron microscope (scanning electron microscope, SEM), transmission electron microscope (transmission electron microscope, TEM), scanning transmission electron microscope (scanning transmission electron microscopy, STEM), and the like. Taking TEM as an example, the stacked fork plate transistor provided in the embodiment of the present application may detect the structure of the stacked fork plate transistor by using a TEM slicing manner, for example, the active areas of the front side transistor and the back side transistor are self-aligned, the front side transistor is divided into a first front side transistor and a second front side transistor which are symmetrically arranged by the dielectric fork plate structure, and the back side transistor is divided into a first back side transistor and a second back side transistor which are symmetrically arranged by the dielectric fork plate structure, and an air gap in the dielectric fork plate structure.

An embodiment of the present application provides a semiconductor device including: stacked fork plate transistors as in the above embodiments. The specific limitation of the stacked fork transistor may be referred to the stacked fork transistor shown in fig. 2 and 4 and will not be described herein.

An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device includes the stacked fork plate transistor described above. The specific limitation of the stacked fork transistor may be referred to the stacked fork transistor shown in fig. 2 and 4 and will not be described herein.

In the description of the present application, a description of the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method of making a stacked fork plate transistor, the method comprising:

forming an active structure on a substrate; the active structure comprises a front active structure and a back active structure;

Forming a front-side transistor based on the front-side active structure;

rewinding and removing the substrate;

Forming a back side transistor based on the back side active structure; the front side transistor and the back side transistor are self-aligned;

The dielectric fork plate structure of the stacked fork plate transistor penetrates through the front active structure and the back active structure, the front active structure is divided into two parts which are symmetrically arranged by the dielectric fork plate structure, the back active structure is divided into two parts which are symmetrically arranged by the dielectric fork plate structure, the dielectric fork plate structure is formed by non-uniform deposition, and an air gap is formed in the dielectric fork plate structure.

2. The method of claim 1, wherein forming an active structure on a substrate comprises:

depositing semiconductor material in a first region on the substrate to form a pair of oppositely disposed first sidewall structures; a space is arranged between the pair of first side wall structures;

etching the substrate by taking the first side wall structure as a mask to form a first groove;

Non-uniformly depositing a dielectric material in the first recess to form the dielectric fork plate structure with an air gap; the substrates are symmetrically arranged on two sides of the medium fork plate structure;

Removing the first side wall structure, and depositing a semiconductor material in a second area on the substrate to form a second side wall structure; the second side wall structure covers the surface of the dielectric fork plate structure and part of the surface of the substrate positioned at two sides of the dielectric fork plate structure;

And etching the substrate by taking the second side wall structure as a mask to form the front active structure and the back active structure.

3. The method of claim 2, wherein forming a front-side transistor based on the front-side active structure comprises:

forming a front dummy gate structure, a front gap wall, a front source drain structure and a front interlayer dielectric layer of the front transistor in sequence based on the front active structure;

Removing the front-side dummy gate structure to expose a front-side gate region of the front-side transistor;

depositing an isolation material on a first portion of the front gate region to form a front gate isolation structure; the front grid isolation structure corresponds to the dielectric fork plate structure;

depositing a metal material in the front gate region except for the first part to form a front gate structure; the front grid electrode structures are symmetrically arranged on two sides of the front grid electrode isolation structure;

and performing a subsequent process on the front-side interlayer dielectric layer to form a front-side metal interconnection layer of the front-side transistor.

4. The method of claim 2, wherein forming a back side transistor based on the back side active structure comprises:

Forming a back dummy gate structure, a back gap wall, a back source drain structure and a back interlayer dielectric layer of the back transistor in sequence based on the back active structure;

removing the back dummy gate structure to expose a back gate region of the back transistor;

Depositing an isolation material in a second portion of the back gate region to form a back gate isolation structure; the back gate isolation structure corresponds to the dielectric fork plate structure;

Depositing a metal material in the back gate region except for the second portion to form a back gate structure; the back gate structures are symmetrically arranged on two sides of the back gate isolation structure;

and performing a back process on the back interlayer dielectric layer to form a back metal interconnection layer of the back transistor.

5. The method of claim 1, wherein forming an active structure on a substrate comprises:

Depositing a semiconductor material in a third region on the substrate to form a third side wall structure; the third side wall structure covers a part of the surface of the substrate;

and etching the substrate by taking the third side wall structure as a mask to form the front active structure and the back active structure.

6. The method of claim 5, wherein forming a front-side transistor based on the front-side active structure comprises:

depositing a metal material in the front gate region to form a front gate structure;

7. The method of claim 6, wherein forming a back side transistor based on the back side active structure comprises:

sequentially etching the back interlayer dielectric layer, the back active structure, the front active structure and the front interlayer dielectric layer to form a second groove; the second groove divides the front active structure into two symmetrically arranged parts, and the second groove divides the back active structure into two symmetrically arranged parts;

non-uniformly depositing a dielectric material in the second recess to form the dielectric fork plate structure with an air gap;

depositing a metal material in the back gate region to form a back gate structure;

8. The method of claim 1, wherein the substrate comprises a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in this order, the top substrate being used to form the front-side active structure, the bottom substrate being used to form the back-side active structure;

Before the forming of the front-side transistor based on the front-side active structure, the method further comprises:

Depositing an insulating material on the substrate to form a shallow trench isolation structure; the shallow slot isolation structure wraps the front active structure, the middle sacrificial layer and the back active structure;

and removing a part of the shallow trench isolation structure, which wraps the front-side active structure, so as to expose the front-side active structure.

9. The method of claim 8, wherein the method further comprises:

removing the intermediate sacrificial layer to form a third groove;

Depositing an insulating material in the third recess to form an intermediate isolation layer; the intermediate isolation layer is used for isolating the front active structure and the back active structure.

10. A stacked fork plate transistor, comprising:

A front side transistor;

A back side transistor; the front side transistor and the back side transistor are self-aligned;

A dielectric fork plate structure; the dielectric fork plate structure penetrates through the front active structure of the front transistor and the back active structure of the back transistor, the front active structure is divided into two parts which are symmetrically arranged by the dielectric fork plate structure, the back active structure is divided into two parts which are symmetrically arranged by the dielectric fork plate structure, the dielectric fork plate structure is formed by adopting non-uniform deposition, and an air gap is formed inside the dielectric fork plate structure.

11. The stacked fork-plate transistor of claim 10, wherein the stacked fork-plate transistor further comprises:

A front gate isolation structure; the front grid isolation structures are arranged on the surface, far away from the back transistor, of the dielectric fork plate structure, and the front grid structures of the front transistors are symmetrically arranged on two sides of the front grid isolation structures;

a back gate isolation structure; the back grid isolation structure is arranged on the surface, far away from the front transistor, of the dielectric fork plate structure, and the back grid structure of the back transistor is symmetrically arranged on two sides of the back grid isolation structure.

12. The stacked fork plate transistor of claim 10, wherein,

The dielectric fork plate structure penetrates through the front grid structure of the front transistor, and the front grid structure is symmetrically arranged on two sides of the dielectric fork plate structure;

the dielectric fork plate structure penetrates through the back gate structure of the back transistor, and the back gate structure is symmetrically arranged on two sides of the dielectric fork plate structure.

13. A semiconductor device, comprising: the stacked fork plate transistor of claim 10.

14. An electronic device, comprising: a circuit board and the semiconductor device according to claim 13, the semiconductor device being provided to the circuit board.