CN118352304A - Preparation method of stacked fork plate transistor, stacked fork plate transistor and device - Google Patents

Abstract

The application provides a preparation method of a stacked fork plate transistor, the stacked fork plate transistor and a device, wherein the method comprises the following steps: forming an active structure on a substrate; the active structure comprises a front active structure and a back active structure; forming a front-side transistor based on the front-side active structure; rewinding and removing the substrate; forming a back dummy gate structure or a back gate structure, a back source drain structure and a back interlayer dielectric layer of the back transistor based on the back active structure; sequentially photoetching a back dummy gate structure or a back gate structure, a back source drain structure, a back active structure, a front source drain structure, a front active structure and a front gate structure to form a first groove; depositing a dielectric material in the first recess to form a dielectric fork plate structure; forming a back metal interconnection layer; the front side transistor and the back side transistor are self-aligned. The application can simplify the process flow.

Description

Preparation method of stacked fork plate transistor, stacked fork plate transistor and device

Technical Field

The present application relates to the field of semiconductors, and in particular, to a method for manufacturing a stacked fork transistor, and a device.

Background

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors further increase transistor integration density by integrating two or more layers of transistors in vertical space is one of the important technologies continuing the scaling of integrated circuits.

When the fork plate transistor is prepared by adopting the traditional monolithic scheme, the following technical difficulties exist: the dielectric wall is formed after the substrate is initially subjected to photoetching and etching, so that in the subsequent preparation process, the influence of photoetching, etching, deposition and other processes on the dielectric wall needs to be considered, the dielectric wall cannot be damaged, and a certain complexity is brought to the process.

Disclosure of Invention

The application provides a preparation method of a stacked fork plate transistor, the stacked fork plate transistor and a device, so as to simplify the process flow.

In a first aspect, an embodiment of the present application provides a method for manufacturing a stacked fork plate transistor, where the method includes: forming an active structure on a substrate; the active structure comprises a front active structure and a back active structure; forming a front-side transistor based on the front-side active structure; the front-side transistor comprises a front-side grid structure, a front-side source-drain structure and a front-side metal interconnection layer; rewinding and removing the substrate; forming a back dummy gate structure or a back gate structure, a back source drain structure and a back interlayer dielectric layer of the back transistor based on the back active structure; sequentially photoetching a back dummy gate structure or a back gate structure, a back source drain structure, a back active structure, a front source drain structure, a front active structure and a front gate structure to form a first groove; the first groove penetrates through the front active structure and the back active structure, the first groove divides the front active structure into two parts which are symmetrically arranged, and the first groove divides the back active structure into two parts which are symmetrically arranged; depositing a dielectric material in the first recess to form a dielectric fork plate structure; forming a back metal interconnection layer; the front side transistor and the back side transistor are self-aligned.

In some possible embodiments, photolithography is performed on the back dummy gate structure or the back gate structure, the back source drain structure, the back active structure, the front source drain structure, the front active structure, and the front gate structure in order to form the first recess, including: coating photoresist on the back dummy gate structure or the back gate structure; and after developing the photoresist, sequentially etching the back dummy gate structure or the back gate structure, the back source drain structure, the back active structure, the front source drain structure, the front active structure and the front gate structure by using the photoresist as a mask to form a first groove.

In some possible embodiments, forming an active structure on a substrate includes: depositing a hard mask material in a first region on a substrate to form a hard mask structure; the hard mask structure is arranged on the surface of the substrate in a centered manner and covers a part of the surface of the substrate; and etching the substrate by taking the hard mask structure as a mask to form a front active structure and a back active structure.

In some possible embodiments, forming a front-side transistor based on the front-side active structure includes: forming a front dummy gate structure, a front spacer, a front source drain structure and a front interlayer dielectric layer of the front transistor in sequence based on the front active structure; removing the front side dummy gate structure to expose a front side gate region of the front side transistor; depositing a metal material in the front gate region to form a front gate structure; and performing a subsequent process on the front-side interlayer dielectric layer and the front-side grid structure to form a front-side metal interconnection layer of the front-side transistor.

In some possible embodiments, after forming the back dummy gate structure, forming the back gate structure includes: removing the back dummy gate structure to expose a back gate region of the back transistor; depositing a metal material in the back gate region to form a back gate structure; after forming the back gate structure, forming a back metal interconnect layer, comprising: and performing a back process on the back interlayer dielectric layer and the back gate structure to form a back metal interconnection layer of the back transistor.

In some possible embodiments, the substrate includes a top substrate, an intermediate sacrificial layer, and a bottom substrate, stacked in order, the top substrate for forming the front-side active structure, the bottom substrate for forming the back-side active structure; before forming the front-side transistor based on the front-side active structure, the method further comprises: depositing an insulating material on the substrate to form a shallow trench isolation structure; the shallow slot isolation structure wraps the front active structure, the middle sacrificial layer and the back active structure; a portion of the shallow trench isolation structure surrounding the front-side active structure is removed to expose the front-side active structure.

In some possible embodiments, the above method further comprises: removing the intermediate sacrificial layer to form a second groove; depositing an insulating material in the second recess to form an intermediate isolation layer; the intermediate isolation layer is used for isolating the front-side active structure and the back-side active structure.

In a second aspect, an embodiment of the present application provides a stacked fork plate transistor, including: a front side transistor; a back side transistor; the front side transistor and the back side transistor are self-aligned; a dielectric fork plate structure; the dielectric fork plate structure penetrates through the front active structure of the front transistor and the back active structure of the back transistor, the front active structure is divided into two parts which are symmetrically arranged by the dielectric fork plate structure, and the back active structure is divided into two parts which are symmetrically arranged by the dielectric fork plate structure.

In some possible embodiments, the dielectric fork plate structure penetrates through the front-side gate structure of the front-side transistor, and divides the front-side gate structure into two parts which are symmetrically arranged; the dielectric fork plate structure penetrates through the back grid structure of the back transistor, and divides the back grid structure into two parts which are symmetrically arranged.

In a third aspect, an embodiment of the present application provides a semiconductor device including: stacked fork plate transistors as in the above embodiments.

In a fourth aspect, an embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board.

In the application, after the back dummy gate structure and the back source drain structure of the front transistor and the back transistor are formed, the dielectric fork plate structure is formed, so that the influence of the complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process on the dielectric fork plate structure can be reduced in the process of preparing the stacked fork plate transistor, and the process flow is simplified.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic flow chart of a method for manufacturing a stacked fork-plate transistor according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a stacked fork plate transistor according to an embodiment of the present application;

FIGS. 3A-3E are schematic diagrams illustrating a process for fabricating a stacked fork plate transistor according to an embodiment of the present application;

the figures above:

10. Stacking fork plate transistors; 11. a front side transistor; 111. a front-side active structure; 112. a front spacer; 113. a front source drain structure; 114. a front interlayer dielectric layer; 115. a front side gate dielectric layer; 116. a front gate structure; 117. a front side metal interconnect layer; 12. a back side transistor; 121. a back active structure; 122. a back spacer; 123. a back source drain structure; 124. a back interlayer dielectric layer; 125. a back gate dielectric layer; 126. a back gate structure; 127. a backside metal interconnect layer; 13. an insulating layer; 14.a carrier wafer; 21. a substrate; 211. a base substrate; 212. an intermediate sacrificial layer; 213. a top substrate; 22. a hard mask structure; 23. shallow trench isolation structure; 231. shallow groove isolation layer; 311. a front dummy gate structure; 312. a back dummy gate structure; 32. an intermediate isolation layer; 331. front source drain inner side wall; 332. a back source drain inner side wall; 34. a first groove; 35. a dielectric fork plate structure.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.

Currently, techniques for fabricating stacked transistors include two schemes, one is a monolithic scheme (monolithic) and the other is a sequential scheme (sequential). In the preparation of the two schemes described above, a method of preparing two-part transistors separately is adopted, which makes the transistors of the two parts not perfectly aligned.

In addition, a certain separation distance must be maintained between two types of transistors, N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS), constituting Complementary Metal Oxide Semiconductor (CMOS) logic, to limit capacitance that impairs device performance and affects power consumption, reducing interference between adjacent transistors. This spacing limits the scaling of nanoplatelet-based logic. Fork plate transistors (forksheet) are one way to break this limitation, and forksheet is constructed by placing transistors in pairs on either side of a dielectric wall (DIELECTRIC WALL). The dielectric walls allow the device to be placed closely without capacitance problems, and the logic cells can be scaled down with additional space, and wider transistors can be fabricated using existing space to achieve better performance.

However, the original forksheet is manufactured based on a monolithic scheme, wherein the dielectric wall is formed after the substrate is initially subjected to photoetching and etching, so that in the subsequent preparation process, the influence of photoetching, etching, deposition and other processes on the dielectric wall is required to be considered, the dielectric wall is ensured not to be damaged, and a certain complexity is brought to the process.

In order to solve the above technical problems, an embodiment of the present application provides a method for manufacturing a stacked fork plate transistor, so as to simplify a process flow.

In the embodiment of the application, the stacked fork plate transistor can be applied to semiconductor devices such as memories, processors and the like.

In some embodiments, the stacked fork plate transistors may include a front side transistor and a back side transistor. The stacked fork plate transistor comprises a dielectric fork plate structure, wherein the dielectric fork plate structure penetrates through the front active structure of the front transistor and divides the front active structure of the front transistor into two parts which are symmetrically arranged; similarly, the dielectric fork plate structure penetrates through the back active structure of the back transistor, and the back active structure of the back transistor is divided into two parts which are symmetrically arranged.

In some embodiments, since the dielectric fork plate structure penetrates through the front active structure of the front transistor, which is equivalent to penetrating through the active region of the front transistor, the active region of the front transistor is divided into two parts symmetrically disposed at two sides of the dielectric fork plate structure, and due to the separation of the active regions, the front transistor can be divided into two symmetrical transistors, such as a first front transistor and a second front transistor. Likewise, the back side transistor may be divided into two symmetrical transistors, such as a first back side transistor and a second back side transistor.

In the embodiment of the application, the active region is a combination of a source region, a drain region and a channel region.

In some possible embodiments, the dielectric fork plate structure penetrates through the front gate structure of the front-side transistor, and the front gate structure is symmetrically arranged at two sides of the dielectric fork plate structure; the dielectric fork plate structure penetrates through the back grid electrode structure of the back transistor, and the back grid electrode structure is symmetrically arranged on two sides of the dielectric fork plate structure.

It will be appreciated that the dielectric fork plate structure may extend through not only the front side active structure and the back side active structure, but also the front side gate structure and the back side gate structure, where the dielectric fork plate structure is used to isolate the gate structure in the first front side transistor from the gate structure in the second front side transistor, and the dielectric fork plate structure is used to isolate the gate structure in the first back side transistor from the gate structure in the second back side transistor.

In embodiments of the present application, the front side and back side transistors are of a "back-to-back" design and are self-aligned. Wherein the first front side transistor corresponds to a first back side transistor, the first front side transistor and the first back side transistor being self-aligned; likewise, the second front side transistor corresponds to a second back side transistor, the second front side transistor and the second back side transistor being self-aligned.

In the embodiment of the application, the polar types of the first front-side transistor and the second front-side transistor are the same (n-type or p-type), and the polar types of the first back-side transistor and the second back-side transistor are the same (n-type or p-type), so that the step of depositing work function metal (namely a grid structure) can be simplified, and the threshold voltage can be regulated and controlled.

In the embodiment of the application, the front side transistor and the back side transistor in the stacked fork plate transistor can be the same type of transistor, such as any one of the following: nanoflake field effect transistors, fin field effect transistors, planar transistors, and the like. Wherein, as fork plate transistors, the first and second front-side transistors of the front-side transistors may be the same type of transistors (e.g., NFETs or PFETs) or may be different types of transistors (e.g., NFETs and PFETs); accordingly, the first back side transistor and the second back side transistor in the back side transistors may be the same type of transistor or may be different types of transistors; the embodiment of the application does not particularly limit the types of the plurality of transistors in the stacked fork plate transistor.

Fig. 2 is a schematic diagram of a stacked fork transistor formed by a nano-chip field effect transistor, and a method for manufacturing the stacked fork transistor according to an embodiment of the present application is described below with reference to the structure of the stacked fork transistor shown in fig. 2.

Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing a stacked fork transistor according to an embodiment of the present application, and referring to fig. 1, the method for manufacturing a stacked fork transistor may include:

S101, forming an active structure on a substrate.

The active structure comprises a front active structure and a back active structure.

It is appreciated that the front-side active structures in the front-side transistors and the back-side active structures in the back-side transistors may be formed by etching the substrate.

In some embodiments, the substrate may include a top substrate, an intermediate sacrificial layer, and a bottom substrate, which are stacked in this order.

It will be appreciated that the process of preparing the substrate may comprise: a layer of sacrificial layer material is epitaxially grown on an original substrate (namely a bottom substrate) to form an intermediate sacrificial layer; next, a top substrate is formed by epitaxially growing the same semiconductor material as the bottom substrate over the intermediate sacrificial layer. The substrate formed by the preparation method comprises a top substrate, an intermediate sacrificial layer and a bottom substrate which are stacked in sequence. Wherein the top substrate is used for preparing the front-side transistor and the bottom substrate is used for preparing the back-side transistor.

In some embodiments, the material of the intermediate sacrificial layer may be a silicon germanium (SiGe) material, or may be another semiconductor material, which is not particularly limited in this embodiment of the present application.

In some embodiments, when the types of stacked fork plate transistors are different, the arrangement of the substrates is correspondingly different. For example, when the stacked fork plate transistor is any one of a fin field effect transistor and a planar transistor, the bottom substrate and the top substrate may be a silicon (Si) material.

In some embodiments, when the stacked fork plate transistor is a nanoflake field effect transistor, both the top substrate and the bottom substrate are of a stacked configuration (i.e., a stack of alternating depositions of silicon and silicon germanium); at this time, the germanium content in the silicon germanium material used in the top and bottom substrates is different from the germanium content in the silicon germanium material used in the intermediate sacrificial layer (i.e., siGe 1 is used to make the top and bottom substrates and SiGe 2 is used to make the intermediate sacrificial layer). Thus, the selective etching of the intermediate sacrificial layer can be completed in the subsequent preparation process.

In some embodiments, when the stacked fork plate transistor is a nano-plate field effect transistor, the thickness of the silicon layer located at the lowest of the bottom substrate may be greater than the thickness of the other silicon layers in the stack, and the substrate is formed by sequentially depositing material layers of different materials based on the lowest silicon layer of the bottom substrate (see (a) in fig. 3A).

In some embodiments, the height of the top substrate may be designed according to practical requirements, such as 50nm, the height of the bottom substrate is greater than the top substrate, and the height of the intermediate sacrificial layer is less than the height of the top substrate.

In the embodiment of the application, the active region of the front-side transistor and the active region of the back-side transistor are self-aligned because the front-side active structure and the back-side active structure are formed by the same process; the self-alignment of the active region further causes the front-side and back-side transistors to also be self-aligned.

And S102, forming a front-side transistor based on the front-side active structure.

The front-side transistor comprises a front-side grid structure, a front-side source-drain structure and a front-side metal interconnection layer.

It will be appreciated that after the front-side active structure and the back-side active structure are formed, the front-side active structure is placed up and the back-side active structure is placed down. Other structures in the front side transistor (e.g., front side source drain structure, front side interlayer dielectric layer, front side gate structure, front side metal interconnect layer, etc.) may be formed based on the front side active structure.

S103, rewinding and removing the substrate.

It will be appreciated that after the front side transistor is formed, the back side active structure is exposed by a reverse process to place the lowermost silicon layer in the bottom substrate upward and then removing the lowermost silicon layer in the bottom substrate before the back side transistor is fabricated.

In some possible embodiments, before the step S103, the method may further include: depositing an insulating material on the surface of the front-side transistor to form an insulating layer; and bonding the insulating layer with the carrier wafer.

It can be appreciated that the bonded carrier wafer can provide physical support for the inverted front-side transistor after rewinding, so as to effectively prevent the front-side transistor from being broken due to external force in the process of preparing the back-side transistor.

And S104, forming a back dummy gate structure or a back gate structure, a back source drain structure and a back interlayer dielectric layer of the back transistor based on the back active structure.

It can be appreciated that after the back active structure is placed up, the back gate region of the back transistor can be opened by photolithography, and an insulating material is deposited in the back gate region to form a back dummy gate structure, and a back source drain structure based on the back active structure, according to standard steps for preparing the transistor; then, depositing an insulating material on the back source drain structure and the back active structure to form a back interlayer dielectric layer; and then forming a back gate structure by removing the back dummy gate structure.

In one example, after the back active structure is formed and placed up, the back gate region of the back transistor is opened by a photolithographic process, and polysilicon is deposited in the back gate region to form a back dummy gate structure. And depositing an insulating material on the surface of the back dummy gate structure to form a back spacer. A portion of the back side active structure is removed by etching to provide a source drain recess for the back side transistor. And forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the back transistor by using the back spacer as a mask through selective epitaxial growth so as to fill the source-drain groove of the back transistor, and then forming a back source-drain structure on the strained material through a heavy doping process. Next, an insulating material (e.g., silicon dioxide (SiO ₂)) is deposited over the back-side active structure and the back-side source-drain structure to form a back-side interlayer dielectric layer, which may cover the back-side active structure and the back-side source-drain structure.

And S105, sequentially carrying out photoetching on the back dummy gate structure or the back gate structure, the back source drain structure, the back active structure, the front source drain structure, the front active structure and the front gate structure to form a first groove.

The first groove penetrates through the front active structure and the back active structure, the front active structure is divided into two parts which are symmetrically arranged by the first groove, and the back active structure is divided into two parts which are symmetrically arranged by the first groove.

It will be appreciated that both the back dummy gate structure and the back gate structure are located in the back gate region, with the back dummy gate structure being formed before the back gate structure. The back gate structure may be formed by removing the back dummy gate structure, exposing the back gate region, and then depositing a metal material in the back gate region. Based on this, when the first recess is formed by the photolithography process, it is possible to select to perform photolithography after forming the back dummy gate structure or to perform photolithography after forming the back gate structure according to process requirements. The first groove formed by photoetching penetrates through the back interlayer dielectric layer, the back dummy gate structure or the back gate structure, the back source drain structure, the back active structure, the shallow groove isolation layer, the middle isolation layer, the front source drain structure, the front active structure, the front interlayer dielectric layer and the front gate structure. The first groove not only divides the front active structure into two parts which are symmetrically arranged, but also divides the back interlayer dielectric layer, the back dummy gate structure or the back gate structure, the back source drain structure, the back active structure, the shallow groove isolation layer, the middle isolation layer, the front source drain structure, the front interlayer dielectric layer and the front gate structure into two parts which are symmetrically arranged respectively.

And S106, depositing dielectric materials in the first grooves to form the dielectric fork plate structure.

It will be appreciated that depositing a dielectric material in the first recess may form a dielectric fork plate structure extending through the front side transistor and the back side transistor. The dielectric fork plate structure divides the front side transistor into a first front side transistor and a second front side transistor which are symmetrically arranged, and divides the back side transistor into a first back side transistor and a second back side transistor which are symmetrically arranged.

In the embodiment of the present application, the dielectric material forming the dielectric fork plate structure may be any one of the following materials: alumina, zirconia, silicon nitride, and the like.

And S107, forming a back metal interconnection layer of the back transistor.

It can be appreciated that in the case of performing photolithography after forming the back dummy gate structure, the back dummy gate structure may be removed after forming the dielectric fork plate structure, then the back gate structure may be formed, and then a back metal interconnection layer may be formed on the back gate structure and the back interlayer dielectric layer; in the case of photolithography after formation of the back gate structure, a back metal interconnect layer may be formed on the back gate structure and the back interlayer dielectric layer after formation of the dielectric fork plate structure.

In some possible embodiments, the step S105 may include: coating photoresist on the back dummy gate structure or the back gate structure; and after developing the photoresist, sequentially etching the back dummy gate structure or the back gate structure, the back source drain structure, the back active structure, the front source drain structure, the front active structure and the front gate structure by using the photoresist as a mask to form a first groove.

It will be appreciated that the first recess is formed by lithography and, as such, the position of the first recess may be determined in accordance with the lithographic pattern.

In one example, photoresist is coated on the back interlayer dielectric layer, the back dummy gate structure or the back gate structure, and after the photoresist is developed and a photolithography pattern is formed, the back interlayer dielectric layer, the back dummy gate structure or the back gate structure, the back source drain structure, the back active structure, the shallow trench isolation layer, the middle isolation layer, the front source drain structure, the front active structure, the front gate structure and the front interlayer dielectric layer are etched according to the photolithography pattern to form the first groove.

In some possible embodiments, the step S101 may include: depositing a hard mask material in a first region on a substrate to form a hard mask structure; the hard mask structure is arranged on the surface of the substrate in a centered manner and covers a part of the surface of the substrate; and etching the substrate by taking the hard mask structure as a mask to form a front active structure and a back active structure.

In the embodiment of the present application, the hard mask material for forming the hard mask structure may be any of the following: silicon nitride (SiN), silicon dioxide (SiO 2), titanium nitride (TiN), and the like.

In one example, a hard mask material is deposited on a substrate to form a hard mask layer; coating photoresist on the hard mask layer, developing the photoresist, and photoetching the hard mask layer to form a hard mask structure; the hard mask structure overlies a portion of the substrate and is centrally disposed on the substrate. After the hard mask structure is formed, etching the substrate by taking the hard mask structure as a mask, stopping etching until the etching is stopped on the lowest silicon layer of the bottom substrate, wherein the substrate which is not etched is a front active structure and a back active structure; the substrate above the middle sacrificial layer is a front active structure, and the substrate below the middle sacrificial layer is a back active structure.

In some possible embodiments, the step S102 may include: forming a front dummy gate structure, a front spacer, a front source drain structure and a front interlayer dielectric layer of the front transistor in sequence based on the front active structure; removing the front side dummy gate structure to expose a front side gate region of the front side transistor; depositing a metal material in the front gate region to form a front gate structure; and performing a subsequent process on the front-side interlayer dielectric layer to form a front-side metal interconnection layer of the front-side transistor.

It will be appreciated that after the front-side active structure is formed, other structures in the front-side transistor (e.g., front-side dummy gate structures, front-side spacers, front-side source drain structures, front-side interlayer dielectric layers, front-side metal interconnect layers, etc.) may be fabricated according to standard steps for fabricating the transistor.

In one example, after the front-side active structure is formed, the front-side gate region of the front-side transistor is opened by a photolithographic process, and polysilicon is deposited in the front-side gate region to form a front-side dummy gate structure. And depositing an insulating material on the surface of the front dummy gate structure to form a front spacer. A portion of the front-side active structure is removed by etching to provide a source drain recess for the front-side transistor. And forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the front transistor by using the front spacer as a mask through selective epitaxial growth so as to fill the source-drain groove of the front transistor, and then forming a front source-drain structure on the strained material through a heavy doping process. And then, depositing insulating materials (such as silicon dioxide (SiO ₂)) on the front-side active structure and the front-side source drain structure to form a front-side interlayer dielectric layer, wherein the front-side interlayer dielectric layer can cover the front-side active structure and the front-side source drain structure. And removing the front dummy gate structure to expose the front gate region. And removing the silicon germanium material layer in the front active structure, wherein the front active structure after the silicon germanium material layer is removed is a plurality of nano-sheet structures. An insulating material is deposited on the surface of the nano-sheet structure in the front gate region to form a front gate dielectric layer. And filling a metal material in the front grid region to form the front grid structure. And performing dielectric deposition, metal line formation, lead-out pad formation and the like among the interconnection lines on the front interlayer dielectric layer to form a front metal interconnection layer of the front transistor.

In an embodiment of the present application, materials used to prepare the front side dummy gate structure and the back side dummy gate structure may include, but are not limited to: polysilicon (poly Si), amorphous silicon, and the like.

In some possible embodiments, after forming the back dummy gate structure, forming the back gate structure may include: removing the back dummy gate structure to expose a back gate region of the back transistor; a metal material is deposited in the back gate region to form a back gate structure.

In some possible embodiments, after forming the back gate structure, the step S107 may include: and performing a back process on the back interlayer dielectric layer and the back gate structure to form a back metal interconnection layer of the back transistor.

It will be appreciated that after the dielectric fork plate structure is formed, other structures in the back side transistor (e.g., back side gate structure, back side gate dielectric layer, back side metal interconnect layer, etc.) may be formed in accordance with standard procedures for fabricating transistors.

In one example, the back dummy gate structure is removed, the back gate region is exposed, and the silicon germanium material layer in the back active structure is removed, the back active structure after the silicon germanium material layer is removed being a plurality of nano-sheet structures. An insulating material is deposited on the surface of the nanoplatelet structure in the back gate region to form a back gate dielectric layer. And filling a metal material in the back gate region to form a back gate structure. And performing dielectric deposition, metal line formation, lead-out pad formation and the like among the interconnection lines on the back interlayer dielectric layer to form a back metal interconnection layer of the back transistor.

In some possible embodiments, before the step S102, the method may further include: depositing an insulating material on the substrate to form a shallow trench isolation structure; the shallow slot isolation structure wraps the front active structure, the middle sacrificial layer and the back active structure; a portion of the shallow trench isolation structure surrounding the front-side active structure is removed to expose the front-side active structure.

It is appreciated that after forming the front-side active structure and the back-side active structure, an insulating material is deposited over the front-side active structure and the back-side active structure, and CMP is performed, with CMP stopping to a surface of the front-side active structure remote from the back-side active structure, to form a shallow trench isolation structure (shallow trench isolation, STI) that encapsulates the front-side active structure and the back-side active structure. And then, removing a part of the shallow trench isolation structure which wraps the front-side active structure, and exposing the front-side active structure so as to prepare the front-side transistor in the subsequent process.

In some possible embodiments, after forming the front-side dummy gate structure, the method may further include: removing the intermediate sacrificial layer to form a second groove; an insulating material is deposited in the second recess to form an intermediate isolation layer.

The middle isolation layer is used for isolating the front active structure and the back active structure.

It will be appreciated that the intermediate sacrificial layer is removed after the front-side dummy gate structure is formed, so that the front-side dummy gate structure can support the front-side active structure to prevent the front-side active structure from collapsing during the removal of the intermediate sacrificial layer. And removing the intermediate sacrificial layer to form a second groove positioned between the front active structure and the back active structure, and filling insulating materials in the second groove to form an intermediate isolation layer.

The middle isolation layer and the front spacer may be made of the same insulating material, and further, the middle isolation layer and the front spacer may be formed in the same process.

In some possible embodiments, after the step S103, the method may further include: and removing the part of the shallow trench isolation structure wrapping the back active structure to expose the back active structure and forming a shallow trench isolation layer.

It will be appreciated that before the back side transistor is fabricated, the back side active structure needs to be exposed, the shallow trench isolation structure may be removed by etching, and during the etching process, the shallow trench isolation structure with a predetermined thickness is reserved, and the reserved portion of the shallow trench isolation structure (i.e., the shallow trench isolation layer) is located between the front side transistor and the back side transistor. The shallow trench isolation layer is used to isolate the front side transistor from the back side transistor.

In the embodiment of the application, the front side transistor is prepared before the film is rewound, the back side transistor is prepared after the film is rewound, namely, the active area and the front side grid structure of the front side transistor are formed before the film is rewound, and the active area and the back side grid structure of the back side transistor are formed after the film is rewound, so that the front side transistor and the back side transistor can be respectively and independently manufactured, and the process optimization of the front side transistor and the back side transistor is realized.

It should be noted that, the front-side source-drain structure represents a source and/or a drain in the front-side transistor, and correspondingly, other expressions related to "source-drain" in the embodiments of the present application are used to represent "source and/or drain", for example: a back source drain structure, a front source drain inner side wall, a back source drain inner side wall and the like.

In the following, a front-side transistor and a back-side transistor are taken as examples of nano-chip field effect transistors, and the stacked fork-plate transistor provided by the embodiment of the application is described. Fig. 2 is a schematic structural diagram of a stacked fork-plate transistor according to an embodiment of the present application. In fig. 2, (a) is a design layout of the stacked fork plate transistor, and for convenience of understanding, only a nano-sheet structure, a gate structure and a source-drain structure are shown in the design layout; (b) Cut-away views of stacked fork-plate transistors taken along the cut-away direction (i.e., the A-A' direction) of the gate structure; (c) A cross-sectional view of the stacked fork plate transistor along a cross-sectional direction (i.e., the B-B' direction) of the source-drain structure; (d) Cut-away views of stacked fork-plate transistors are made along the cut-away direction (i.e., the C-C' direction) of the nanoplate structure.

Referring to fig. 2, stacked fork plate transistors include front side transistors, back side transistors, and dielectric fork plate structures. The front side transistor comprises a first front side transistor and a first back side transistor, the back side transistor comprises a second front side transistor and a second back side transistor, the first front side transistor and the first back side transistor are self-aligned, and the second front side transistor and the second back side transistor are self-aligned; the first front-side transistor and the second front-side transistor are symmetrically arranged on two sides of the dielectric fork plate structure, and the first back-side transistor and the second back-side transistor are symmetrically arranged on two sides of the dielectric fork plate structure. The dielectric fork plate structure penetrates through the front active structure and the back active structure, divides the front active structure into two symmetrically arranged parts, and divides the back active structure into two symmetrically arranged parts.

The process of manufacturing the stacked fork-plate transistor 10 shown in fig. 2 will be described below in connection with the above manufacturing method. The stacked fork-plate transistor 10 shown in fig. 2 can be prepared by the process shown in fig. 3A to 3E, and fig. 3A to 3E are schematic views of a preparation process of the stacked fork-plate transistor according to an embodiment of the present application.

In an example where stacked fork plate transistor 10 is a nano-plate field effect transistor and a dielectric fork plate structure is formed after the formation of the back side dummy gate structure, a first fabrication process of stacked fork plate transistor 10 may include the steps of:

It should be noted that the different steps (i.e., different processes) in the following examples may show the manufacturing process of the stacked fork plate transistor 10 with A-A ' direction, B-B ' direction, C-C ' direction, or different combinations of the above directions, respectively, according to the structural changes.

The first step: a substrate 21 is provided (see (a) in fig. 3A).

The preparation method of the substrate 21 comprises providing a Si layer, alternately depositing SiGe 1 material and Si material on the Si layer to form a laminated layer with a preset thickness, wherein the laminated layer is a bottom substrate 211; next, a SiGe 2 material is deposited on the bottom substrate 211, forming an intermediate sacrificial layer 212; finally, siGe 1 material and Si material are alternately deposited on the intermediate sacrificial layer 212 to form a stack of a predetermined thickness, which is a top substrate 213.

And a second step of: depositing a hard mask material on the top substrate 213, forming a hard mask layer covering an upper surface (not shown) of the top substrate 213; next, a photoresist is coated on the above hard mask layer, and after the photoresist is developed, a portion of the hard mask layer is removed by photolithography, and finally a hard mask structure 22 is formed, the hard mask structure 22 being centrally disposed on the top substrate 213 (see (b) in fig. 3A).

And a third step of: the top substrate 213, the intermediate sacrificial layer 212, and the bottom substrate 211 are sequentially etched using the hard mask structure 22 as a mask, and the etching is stopped to the upper surface of the lowermost substrate of the bottom substrate 211, forming the front active structure 111 and the rear active structure 121 (see (c) in fig. 3A).

Fourth step: the hard mask structure 22 is removed and an insulating material is deposited on the top substrate 213 and on the lowermost substrate of the bottom substrate 211, and a CMP process is performed, which stops on the surface of the front-side active structure 111 remote from the back-side active structure 121, forming a shallow trench isolation structure 23 (see (d) in fig. 3A).

Wherein shallow trench isolation structure 23 wraps around front side active structure 111, intermediate sacrificial layer 212 and back side active structure 121.

Fifth step: the shallow trench isolation structure 23 surrounding the front-side active structure 111 and the intermediate sacrificial layer 212 is removed by etching, exposing the front-side active structure 111 (see (e) in fig. 3A).

As shown in (a) to (e) of fig. 3A, the fabrication process of the stacked fork plate transistor 10 is shown in the A-A' direction.

Sixth step: the front-side gate region of the front-side transistor 11 is opened by photolithography and polysilicon is deposited in the front-side gate region to form a front-side dummy gate structure 311 of the front-side transistor 11 (see (a) in fig. 3B).

Seventh step: under the supporting action of the front dummy gate structure 311, the intermediate sacrificial layer 212 is removed to form a groove (i.e., a second groove) (not shown in the figure); next, an insulating material is deposited in the second recess and on the sidewalls of the front dummy gate structure 311 to form the intermediate isolation layer 32 and the front spacers 112 (see (B) in fig. 3B).

Eighth step: the front-side source drain inner side walls 331 and the front-side source drain structures 113 are grown following standard procedures (see (c) in fig. 3B).

Wherein, as shown in (a) and (B) in fig. 3B, the fabrication process of the stacked fork plate transistor 10 is shown in the A-A 'direction and the C-C' direction; as shown in (C) of fig. 3B, the fabrication process of the stacked fork plate transistor 10 is shown in the B-B 'direction and the C-C' direction.

Ninth step: depositing an insulating material on the front-side source drain structure 113 to form a front-side interlayer dielectric layer 114; removing the front dummy gate structure 311 to expose the front gate region; removing the SiGe 1 material layer in the front-side active structure 111 (the front-side active structure 111 after the SiGe 1 material layer is removed is a nano-sheet structure); depositing an insulating material on the surface of the front-side active structure 111 to form a front-side gate dielectric layer 115; depositing a metal material in the front gate region to form a front gate structure 116; a subsequent process is performed over the front side interlayer dielectric layer 114 and the front side gate structure 116 to form a front side metal interconnect layer 117 (see (a) in fig. 3C).

Tenth step: depositing an insulating material on the front side metal interconnect layer 117 to form an insulating layer 13; bonding the carrier wafer 14 to the insulating layer 13; the front-side transistor 11 is rewound so that the bottom substrate 211 is placed upward (see (b) in fig. 3C).

Eleventh step: the lowermost Si layer of the bottom substrate 211 is removed by a wafer thinning process and a CMP process (see (C) in fig. 3C).

Wherein, as shown in (a) to (C) of fig. 3C, the fabrication process of the stacked fork plate transistor 10 is shown in the A-A 'direction and the C-C' direction.

Twelfth step: removing the shallow trench isolation structure 23 wrapping the back active structure 121 to expose the back active structure 121 and form a shallow trench isolation layer 231; based on the back active structure 121, a back dummy gate structure 312, a back spacer 122, a back source drain sidewall spacer 332, a back source drain structure 123, and a back interlayer dielectric layer 124 in the back transistor 12 are formed (see (a) in fig. 3D) (see sixth to ninth steps for specific processes).

Thirteenth step: photoresist (not shown) is coated on the back dummy gate structure 312 and the back interlayer dielectric layer 124, and after the photoresist is developed, the back interlayer dielectric layer 124, the back dummy gate structure 312, the back active structure 121, the shallow trench isolation layer 231, the intermediate isolation layer 32, the front active structure 111, the front interlayer dielectric layer 114 and the front gate structure 116 are etched by photolithography to form the first recess 34; next, the photoresist is removed (see (b) in fig. 3D).

Fourteenth step: a dielectric material is deposited in the first recess 34 forming a dielectric fork plate structure 35 (see (c) in fig. 3D).

Wherein, as shown in (a) to (C) of fig. 3D, the fabrication process of the stacked fork plate transistor 10 is shown in A-A ', B-B ' and C-C ' directions.

Fifteenth step: removing the back dummy gate structure 312, exposing the back gate region; removing the SiGe 1 material layer in the back-side active structure 121 (the back-side active structure 121 after the SiGe 1 material layer is removed is a nano-sheet structure); depositing an insulating material on the surface of the back active structure 121 to form a back gate dielectric layer 125; a metal material is deposited in the back gate region to form a back gate structure 126 (see fig. 3E). A back-side process is performed on the back-side gate structure 126 and the back-side interlayer dielectric layer 124 to form a back-side metal interconnect layer 127 (see fig. 2 for specific structure).

Thus, the stacked fork-plate transistor 10 in which the front-side transistor 11 and the back-side transistor 12 are nanoflake field-effect transistors is completed as described above.

In the case of the A-A' direction (refer to the (b) diagram in fig. 2), the first front side transistor and the second front side transistor are used to represent transistors distributed on both sides of the dielectric fork structure, and the present application is not limited to the positions of the first front side transistor and the second front side transistor in the front side transistors. For example, the first front side transistor may be located on the left or right side of the dielectric fork plate structure, and the second front side transistor may be located on the right or left side of the dielectric fork plate structure, respectively.

Wherein, since the dielectric fork plate structure is formed in the process of preparing the back side transistor (i.e. after forming the back side dummy gate structure and the back side source drain structure), as shown in fig. 2, the dielectric fork plate structure has an inverted trapezoid shape (the short side is under and the long side is over).

In the embodiment of the application, after the front-side transistor, the back-side pseudo gate structure and the back-side source drain structure of the back-side transistor are formed, the dielectric fork plate structure is formed, so that the influence of the CMOS technology on the dielectric fork plate structure can be reduced in the process of preparing the stacked fork plate transistor, and the technological process is further simplified.

Further, the combination of the stacked transistor and the fork plate transistor can reduce the space between the symmetrically placed devices on two sides of the dielectric fork plate structure, and improve the integration density of the transistor.

Further, the stacked fork plate transistor provided by the embodiment of the application can be detected by using a detection analysis instrument, for example: scanning electron microscope (scanning electron microscope, SEM), transmission electron microscope (transmission electron microscope, TEM), scanning transmission electron microscope (scanning transmission electron microscopy, STEM), and the like. Taking a TEM as an example, the stacked fork plate transistor provided in the embodiment of the present application may detect the structure of the stacked fork plate transistor by adopting a TEM slicing manner, for example, the active areas of the front side transistor and the back side transistor are self-aligned, the front side transistor is divided into a first front side transistor and a second front side transistor which are symmetrically arranged by the dielectric fork plate structure, and the back side transistor is divided into a first back side transistor and a second back side transistor which are symmetrically arranged by the dielectric fork plate structure and a dielectric fork plate structure which is in an inverted trapezoid shape.

An embodiment of the present application provides a semiconductor device including: stacked fork plate transistors as in the above embodiments. For specific limitation of the stacked fork transistor, reference may be made to the stacked fork transistor shown in fig. 2 and will not be described herein.

An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device includes the stacked fork plate transistor described above. For specific limitation of the stacked fork transistor, reference may be made to the stacked fork transistor shown in fig. 2 and will not be described herein.

In the description of the present application, a description of the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (11)

1. A method of making a stacked fork plate transistor, the method comprising:

Forming an active structure on a substrate; the active structure comprises a front active structure and a back active structure;

Forming a front-side transistor based on the front-side active structure; the front-side transistor comprises a front-side grid structure, a front-side source-drain structure and a front-side metal interconnection layer;

rewinding and removing the substrate;

forming a back dummy gate structure or a back gate structure, a back source drain structure and a back interlayer dielectric layer of the back transistor based on the back active structure;

Photoetching the back dummy gate structure or the back gate structure, the back source drain structure, the back active structure, the front source drain structure, the front active structure and the front gate structure in sequence to form a first groove; the first groove penetrates through the front active structure and the back active structure, the first groove divides the front active structure into two symmetrically arranged parts, and the first groove divides the back active structure into two symmetrically arranged parts;

Depositing a dielectric material in the first groove to form a dielectric fork plate structure;

forming a back metal interconnection layer of a back transistor; the front side transistor and the back side transistor are self-aligned.

2. The method of claim 1, wherein the sequentially photolithography the back dummy gate structure or back gate structure, the back source drain structure, the back active structure, the front source drain structure, the front active structure, and the front gate structure to form the first recess comprises:

coating photoresist on the back dummy gate structure or the back gate structure;

And after the photoresist is developed, sequentially etching the back dummy gate structure or the back gate structure, the back source drain structure, the back active structure, the front source drain structure, the front active structure and the front gate structure by taking the photoresist as a mask to form the first groove.

3. The method of claim 1, wherein forming an active structure on a substrate comprises:

Depositing a hard mask material in a first region on the substrate to form a hard mask structure; the hard mask structure is arranged on the surface of the substrate in a centering way and covers a part of the surface of the substrate;

And etching the substrate by taking the hard mask structure as a mask to form the front active structure and the back active structure.

4. The method of claim 1, wherein forming a front-side transistor based on the front-side active structure comprises:

forming a front dummy gate structure, a front gap wall, a front source drain structure and a front interlayer dielectric layer of the front transistor in sequence based on the front active structure;

Removing the front-side dummy gate structure to expose a front-side gate region of the front-side transistor;

depositing a metal material in the front gate region to form a front gate structure;

And performing a subsequent process on the front-side interlayer dielectric layer and the front-side grid structure to form a front-side metal interconnection layer of the front-side transistor.

5. The method of claim 1, wherein after forming the back side dummy gate structure, the forming the back side gate structure comprises: removing the back dummy gate structure to expose a back gate region of the back transistor; depositing a metal material in the back gate region to form the back gate structure;

After forming the back gate structure, the forming a back metal interconnect layer includes: and performing a back process on the back interlayer dielectric layer and the back gate structure to form a back metal interconnection layer of the back transistor.

6. The method of claim 1, wherein the substrate comprises a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in this order, the top substrate being used to form the front-side active structure, the bottom substrate being used to form the back-side active structure;

Before the forming of the front-side transistor based on the front-side active structure, the method further comprises:

Depositing an insulating material on the substrate to form a shallow trench isolation structure; the shallow slot isolation structure wraps the front active structure, the middle sacrificial layer and the back active structure;

And removing a part of the shallow trench isolation structure, which wraps the front-side active structure, so as to expose the front-side active structure.

7. The method of claim 6, wherein the method further comprises:

Removing the intermediate sacrificial layer to form a second groove;

Depositing an insulating material in the second recess to form an intermediate isolation layer; the intermediate isolation layer is used for isolating the front active structure and the back active structure.

8. A stacked fork plate transistor, comprising:

a front side transistor;

A back side transistor; the front side transistor and the back side transistor are self-aligned;

a dielectric fork plate structure; the dielectric fork plate structure penetrates through the front active structure of the front transistor and the back active structure of the back transistor, the dielectric fork plate structure divides the front active structure into two parts which are symmetrically arranged, and the dielectric fork plate structure divides the back active structure into two parts which are symmetrically arranged.

9. The stacked fork plate transistor of claim 8, wherein,

The dielectric fork plate structure penetrates through the front grid structure of the front transistor, and divides the front grid structure into two parts which are symmetrically arranged;

The dielectric fork plate structure penetrates through the back gate structure of the back transistor, and divides the back gate structure into two parts which are symmetrically arranged.

10. A semiconductor device, comprising: the stacked fork plate transistor of claim 8.

11. An electronic device, comprising: a circuit board and the semiconductor device according to claim 10, the semiconductor device being provided to the circuit board.