CN118315343A

CN118315343A - Method for preparing semiconductor structure, device and equipment

Info

Publication number: CN118315343A
Application number: CN202410442420.9A
Authority: CN
Inventors: 吴恒; 彭莞越; 葛延栋; 卢浩然; 王润声; 黎明; 黄如
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2024-04-12
Filing date: 2024-04-12
Publication date: 2024-07-09

Abstract

The application provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment, wherein the method comprises the following steps: forming an active structure on a substrate; depositing an insulating material on the active structure to form a shallow trench isolation structure; forming a hard mask layer on the shallow trench isolation structure, and etching the shallow trench isolation structure by taking the hard mask layer as a mask to form a grid groove; depositing a semiconductor material in the gate recess to form an initial dummy gate structure; the first dummy gate structure and the second dummy gate structure are self-aligned; removing a portion of the shallow trench isolation structure surrounding the first active structure to expose the first active structure; forming a first transistor based on the first active structure; rewinding and removing the substrate; removing a portion of the shallow trench isolation structure surrounding the second active structure to expose the second active structure; a second transistor is formed based on the second active structure. By the application, the process flow can be optimized.

Description

Method for preparing semiconductor structure, device and equipment

Technical Field

The present application relates to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor structure, a device, and equipment.

Background

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors further increase transistor integration density by integrating two or more layers of transistors in vertical space is one of the important technologies continuing the scaling of integrated circuits.

When a conventional monolithic scheme is used for preparing a stacked transistor, the following technical difficulties exist: the dummy gate recrystallization causes a complication in the process flow.

Disclosure of Invention

The application provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment, so as to optimize the process flow.

In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, where the method includes: forming an active structure on a substrate; the active structure comprises a first active structure and a second active structure; depositing an insulating material on the active structure to form a shallow trench isolation structure; the shallow slot isolation structure wraps the active structure; forming a hard mask layer on the shallow trench isolation structure, and etching the shallow trench isolation structure by taking the hard mask layer as a mask to form a grid groove; depositing a semiconductor material in the gate recess to form an initial dummy gate structure; the initial dummy gate structure includes a first dummy gate structure corresponding to the first active structure and a second dummy gate structure corresponding to the second active structure, the first dummy gate structure and the second dummy gate structure being self-aligned; removing a portion of the shallow trench isolation structure surrounding the first active structure to expose the first active structure; forming a first transistor based on the first active structure; rewinding and removing the substrate; removing a portion of the shallow trench isolation structure surrounding the second active structure to expose the second active structure; forming a second transistor based on the second active structure; the first transistor and the second transistor are self-aligned.

In some possible embodiments, a first gate isolation layer is disposed between the first dummy gate structure and the second dummy gate structure; the gate grooves comprise a first gate groove corresponding to the first active structure and a second gate groove corresponding to the second active structure; depositing semiconductor material in the gate recess to form an initial dummy gate structure, comprising: depositing a semiconductor material in the second gate recess to form a second dummy gate structure; depositing an oxide on the second dummy gate structure to form a first gate isolation layer; the first gate isolation layer is used for isolating the first pseudo gate structure and the second pseudo gate structure; a semiconductor material is deposited on the first gate isolation layer to form a first dummy gate structure.

In some possible embodiments, forming a first transistor based on the first active structure includes: forming a first source drain structure and a first interlayer dielectric layer based on the first active structure; removing the first pseudo gate structure, depositing an insulating material on the surface of the first active structure in the first gate groove, and depositing a metal material in the first gate groove to form a first gate dielectric layer and a first gate structure; and performing subsequent process treatment on the first gate structure and the first interlayer dielectric layer to form a first metal interconnection layer.

In some possible embodiments, forming a second transistor based on the second active structure includes: forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure; removing the second pseudo gate structure, depositing an insulating material on the surface of the second active structure in the second gate groove, and depositing a metal material in the second gate groove to form a second gate dielectric layer and a second gate structure; and performing subsequent process treatment on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

In some possible embodiments, the first dummy gate structure and the second dummy gate structure are formed through one process, and the gate recess includes a first gate recess corresponding to the first active structure and a second gate recess corresponding to the second active structure; depositing semiconductor material in the gate recess to form an initial dummy gate structure, comprising: depositing semiconductor material in the second gate recess and the first gate recess to form a second dummy gate structure and a first dummy gate structure; the second dummy gate structure and the first dummy gate structure are integrally provided.

In some possible embodiments, forming a first transistor based on the first active structure includes: forming a first source drain structure and a first interlayer dielectric layer based on the first active structure; and performing subsequent process treatment on the first pseudo gate structure and the first interlayer dielectric layer to form a first metal interconnection layer.

In some possible embodiments, forming a second transistor based on the second active structure includes: forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure; removing the first dummy gate structure and the second dummy gate structure to expose the gate recess; depositing an insulating material on the surface of the active structure in the gate groove to form a gate dielectric layer; depositing a metal material in the first gate recess and the second gate recess to form a first gate structure of the first transistor and a second gate structure of the second transistor; the first grid structure and the first grid structure are integrally arranged; and performing subsequent process treatment on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

In some possible embodiments, forming a second transistor based on the second active structure includes: forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure; removing the first and second dummy gate structures to expose the first and second gate recesses; depositing an insulating material on the surface of the active structure in the gate groove to form a gate dielectric layer; depositing a metal material in the first gate recess and the second gate recess, respectively, to form a first gate structure of the first transistor and a second gate structure of the second transistor; and performing subsequent process treatment on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

In some possible embodiments, depositing a metal material in the first gate recess and the second gate recess, respectively, to form a first gate structure of the first transistor and a second gate structure of the second transistor, includes: depositing a metal material in the first gate recess to form a first gate structure; depositing an oxide on the first gate structure to form a second gate isolation layer; the second gate isolation layer is used for isolating the first gate structure and the second gate structure; a metal material is deposited on the second gate spacer to form a second gate structure.

In some possible embodiments, the substrate includes a top substrate, a first sacrificial layer, and a bottom substrate in a stacked arrangement, the top substrate being used to form the active structure; forming an active structure on a substrate, comprising: etching the top substrate and the first sacrificial layer to form an active structure and a second sacrificial layer; the second sacrificial layer is connected with the bottom substrate and the active structure; after rewinding and removing the substrate, the method further comprises: removing the bottom substrate and the second sacrificial layer to form a first groove; filling semiconductor material in the first groove to form a pseudo gate structure; the dummy gate structure wraps the active structure in the gate recess.

In a second aspect, an embodiment of the present application provides a semiconductor structure, including: a first transistor; a second transistor; the first transistor and the second transistor are stacked and self-aligned; the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

In some possible embodiments, the first gate structure and the second gate structure are integrally provided; or, a gate isolation layer is arranged between the first gate structure and the second gate structure, and is used for isolating the first gate structure and the second gate structure.

In a third aspect, an embodiment of the present application provides a semiconductor device including: such as the semiconductor structures of the above embodiments.

In a fourth aspect, an embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board.

In the application, the shallow slot isolation structure is formed first, and then the process sequence of the first pseudo gate structure and the second pseudo gate structure is formed, so that the first pseudo gate structure and the second pseudo gate structure can be prevented from being recrystallized, and the process flow is optimized.

Further, since the first dummy gate structure and the second dummy gate structure are formed before the first transistor is reworked, the first dummy gate structure and the second dummy gate structure are self-aligned, and thus the first gate structure and the second gate structure formed based on the first dummy gate structure and the second dummy gate structure are also self-aligned.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a first structure of a semiconductor structure according to an embodiment of the present application;

FIGS. 3A-3G are schematic diagrams illustrating a first process for fabricating a semiconductor structure according to embodiments of the present application;

FIG. 4 is a schematic diagram of a second structure of a semiconductor structure according to an embodiment of the present application;

FIGS. 5A and 5B are schematic diagrams illustrating a second process for fabricating a semiconductor structure according to embodiments of the present application;

FIG. 6 is a schematic diagram of a third structure of a semiconductor structure according to an embodiment of the present application;

FIG. 7 is a schematic diagram illustrating a third process for fabricating a semiconductor structure according to an embodiment of the present application;

The figures above:

10. A semiconductor structure; 11. a first transistor; 111. a first active structure; 112. a first gate structure; 113. a first spacer; 114. a first source drain structure; 115. a first interlayer dielectric layer; 116. a first gate dielectric layer; 117. a first metal interconnect layer; 12. a second transistor; 121. a second active structure; 122. a second gate structure; 123. a second spacer; 124. a second source drain structure; 125. a second interlayer dielectric layer; 126. a second gate dielectric layer; 127. a second metal interconnect layer; 13. a first gate isolation layer; 14. a second gate isolation layer; 15. an insulating layer; 16. a carrier wafer; 21. a substrate; 211. a top substrate; 212. a first sacrificial layer; 213. a base substrate; 214. a second sacrificial layer; 22. shallow trench isolation structure; 221. shallow groove isolation layer; 23. a hard mask layer; 24. a gate groove; 241. a first gate recess; 242. a second gate groove; 25. oxidizing the isolation layer; 261. a first dummy gate structure; 262. a second dummy gate structure; 31. a first groove.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.

While moore's law is continually deepening, continuing to advance transistor scaling after the technology node of the full-round gate transistor (GAA) is a hot spot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits.

In one embodiment, the technique for fabricating stacked transistors includes two schemes, one is a monolithic scheme (monolithic) and the other is a sequential scheme (sequential).

In the first approach, N-channel field effect transistors (N FIELD EFFECT transistors, NFETs) and P-channel field effect transistors (P FIELD EFFECT transistors, PFETs) are fabricated on the same substrate, and wafer bonding techniques are not used. This determines that the same layer transistors must be of the same type, i.e., NFET or PFET. And the transistors on the upper layer and the lower layer are strictly in the same plane space, and no alignment deviation exists. The advantage of this solution is a better integration density. Drawbacks of this approach include the following two points: (1) The process is complex, and a large number of process technologies need to be developed and optimized; (2) Each layer of transistors has a fixed polarity, and two layers of transistors must be relied upon to form a basic Complementary Metal Oxide Semiconductor (CMOS) circuit, which has poor design flexibility.

The second scheme is based on wafer bonding and layer-by-layer processing. Specifically, the two transistors are stacked vertically by bonding a wafer on top of the fabricated lower transistor to prepare the upper transistor. However, this approach requires tight temperature control during the thermal process of processing the upper layer transistors, avoiding affecting the lower layer transistors and the interconnect lines. The scheme has the advantages that the device structure, the channel crystal orientation and even the channel material adopted by the upper layer transistor and the lower layer transistor can be correspondingly optimized to obtain better and more matched device performance due to wafer bonding. This solution currently presents the following technical challenges: (1) preparation of a high-quality upper transistor active layer; (2) thinning and defect control of the upper bonded wafer; (3) The upper and lower layer transistors have alignment errors and have extremely high requirements on photoetching precision.

However, the original stacking scheme needs to consider the problem of recrystallisation of the dummy gate, which leads to complexity of the process flow.

In order to solve the above technical problems, an embodiment of the present application provides a method for manufacturing a semiconductor structure, so as to optimize a process flow.

In the embodiment of the application, the semiconductor structure can be applied to semiconductor devices such as memories, processors and the like.

In some embodiments, the semiconductor structure may include a first transistor and a second transistor disposed opposite and stacked. Wherein the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned in a direction perpendicular to the active region.

In some embodiments, the first gate structure and the second gate structure in the semiconductor structure may be integrally provided, i.e., a common gate (common gate) between the first transistor and the second transistor.

In other embodiments, a gate isolation layer may be disposed between the first gate structure and the second gate structure in the semiconductor structure, the gate isolation layer being used to isolate the first gate structure and the second gate structure.

In the embodiment of the application, the active region is a combination of a source region, a drain region and a channel region.

In the embodiment of the application, the first transistor and the second transistor in the semiconductor structure may be transistors of the same type, such as any one of the following: nanoflake field effect transistors (GAA Nanosheet), fin field effect transistors (FinFET), planar transistors, vertical transistors (VTFET), and fork plate transistors (forksheet), among others.

Fig. 2 is a semiconductor structure formed by a fin field effect transistor, and a method for manufacturing the semiconductor structure according to an embodiment of the present application is described below with reference to the semiconductor structure shown in fig. 2.

Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing a semiconductor structure according to an embodiment of the present application, and referring to fig. 1, the method for manufacturing a semiconductor structure may include:

s101, forming an active structure on a substrate. The active structures comprise a first active structure and a second active structure.

It will be appreciated that the first active structure of the first transistor and the second active structure of the second transistor in the semiconductor structure are formed by the same process (e.g. etching process) such that the active region of the first transistor and the active region of the second transistor are self-aligned.

In some possible embodiments, the substrate includes a top substrate, a first sacrificial layer, and a bottom substrate in a stacked arrangement, the top substrate being used to form the active structure.

It will be appreciated that the substrate in embodiments of the present application may be a multi-layer structure. Specifically, a sacrificial layer (namely, a first sacrificial layer) is epitaxially grown on the bottom substrate, a top substrate (see fig. 3A) is epitaxially grown above the first sacrificial layer, and the first sacrificial layer is used for protecting the main structure of the top substrate, reducing impact and vibration from the outside, improving the durability and reliability of the top substrate, and prolonging the service life.

In some embodiments, the sacrificial layer has a height of about 10-20 nm and the top substrate has a height of greater than 100nm. It should be noted that the heights of the first sacrificial layer and the top substrate may be selected according to actual use requirements, which is not particularly limited in the embodiment of the present application.

In some embodiments, when the first transistor and the second transistor in the semiconductor structure are of different types, the arrangement of the substrate is correspondingly different. For example, when the first transistor and the second transistor are any one of a fin field effect transistor, a planar transistor, and a vertical field effect transistor, the top substrate may be a silicon (Si) material. When the first transistor and the second transistor are nanoflake field effect transistors or fork plate transistors, the top substrate may be a stack of alternately deposited silicon material and silicon germanium (SiGe) material.

In some possible embodiments, the step S101 may include: the top substrate and the first sacrificial layer are etched to form an active structure and a second sacrificial layer. Wherein the second sacrificial layer connects the base substrate and the active structure.

It will be appreciated that the active structure is formed by etching the substrate, by the steps of: etching the top substrate and the first sacrificial layer, forming an active structure on the etched top substrate, and forming a second sacrificial layer on the etched first sacrificial layer. Wherein the active structure is divided into two parts, the upper part being used as a first active structure in the first transistor and the lower part being used as a second active structure in the second transistor.

It should be noted that, the etching process mentioned in the embodiment of the present application may include any of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal processes, to which embodiments of the present application are not limited.

And S102, depositing an insulating material on the active structure to form a shallow trench isolation structure (shallow trench isolation, STI). Wherein the shallow trench isolation structure wraps the active structure.

It will be appreciated that depositing an insulating material over the active structure, the first sacrificial layer and the base substrate may form a shallow trench isolation structure that encapsulates the active structure and the first sacrificial layer. The height of the shallow trench isolation structure is greater than that of the active structure.

In the embodiment of the present application, the insulating material for forming the shallow trench isolation structure may be: silicon nitride (SiN, si ₃N₄), silicon dioxide (SiO ₂), silicon oxycarbide (SiCO), or the like, but may be other insulating materials, and embodiments of the present application are not limited thereto.

In some embodiments, in order to facilitate the subsequent processing, after S102, a polishing process or a chemical-mechanical planarization (CMP) process may be further performed on the shallow trench isolation structure, so that when the shallow trench isolation structure is etched subsequently, the corresponding etching depths of the shallow trench isolation structures in different areas are the same, so that the heights of the tops of the exposed active structures are the same.

S103, forming a hard mask layer on the shallow trench isolation structure, and etching the shallow trench isolation structure by taking the hard mask layer as a mask to form a grid groove.

It will be appreciated that a layer of hard mask material (denoted as a first hard mask layer) is deposited over the shallow trench isolation structure, and then the first hard mask layer is covered on the surface of the shallow trench isolation structure, and then a photoresist is coated on the first hard mask layer, and after the photoresist is developed and a photolithography pattern is formed, the first hard mask layer is etched according to the photolithography pattern to form the hard mask layer. The hard mask layers are arranged on the surface of the shallow trench isolation structure at intervals, and gaps between the hard mask layers correspond to gate regions of the semiconductor structure. And finally, etching the shallow trench isolation structure by taking the hard mask layer as a mask, stopping etching until the etching reaches the bottom substrate, and forming a grid groove.

It should be noted that the gate recess is a recess formed in a gate region of the semiconductor structure, the semiconductor structure includes a first transistor and a second transistor, and correspondingly, the gate recess also includes a first gate recess and a second gate recess, the first gate recess corresponds to the first transistor, and the second gate recess corresponds to the second transistor.

And S104, depositing a semiconductor material in the grid groove to form an initial pseudo grid structure.

Wherein the initial dummy gate structure includes a first dummy gate structure corresponding to the first active structure and a second dummy gate structure corresponding to the second active structure, the first dummy gate structure and the second dummy gate structure being self-aligned.

It will be appreciated that depositing a semiconductor material (e.g., polysilicon) in the gate recess may form an initial dummy gate structure of the semiconductor structure, which also includes the first dummy gate structure and the second dummy gate structure, corresponding to the first transistor and the second transistor.

In some embodiments, before the step S104, the method may further include: and depositing a layer of oxide on the surface of the active structure positioned inside the gate groove, the surface of the second sacrificial layer and the upper surface of the bottom substrate to form an oxidation isolation layer (shown in fig. 3B).

In the embodiment of the application, the oxidation isolation layer can isolate and protect the active structure in the subsequent preparation process.

It should be noted that, for the process flow of forming the dummy gate structure and then forming the shallow trench isolation structure, the shallow trench isolation structure needs a high temperature in the forming process to ensure the quality of the shallow trench isolation structure; this makes the dummy gate structure subject to recrystallization during the formation of the shallow trench isolation structure. In the embodiment of the application, the problem of recrystallization of the initial pseudo gate structure can be avoided by the process flow of firstly forming the shallow slot isolation structure and then forming the initial pseudo gate structure.

S105, removing a part of the shallow trench isolation structure wrapping the first active structure to expose the first active structure.

It will be appreciated that a portion of the shallow trench isolation structure may be removed by etching until the first active structure is exposed, in order to facilitate the preparation of the first transistor in a subsequent process flow.

And S106, forming a first transistor based on the first active structure.

It is understood that other structures in the first transistor (e.g., the first source drain structure, the first spacer, the first interlayer dielectric layer, the first metal interconnect layer, etc.) may be formed based on the first active structure.

S107, rewinding and removing the substrate.

It will be appreciated that, after the first transistor is fabricated, the first transistor is reworked, and the second active structure may be placed upward, so as to facilitate the fabrication of the second transistor. The method comprises the following specific steps: after rewinding, the bottom substrate is placed upwards, the bottom substrate is removed, the shallow trench isolation structure wrapping the second active structure is exposed, and the surface of the second active structure far away from the first active structure is exposed.

In some possible embodiments, before the step S107, the method may further include: depositing an insulating material on the surface of the first transistor to form an insulating layer; and bonding the insulating layer with the carrier wafer.

It can be appreciated that the bonded carrier wafer can provide physical support for the flipped first transistor after rewinding, so as to effectively prevent the first transistor from being broken by external force during the process of preparing the second transistor.

In some possible embodiments, after the step S107, the method may further include: removing the bottom substrate and the second sacrificial layer to form a first groove; and filling semiconductor material in the first groove to form a pseudo gate structure. Wherein the dummy gate structure wraps the active structure in the gate recess.

It will be appreciated that the initial dummy gate structure does not cover the surface of the second active structure remote from the first active structure, and after rewinding and removing the bottom substrate, the second sacrificial layer between the second active structure and the bottom substrate may be removed, at which time the surface of the second active structure remote from the first active structure is exposed in the first recess; the first recess is then filled with the same semiconductor material (e.g., polysilicon) as the initial dummy gate structure, the filled polysilicon material together with the initial dummy gate structure forming a dummy gate structure that encapsulates the first active structure and the second active structure in the gate region.

And S108, removing a part of the shallow trench isolation structure, which wraps the second active structure, so as to expose the second active structure.

It will be appreciated that a portion of the shallow trench isolation structure may be removed by etching until the second active structure is exposed, in order to facilitate the preparation of the second transistor in a subsequent process flow.

In some embodiments, the shallow trench isolation structure with a predetermined thickness is reserved in the process of exposing the second active structure by etching the shallow trench isolation structure, and for convenience of distinction, the reserved shallow trench isolation structure with a predetermined thickness is denoted as a shallow trench isolation layer, and the shallow trench isolation layer is located between the first transistor and the second transistor and is used for isolating the first transistor and the second transistor.

S109, forming a second transistor based on the second active structure. Wherein the first transistor and the second transistor are self-aligned.

It is understood that other structures in the second transistor (e.g., the second source drain structure, the second spacer, the second interlayer dielectric layer, the second metal interconnect layer, etc.) may be formed based on the second active structure.

In the embodiment of the application, the active region of the first transistor and the active region of the second transistor are self-aligned, so that the first transistor and the second transistor are self-aligned.

In the embodiment of the application, the first dummy gate structure and the second dummy gate structure may be formed through the same process (i.e., the first dummy gate structure and the second dummy gate structure are integrated); the first dummy gate structure and the second dummy gate structure may be formed by different processes, and when the first dummy gate structure and the second dummy gate structure are formed by different processes, a gate isolation layer is disposed between the first dummy gate structure and the second dummy gate structure, and the gate isolation layer may be used to isolate the first dummy gate structure and the second dummy gate structure, or may be used to isolate the first gate structure formed based on the first dummy gate structure and the second gate structure formed based on the second dummy gate structure. When the first dummy gate structure and the second dummy gate structure are formed through the same process, the first gate structure and the second gate structure may be formed in the same process (i.e., a "common gate" design is adopted) during the formation of the first gate structure and the second gate structure; the first gate structure and the second gate structure may be formed by different processes, respectively, and a gate spacer may be disposed between the first gate structure and the second gate structure.

According to the above, the design of the dummy gate structure (i.e., the first dummy gate structure and the second dummy gate structure) and the gate structure (i.e., the first gate structure and the second gate structure) in the embodiment of the present application may include three cases: 1. a gate isolation layer is arranged between the first pseudo gate structure and the second pseudo gate structure, and a gate isolation layer is also arranged between the first gate structure and the second gate structure; 2. the first pseudo gate structure and the second pseudo gate structure are integrally arranged, and the first gate structure and the second gate structure are integrally arranged; 3. the first pseudo gate structure and the second pseudo gate structure are integrally arranged, and a gate isolation layer is arranged between the first gate structure and the second gate structure.

In some possible embodiments, where a gate isolation layer is disposed between the first dummy gate structure and the second dummy gate structure, and a gate isolation layer is also disposed between the first gate structure and the second gate structure, S104 may include: depositing a semiconductor material in the second gate recess to form a second dummy gate structure; depositing an oxide on the second dummy gate structure to form a first gate isolation layer; the first gate isolation layer is used for isolating the first pseudo gate structure and the second pseudo gate structure; a semiconductor material is deposited on the first gate isolation layer to form a first dummy gate structure.

It will be appreciated that, since the second gate recess is located below the first gate recess prior to rewinding, during formation of the initial dummy gate structure, semiconductor material should be deposited in the second gate recess to form the second dummy gate structure; depositing a layer of oxide with a preset thickness above the second pseudo gate structure to form a first gate isolation layer; and finally, depositing the semiconductor material which is the same as that of the second pseudo gate structure above the first gate isolation layer to form the first pseudo gate structure.

It should be noted that, the thickness of the first gate isolation layer may be designed according to practical requirements, which is not particularly limited in the embodiment of the present application.

In some possible embodiments, where a gate isolation layer is disposed between the first dummy gate structure and the second dummy gate structure, and a gate isolation layer is also disposed between the first gate structure and the second gate structure, S106 may include: forming a first source drain structure and a first interlayer dielectric layer based on the first active structure; removing the first pseudo gate structure, depositing an insulating material on the surface of the first active structure in the first gate groove, and depositing a metal material in the first gate groove to form a first gate dielectric layer and a first gate structure; and performing subsequent process treatment on the first gate structure and the first interlayer dielectric layer to form a first metal interconnection layer.

It will be appreciated that where a gate spacer is provided between the first dummy gate structure and the second dummy gate structure, and also between the first gate structure and the second gate structure, the first gate structure is formed during the process of fabricating the first transistor (i.e. before rewinding).

In some embodiments, forming the first source-drain structure and the first interlayer dielectric layer based on the first active structure may include: firstly, depositing insulating materials on two sides of a first pseudo gate structure to form a first spacer; next, a portion of the first active structure is removed by etching to provide a first source drain recess of the first transistor. Forming a strained material such as silicon germanium or silicon carbide in the first source-drain groove of the first transistor by using the first spacer as a mask through selective epitaxial growth so as to fill the first source-drain groove of the first transistor, and then forming a first source-drain structure on the strained material through a heavy doping process; finally, depositing an insulating material (such as silicon dioxide (SiO ₂)) above the first active structure and the first source drain structure to form a first interlayer dielectric layer; the first interlayer dielectric layer can cover the first active structure and the first source drain structure.

In some embodiments, removing the first dummy gate structure, depositing an insulating material on a surface of the first active structure in the first gate recess, and depositing a metal material in the first gate recess to form the first gate dielectric layer and the first gate structure may include: removing the first pseudo gate structure by etching to expose a first gate groove of the first transistor, removing an oxidation isolation layer covering the surface of the first active structure, and depositing an insulating material on the surface of the first active structure in the first gate groove to form a first gate dielectric layer; then, a metal material is deposited in the first gate recess to form a first gate structure of the first transistor. The first gate dielectric layer is used for isolating the first active structure and the first gate structure.

In some embodiments, performing a subsequent process on the first gate structure and the first interlayer dielectric layer to form a first metal interconnection layer may include: and performing dielectric deposition, metal line formation, lead-out pad formation and the like among the interconnection lines on the first interlayer dielectric layer and the first grid structure to form a first metal interconnection layer of the first transistor.

In some possible embodiments, where a gate isolation layer is disposed between the first dummy gate structure and the second dummy gate structure, and a gate isolation layer is also disposed between the first gate structure and the second gate structure, S109 may include: forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure; removing the second pseudo gate structure, depositing an insulating material on the surface of the second active structure in the second gate groove, and depositing a metal material in the second gate groove to form a second gate dielectric layer and a second gate structure; and performing subsequent process treatment on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

It will be appreciated that where a gate spacer is provided between the first dummy gate structure and the second dummy gate structure, and also between the first gate structure and the second gate structure, the second gate structure is formed during the process of fabricating the second transistor (i.e. after rewinding).

In some embodiments, forming the second source-drain structure and the second interlayer dielectric layer based on the second active structure may include: firstly, depositing insulating materials on two sides of a second pseudo gate structure to form a second gap wall; next, a portion of the second active structure is removed by etching to provide a second source drain recess of the second transistor. Forming a strain material such as silicon germanium or silicon carbide in the second source-drain groove of the second transistor by using the second spacer as a mask through selective epitaxial growth so as to fill the second source-drain groove of the second transistor, and then forming a second source-drain structure on the strain material through a heavy doping process; finally, depositing insulating materials (such as silicon dioxide) above the second active structure and the second source drain structure to form a second interlayer dielectric layer; the second interlayer dielectric layer can cover the second active structure and the second source drain structure.

In some embodiments, removing the second dummy gate structure, depositing an insulating material on a surface of the second active structure in the second gate recess, and depositing a metal material in the second gate recess to form the second gate dielectric layer and the second gate structure may include: removing the second pseudo gate structure by etching to expose a second gate groove of the second transistor, removing an oxidation isolation layer covered on the surface of the second active structure, and depositing an insulating material on the surface of the second active structure in the second gate groove to form a second gate dielectric layer; then, a metal material is deposited in the second gate recess to form a second gate structure of the second transistor. The second gate dielectric layer is used for isolating the second active structure and the second gate structure.

In some embodiments, performing a subsequent process on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer may include: and performing dielectric deposition, metal line formation, lead-out pad formation and the like among the interconnection lines on the second interlayer dielectric layer and the second gate structure to form a second metal interconnection layer of the second transistor.

In an embodiment of the present application, the metal material forming the first gate structure and/or the second gate structure may include, but is not limited to: the materials of the tantalum nitride (TaN), the titanium nitride (TiN), the aluminum nitride (AlN), the titanium aluminum carbide (TiAlC), the titanium aluminum nitride (TiAlN), the first gate structure and the second gate structure may be selected according to actual situations, and are not limited to the above listed metal materials.

In some possible embodiments, where the first dummy gate structure and the second dummy gate structure are integrally disposed, and the first gate structure and the second gate structure are integrally disposed, S104 may include: semiconductor material is deposited in the second gate recess and the first gate recess to form a second dummy gate structure and a first dummy gate structure. Wherein the second dummy gate structure and the first dummy gate structure are integrally provided.

It will be appreciated that the first dummy gate structure and the second dummy gate structure may be integrally formed by depositing semiconductor material directly into the gate recesses (the first gate recess and the second gate recess).

In some possible embodiments, where the first dummy gate structure and the second dummy gate structure are integrally disposed, and the first gate structure and the second gate structure are integrally disposed, S106 may include: forming a first source drain structure and a first interlayer dielectric layer based on the first active structure; and performing subsequent process treatment on the first pseudo gate structure and the first interlayer dielectric layer to form a first metal interconnection layer.

It can be appreciated that, in the second case, since the first gate structure and the second gate structure are integrally formed, the first gate structure and the second gate structure are formed during the process of manufacturing the second transistor, and other structures (such as the first spacer, the first source-drain structure, the first interlayer dielectric layer, and the first metal interconnection layer) in the first transistor except for the first gate structure are the same as the manufacturing process in the first case, which is not described in detail in the embodiment of the present application.

In some possible embodiments, where the first dummy gate structure and the second dummy gate structure are integrally disposed, and the first gate structure and the second gate structure are integrally disposed therebetween, S109 may include: forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure; removing the first dummy gate structure and the second dummy gate structure to expose the gate recess; depositing an insulating material on the surface of the active structure in the gate groove to form a gate dielectric layer; depositing a metal material in the first gate recess and the second gate recess to form a first gate structure of the first transistor and a second gate structure of the second transistor; the first grid structure and the first grid structure are integrally arranged; and performing subsequent process treatment on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

It can be understood that in the second case, in the process of preparing the second transistor, the first dummy gate structure and the second dummy gate structure are removed by the same etching process, the active structures (the first active structure and the second active structure) located in the gate groove are exposed, and after the oxide isolation layer on the surface of the active structure is removed, an insulating material is deposited on the surface of the active structure to form a gate dielectric layer (i.e., the first gate dielectric layer and the second gate dielectric layer), where the first gate dielectric layer and the second gate dielectric layer are also integrally disposed; finally, a metal material is deposited in the gate recesses (i.e., the first gate recess and the second gate recess) to form integrally disposed first gate structures and second gate structures. Except for the first gate structure in the first transistor and the second gate structure in the second transistor, other structures (such as the second spacer, the second source-drain structure, the second interlayer dielectric layer, and the second metal interconnection layer) in the second transistor are the same as the preparation process in the first case, which is not described in detail in the embodiment of the present application.

In some possible embodiments, where the first dummy gate structure and the second dummy gate structure are integrally provided, and a gate isolation layer is provided between the first gate structure and the second gate structure, S109 may include: forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure; removing the first and second dummy gate structures to expose the first and second gate recesses; depositing an insulating material on the surface of the active structure in the gate groove to form a gate dielectric layer; depositing a metal material in the first gate recess and the second gate recess, respectively, to form a first gate structure of the first transistor and a second gate structure of the second transistor; and performing subsequent process treatment on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

It will be appreciated that in the third case described above, the first gate structure and the second gate structure are formed in the process of manufacturing the second transistor, unlike the second case described above, the first gate structure and the second gate structure are formed through different processes, and a gate isolation layer is provided between the first gate structure and the second gate structure.

In the third case, the first gate dielectric layer and the second gate dielectric layer are integrally provided.

In some possible embodiments, depositing a metal material in the first gate recess and the second gate recess to form a first gate structure of the first transistor and a second gate structure of the second transistor, respectively, may include: depositing a metal material in the first gate recess to form a first gate structure; depositing an oxide on the first gate structure to form a second gate isolation layer; the second gate isolation layer is used for isolating the first gate structure and the second gate structure; a metal material is deposited on the second gate spacer to form a second gate structure.

It can be appreciated that in the third case, after rewinding, the first gate groove is located below the second gate groove, and a metal material may be deposited in the first gate groove first to form the first gate structure; depositing oxide on the first grid structure to form a second grid isolation layer; finally, a second gate structure is formed on the second gate isolation layer.

It should be noted that, the first gate isolation layer and the second gate isolation layer may be referred to as a gate isolation layer, and the first gate isolation layer and the second gate isolation layer are located between the first gate structure and the second gate structure and are used for isolating the first gate structure and the second gate structure. The first gate spacer is different from the second gate spacer in that the first gate spacer is formed during the preparation of the initial dummy gate structure and the second gate spacer is formed during the preparation of the first gate structure and the second gate structure.

It should be noted that, the first source-drain structure represents a source and/or a drain in the first transistor, and correspondingly, other expressions related to "source-drain" in the embodiments of the present application are all used to represent "source and/or drain", for example: the second source drain structure, the first source drain groove, the second source drain groove and the like.

The semiconductor structure provided by the embodiment of the application is described below by taking the first transistor and the second transistor as fin field effect transistors as examples. Fig. 2 is a schematic diagram of a first structure of a semiconductor structure according to an embodiment of the application. In fig. 2, (a) is a design layout of a semiconductor structure, and for convenience of understanding, only fin structures, gate structures, and source-drain structures are shown in the design layout; (b) A cut-away view of the semiconductor structure taken along a cut-away direction (i.e., A-A') of the gate structure; (c) A cut-away view of the semiconductor structure along a cut-away direction (i.e., the B-B' direction) of the source-drain structure; (d) A cut-away view of the semiconductor structure taken along the direction of the cut-away surface of the fin structure (i.e., the C-C' direction).

Referring to fig. 2, the semiconductor structure 10 includes a first transistor 11 and a second transistor 12, and the active structure in the semiconductor structure 10 is a plurality of fin structures. The fin structure is divided into two parts, one part serving as a first active structure 111 in the first transistor 11 and the other part serving as a second active structure 121 in the second transistor 12. The first gate structure 112 in the first transistor 11 and the second gate structure 122 in the second transistor 12 are self-aligned, and a first gate isolation layer 13 is provided between the first gate structure 112 and the second gate structure 122, the first gate isolation layer 13 being used to isolate the first gate structure 112 and the second gate structure 122.

The process of fabricating the semiconductor structure 10 shown in fig. 2 will be described below in conjunction with the above fabrication method. The semiconductor structure shown in fig. 2 may be prepared by the process shown in fig. 3A to 3G, and fig. 3A to 3G are schematic views of a first preparation process of the semiconductor structure according to an embodiment of the present application.

The first step: a substrate 21 is provided. Wherein the substrate 21 includes a top substrate 211, a first sacrificial layer 212, and a bottom substrate 213, which are sequentially stacked (see (a) in fig. 3A).

And a second step of: patterning of the fin structure is performed, and the top substrate 211 and the first sacrificial layer 212 are sequentially etched, and the etching is stopped to the bottom substrate 213, forming an active structure, i.e., the first active structure 111 and the second active structure 121, and the second sacrificial layer 214 (see (b) in fig. 3A).

And a third step of: an insulating material, such as SiO ₂, is deposited on the top substrate 211, the first sacrificial layer 212, and the bottom substrate 213 to form the shallow trench isolation structure 22 (see (c) in fig. 3A).

Fourth step: a hard mask layer 23 is formed on the shallow trench isolation structure 22 by a photolithography process (see (a) in fig. 3B).

Fifth step: the shallow trench isolation structure 22 is etched under the masking of the hard mask layer 23 to form a gate recess 24, wherein the gate recess 24 includes a first gate recess 241 and a second gate recess 242 (see (B) in fig. 3B).

Sixth step: the hard mask layer 23 is removed, and oxide is deposited on the surfaces of the first active structure 111, the second active structure 121, and the second sacrificial layer 214 located in the gate recess 24 to form an oxide isolation layer 25 (see (c) in fig. 3B).

Seventh step: depositing polysilicon in the second gate recess 242 to form a second dummy gate structure 262; depositing a layer of oxide on the second dummy gate structure 262 to form the first gate isolation layer 13; polysilicon is deposited in the first gate recess 241 to form a first dummy gate structure 261 (see fig. 3C).

Eighth step: the shallow trench isolation structure 22 wrapping the first active structure 111 is removed to expose the first active structure 111 (see (a) in fig. 3D).

Ninth step: based on the first active structure 111, a first spacer 113, a first source-drain structure 114, and a first interlayer dielectric layer 115 are formed (see (b) in fig. 3D).

Tenth step: removing the first dummy gate structure 261 and the oxide isolation layer 25 covering the surface of the first active structure 111; depositing a layer of insulating material on the surface of the first active structure 111 to form a first gate dielectric layer 116; next, a metal material is deposited in the first gate recess 241 to form the first gate structure 112 (see (c) in fig. 3D).

Eleventh step: a subsequent process treatment is performed on the first gate structure 112 and the first interlayer dielectric layer 115 to form a first metal interconnection layer 117 (see (a) in fig. 3E).

Twelfth step: an insulating material is deposited on the surface of the first metal interconnect layer 117 to form an insulating layer 15, and the carrier wafer 16 is bonded to the insulating layer 15, and then the first transistor 11 is rewound so that the bottom substrate 213 is placed upward (see (b) in fig. 3E).

Thirteenth step: the bottom substrate 213 is removed by a CMP process to achieve wafer thinning (see (c) in fig. 3E).

Fourteenth step: the second sacrificial layer 214 is removed to form the first recess 31 (see (a) in fig. 3F).

Fifteenth step: the first grooves 31 are filled with polysilicon (see (b) in fig. 3F).

Sixteenth step: the shallow trench isolation structure 22 wrapping the second active structure 121 is removed to expose the second active structure 121 and form a shallow trench isolation layer 221 (see (c) in fig. 3F).

Seventeenth step: based on the second active structure 121, a second spacer 123, a second source drain structure 124, and a second interlayer dielectric layer 125 are formed (see (a) in fig. 3G).

Eighteenth step: removing the second dummy gate structure 262 and the oxide isolation layer 25 covering the surface of the second active structure 121; depositing a layer of insulating material on the surface of the second active structure 121 to form a second gate dielectric layer 126; next, a metal material is deposited in the second gate groove 242 to form the second gate structure 122 (see (b) in fig. 3G).

Note that the oxide spacer 25 located inside the first gate spacer 13 is not removed, but remains between the first gate dielectric layer 116 and the second gate dielectric layer 126.

Nineteenth step: a subsequent process treatment is performed on the second gate structure 122 and the second interlayer dielectric layer 125 to form a second metal interconnection layer 127 (see (c) in fig. 3G).

Thus, the semiconductor structure 10 in which the first transistor 11 and the second transistor 12 are fin field effect transistors is completed in the case where the gate isolation layer is provided between the first dummy gate structure and the second dummy gate structure, and the gate isolation layer is also provided between the first gate structure and the second gate structure.

Fig. 4 is a schematic diagram of a second structure of a semiconductor structure according to an embodiment of the present application. In fig. 4, (a) is a design layout of a semiconductor structure, and for convenience of understanding, only fin structures, gate structures, and source-drain structures are shown in the design layout; (b) A cut-away view of the semiconductor structure taken along a cut-away direction (i.e., A-A') of the gate structure; (c) A cut-away view of the semiconductor structure along a cut-away direction (i.e., the B-B' direction) of the source-drain structure; (d) A cut-away view of the semiconductor structure taken along the direction of the cut-away surface of the fin structure (i.e., the C-C' direction).

Referring to fig. 4, the semiconductor structure 10 includes a first transistor 11 and a second transistor 12, and the active structure in the semiconductor structure 10 is a plurality of fin structures. The fin structure is divided into two parts, one part serving as a first active structure 111 in the first transistor 11 and the other part serving as a second active structure 121 in the second transistor 12. The first gate structure 112 in the first transistor 11 and the second gate structure 122 in the second transistor 12 are integrally provided and self-aligned.

The process of fabricating the semiconductor structure 10 shown in fig. 4 will be described below in conjunction with the above fabrication method. The semiconductor structure shown in fig. 4 may be prepared by the process shown in fig. 5A and 5B, and fig. 5A and 5B are schematic diagrams illustrating a second preparation process of the semiconductor structure according to an embodiment of the present application.

The first step: providing a substrate 21; forming first and second active structures 111 and 121 and a second sacrificial layer 214; forming a shallow trench isolation structure 22; the gate groove 24 is formed, wherein the gate groove 24 includes a first gate groove 241 and a second gate groove 242 (see (a) in fig. 5A) (for a specific process, reference may be made to the first to fifth steps of the first manufacturing process of the semiconductor structure described above).

And a second step of: polysilicon is deposited in the first and second gate grooves 241 and 242 to form first and second dummy gate structures 261 and 262 integrally provided (see (b) in fig. 5A).

And a third step of: the first active structure 111 is exposed, and based on the first active structure 111, a first spacer 113, a first source drain structure 114, a first interlayer dielectric layer 115, and a first metal interconnection layer (see (c) in fig. 5A) are formed (except that the first gate structure 112 and the first gate dielectric layer 116 are not formed, the processes for preparing other structures in the first transistor 11 may refer to the eighth step to the eleventh step of the first preparation process of the semiconductor structure described above).

Fourth step: after the rewinding, the second spacer 123, the second source-drain structure 124 and the second interlayer dielectric layer 125 of the second transistor 12 are formed (see (a) in fig. 5B) (for a specific process, reference may be made to the twelfth step to seventeenth step of the first preparation process of the above-mentioned semiconductor structure).

Fifth step: the first dummy gate structure 261, the second dummy gate structure 262, and the oxide isolation layer 25 are removed, an insulating material is deposited on the surfaces of the first active structure 111 and the second active structure 121 to form the first gate dielectric layer 116 and the second gate dielectric layer 126 integrally provided, and a metal material is deposited in the first gate recess 241 and the second gate recess 242 to form the first gate structure 112 and the second gate structure 122 integrally provided (see (B) in fig. 5B).

Sixth step: a subsequent process treatment is performed on the second gate structure 122 and the second interlayer dielectric layer 125 to form a second metal interconnection layer 127 (see (c) in fig. 5B).

Thus, the semiconductor structure 10 in which the first transistor 11 and the second transistor 12 are fin field effect transistors is completed in the case where the first dummy gate structure and the second dummy gate structure are integrally provided and the first gate structure and the second gate structure are integrally provided.

Fig. 6 is a schematic diagram of a third structure of a semiconductor structure according to an embodiment of the present application. In fig. 6, (a) is a design layout of a semiconductor structure, and for convenience of understanding, only fin structures, gate structures, and source-drain structures are shown in the design layout; (b) A cut-away view of the semiconductor structure taken along a cut-away direction (i.e., A-A') of the gate structure; (c) A cut-away view of the semiconductor structure along a cut-away direction (i.e., the B-B' direction) of the source-drain structure; (d) A cut-away view of the semiconductor structure taken along the direction of the cut-away surface of the fin structure (i.e., the C-C' direction).

Referring to fig. 6, the semiconductor structure 10 includes a first transistor 11 and a second transistor 12, and the active structure in the semiconductor structure 10 is a plurality of fin structures. The fin structure is divided into two parts, one part serving as a first active structure 111 in the first transistor 11 and the other part serving as a second active structure 121 in the second transistor 12. The first gate structure 112 in the first transistor 11 and the second gate structure 122 in the second transistor 12 are self-aligned, and a second gate isolation layer 14 is provided between the first gate structure 112 and the second gate structure 122, the second gate isolation layer 14 being used to isolate the first gate structure 112 and the second gate structure 122.

The process of fabricating the semiconductor structure 10 shown in fig. 6 will be described below in conjunction with the above fabrication method. The semiconductor structure shown in fig. 6 may be prepared by the process shown in fig. 7, and fig. 7 is a schematic diagram illustrating a third preparation process of the semiconductor structure according to an embodiment of the present application.

The first step: forming a first transistor 11 in which a first dummy gate structure 261 and a second dummy gate structure 262 are integrally provided; the first transistor 11 is reworked and the bottom substrate 213 is removed, filling the first recess 31; the second spacer 123, the second source-drain structure 124, and the second interlayer dielectric layer 125 in the second transistor 12 are formed (see (a) in fig. 7) (except that the first gate structure 112 and the first gate dielectric layer 116 are not formed, the specific process may refer to the first step to seventeenth step of the first preparation process of the above-mentioned semiconductor structure).

And a second step of: removing the first dummy gate structure 261, the second dummy gate structure 262, and the oxide isolation layer 25; depositing an insulating material on the surfaces of the first active structure 111 and the second active structure 121 to form a first gate dielectric layer 116 and a second gate dielectric layer 126, wherein the first gate dielectric layer 116 and the second gate dielectric layer 126 are integrally arranged; a metal material is deposited in the first gate recess 241 to form the first gate structure 112, an oxide is deposited on the first gate structure 112 to form the second gate isolation layer 14, and a metal material is deposited in the second gate recess 242 to form the second gate structure 122 (see (b) in fig. 7).

And a third step of: a subsequent process treatment is performed on the second gate structure 122 and the second interlayer dielectric layer 125 to form a second metal interconnection layer 127 (see (c) in fig. 7).

Thus, the semiconductor structure 10 in which the first transistor 11 and the second transistor 12 are fin field effect transistors is completed in the case where the first dummy gate structure and the second dummy gate structure are integrally provided and the gate isolation layer is provided between the first gate structure and the second gate structure.

In the embodiment of the application, the shallow slot isolation structure is formed first, and then the process sequence of the first pseudo gate structure and the second pseudo gate structure is formed, so that the first pseudo gate structure and the second pseudo gate structure can be prevented from being recrystallized, and the process flow is optimized.

Further, the semiconductor structure provided by the embodiment of the application can be detected by using a detection and analysis instrument, for example: scanning electron microscope (scanning electron microscope, SEM), transmission electron microscope (transmission electron microscope, TEM), scanning transmission electron microscope (scanning transmission electron microscopy, STEM), and the like. Taking TEM as an example, the semiconductor structure provided in the embodiment of the present application may adopt a TEM slicing manner to detect the semiconductor structure, such as a first gate structure and a second gate structure that are integrally provided, or a first gate structure and a second gate structure that are provided with a gate isolation layer in the middle.

In the embodiment of the application, the preparation method of the semiconductor structure not only optimizes the technological process of the semiconductor structure, but also considers the problems of consistency, defect density, alignment and the like of the active regions of the upper transistor and the lower transistor (namely the first transistor and the second transistor). In addition, the preparation method of the semiconductor structure further solves the problems of complex process, fixed polarity (single-chip scheme), difficult alignment, high defect density of upper semiconductor materials (sequential scheme) and the like of the existing mainstream technical scheme of the stacked transistor, thereby promoting the industrialization of the stacked transistor technology.

Secondly, the preparation method of the semiconductor structure provided by the embodiment of the application is also an organic fusion of the current sequence and the single-chip stacked transistor scheme, has high multiplexing degree of the mature technology, can avoid a great deal of high-cost process development to save cost, and has high feasibility. Meanwhile, in the embodiment of the application, the semiconductor structure adopts a self-aligned back-to-back active area and metal grid design, the front and back transistors (namely the first transistor and the second transistor) have independent signals and power supply networks and are connected through local interconnection, metal wiring resources are greatly released (can be improved by more than 60 percent) under the condition of not changing the design of a very miniature 4T track unit, and the space is huge in the cooperative optimization direction of the process design. Finally, the flip-chip transistor scheme is compatible with the existing mainstream device architecture, and can realize front-back stacking of nano-chip field effect transistors, fin field effect transistors, planar transistors, vertical transistors and fork plate transistors without special process development for specific device architecture, so that the flip-chip transistor scheme is high in flexibility and high in extensibility from the iteration point of semiconductor process nodes. The inverted stacked transistor is quite advanced in concept, has important industrial value, and is high in practicability and wide in expansion prospect.

An embodiment of the present application provides a semiconductor device including: such as the semiconductor structures of the above embodiments. The specific limitation of the semiconductor structure may be referred to the semiconductor structures shown in fig. 2, 4 and 6, and will not be described herein.

An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device comprises the semiconductor structure. The specific limitation of the semiconductor structure may be referred to the semiconductor structures shown in fig. 2, 4 and 6, and will not be described herein.

In the description of the present application, a description of the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method of fabricating a semiconductor structure, the method comprising:

forming an active structure on a substrate; the active structure comprises a first active structure and a second active structure;

depositing an insulating material on the active structure to form a shallow trench isolation structure; the shallow slot isolation structure wraps the active structure;

Forming a hard mask layer on the shallow trench isolation structure, and etching the shallow trench isolation structure by taking the hard mask layer as a mask to form a grid groove;

Depositing a semiconductor material in the gate recess to form an initial dummy gate structure; the initial dummy gate structure includes a first dummy gate structure corresponding to the first active structure and a second dummy gate structure corresponding to the second active structure, the first dummy gate structure and the second dummy gate structure being self-aligned;

removing a portion of the shallow trench isolation structure surrounding the first active structure to expose the first active structure;

Forming a first transistor based on the first active structure;

Rewinding and removing the substrate;

Removing a portion of the shallow trench isolation structure surrounding the second active structure to expose the second active structure;

Forming a second transistor based on the second active structure; the first transistor and the second transistor are self-aligned.

2. The method of claim 1, wherein a first gate spacer is disposed between the first dummy gate structure and the second dummy gate structure; the gate recess includes a first gate recess corresponding to the first active structure and a second gate recess corresponding to the second active structure;

The depositing semiconductor material in the gate recess to form an initial dummy gate structure, comprising:

Depositing a semiconductor material in the second gate recess to form the second dummy gate structure;

Depositing an oxide on the second dummy gate structure to form the first gate isolation layer; the first gate isolation layer is used for isolating the first pseudo gate structure and the second pseudo gate structure;

Depositing a semiconductor material on the first gate isolation layer to form the first dummy gate structure.

3. The method of claim 2, wherein forming a first transistor based on the first active structure comprises:

Forming a first source drain structure and a first interlayer dielectric layer based on the first active structure;

Removing the first pseudo gate structure, depositing an insulating material on the surface of a first active structure positioned in the first gate groove, and depositing a metal material in the first gate groove to form a first gate dielectric layer and a first gate structure;

And performing subsequent process treatment on the first grid structure and the first interlayer dielectric layer to form a first metal interconnection layer.

4. The method of claim 2, wherein forming a second transistor based on the second active structure comprises:

forming a second source drain structure and a second interlayer dielectric layer based on the second active structure;

removing the second pseudo gate structure, depositing an insulating material on the surface of a second active structure positioned in the second gate groove, and depositing a metal material in the second gate groove to form a second gate dielectric layer and a second gate structure;

And performing subsequent process treatment on the second gate structure and the second interlayer dielectric layer to form a second metal interconnection layer.

5. The method of claim 1, wherein the first dummy gate structure and the second dummy gate structure are formed by a single process, the gate recess including a first gate recess corresponding to the first active structure and a second gate recess corresponding to the second active structure;

Depositing a semiconductor material in the second gate recess and the first gate recess to form the second dummy gate structure and the first dummy gate structure; the second dummy gate structure and the first dummy gate structure are integrally arranged.

6. The method of claim 5, wherein forming a first transistor based on the first active structure comprises:

and carrying out subsequent process treatment on the first pseudo gate structure and the first interlayer dielectric layer to form a first metal interconnection layer.

7. The method of claim 5, wherein forming a second transistor based on the second active structure comprises:

removing the first and second dummy gate structures to expose the gate recess;

Depositing an insulating material on the surface of the active structure in the gate groove to form a gate dielectric layer;

Depositing a metal material in the first gate recess and the second gate recess to form a first gate structure of a first transistor and a second gate structure of a second transistor; the first grid structure and the first grid structure are integrally arranged;

8. The method of claim 5, wherein forming a second transistor based on the second active structure comprises:

removing the first and second dummy gate structures to expose the first and second gate recesses;

depositing a metal material in the first gate recess and the second gate recess, respectively, to form a first gate structure of a first transistor and a second gate structure of a second transistor;

9. The method of claim 8, wherein depositing a metal material in the first gate recess and the second gate recess, respectively, to form a first gate structure of a first transistor and a second gate structure of a second transistor, comprises:

Depositing a metal material in the first gate recess to form the first gate structure;

Depositing oxide on the first grid structure to form a second grid isolation layer; the second gate isolation layer is used for isolating the first gate structure and the second gate structure;

and depositing a metal material on the second gate isolation layer to form the second gate structure.

10. The method of claim 1, wherein the substrate comprises a top substrate, a first sacrificial layer, and a bottom substrate in a stacked arrangement, the top substrate being used to form the active structure;

The forming an active structure on a substrate includes: etching the top substrate and the first sacrificial layer to form the active structure and a second sacrificial layer; the second sacrificial layer connects the bottom substrate and the active structure;

after the rewinding and removing the substrate, the method further comprises: removing the bottom substrate and the second sacrificial layer to form a first groove; filling the first groove with the semiconductor material to form a pseudo gate structure; the dummy gate structure wraps the active structure in the gate recess.

11. A semiconductor structure, the semiconductor structure comprising:

a first transistor;

A second transistor;

Wherein the first transistor and the second transistor are stacked and self-aligned; the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

12. The semiconductor structure of claim 11, wherein,

The first grid structure and the second grid structure are integrally arranged; or alternatively, the first and second heat exchangers may be,

A gate isolation layer is arranged between the first gate structure and the second gate structure, and is used for isolating the first gate structure and the second gate structure.

13. A semiconductor device, comprising: the semiconductor structure of claim 11.

14. An electronic device, comprising: a circuit board and the semiconductor device according to claim 13, the semiconductor device being provided to the circuit board.