CN117894754A

CN117894754A - Interconnection method of stacked transistor, stacked transistor and semiconductor device

Info

Publication number: CN117894754A
Application number: CN202410177747.8A
Authority: CN
Inventors: 吴恒; 郭睿; 卢浩然; 王润声; 黎明
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2024-02-08
Filing date: 2024-02-08
Publication date: 2024-04-16

Abstract

The application provides an interconnection method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the following steps: forming a fin structure on a semiconductor substrate, the fin structure including a first portion and a second portion; forming a first semiconductor structure based on the first portion; forming a first single diffusion barrier structure in the single diffusion isolation region of the first semiconductor structure; rewinding the first semiconductor structure and removing the semiconductor substrate to expose a second portion of the fin structure; forming a second semiconductor structure based on the second portion; forming a second single diffusion barrier structure within the single diffusion isolation region of the second semiconductor structure; wherein, the first single diffusion partition structure and the second single diffusion partition structure are provided with interconnection through hole structures; the interconnect via structure is connected to a first metal interconnect layer on the first semiconductor structure and a second metal interconnect layer on the second semiconductor structure.

Description

Interconnection method of stacked transistor, stacked transistor and semiconductor device

Technical Field

The present disclosure relates to the field of semiconductors, and more particularly, to a stacked transistor interconnection method, a stacked transistor, and a semiconductor device.

Background

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors further increase transistor integration density by integrating two or more layers of transistors in vertical space is one of the important technologies continuing the scaling of integrated circuits.

In some schemes for preparing stacked transistors (stacked transistor), when forming the direct connection structure of the upper and lower transistors, the positions of the channel structure and the source-drain structure in the upper and lower transistors are often needed to be avoided, so that more space is required in the process of forming the direct connection structure, the area of standard stacked transistor units is increased, and the integration of the stacked transistors is not facilitated.

Disclosure of Invention

The application provides an interconnection method of a stacked transistor, the stacked transistor and a semiconductor device, so that the area of a standard stacked transistor unit is not increased while a direct connection structure between an upper layer transistor and a lower layer transistor of the stacked transistor is formed, and the integration level of the stacked transistor is effectively improved.

In a first aspect, embodiments of the present application provide a method for interconnecting stacked transistors, the method including: forming a fin structure on a semiconductor substrate; the fin structure includes a first portion and a second portion, the first portion being remote from the semiconductor substrate relative to the second portion; forming a first semiconductor structure based on the first portion; the first semiconductor structures are sequentially and alternately arranged with the first grid structures and the first source-drain structures in the extending direction of the fin-shaped structures; removing the first gate structure and the first part of the fin structure in the single diffusion isolation region of the first semiconductor structure, and depositing a first insulating material in the single diffusion isolation region to form a first single diffusion isolation structure; the first single diffusion barrier structure is used for isolating at least the first transistor and the second transistor in the first semiconductor structure; rewinding the first semiconductor structure and removing the semiconductor substrate to expose a second portion of the fin structure; forming a second semiconductor structure based on the second portion; the second semiconductor structures are sequentially and alternately arranged with second grid structures and second source-drain structures in the extending direction of the fin-shaped structures; removing the second gate structure and the second part of the fin structure in the single diffusion isolation region of the second semiconductor structure, and depositing a second insulating material in the single diffusion isolation region to form a second single diffusion isolation structure; the second single diffusion barrier structure is used for isolating at least the third transistor and the fourth transistor in the second semiconductor structure; the single diffusion isolation region of the second semiconductor structure is overlapped with the single diffusion isolation region of the first semiconductor structure; wherein, the first single diffusion partition structure and the second single diffusion partition structure are provided with interconnection through hole structures; the interconnect via structure is for connecting with a first metal interconnect layer located on the first semiconductor structure and a second metal interconnect layer located on the second semiconductor structure.

In some possible embodiments, the second semiconductor structure further comprises a second source drain metal formed over the second source drain structure; forming a second semiconductor structure based on the second portion, comprising: removing a first part of the second source drain metal in the second semiconductor structure by adopting a back etching process so as to form a first groove; the projection area of the first groove projected towards the second source drain structure is smaller than the projection area of the second source drain metal projected towards the second source drain structure; the depth of the first groove is smaller than that of the second source drain metal; depositing a third insulating material in the first groove to form a first barrier layer; the selectivity of etching the third insulating material is different from the selectivity of etching the first insulating material and the second insulating material.

In some possible embodiments, after forming the second single diffusion barrier structure, the method further comprises: sequentially etching the second single diffusion partition structure and the first single diffusion partition structure to form a first through hole; depositing a layer of insulating material on the inner wall of the first through hole to form a first isolation layer; depositing a metal material inside the first via to form an interconnect via structure; the first isolation layer is used for isolating the interconnection through hole structure and the fin-shaped structure.

In some possible embodiments, etching the second single diffusion barrier structure and the first single diffusion barrier structure sequentially to form the first via includes: the second single diffusion barrier structure and the first single diffusion barrier structure are selectively etched to form a first via hole in self-alignment.

In some possible embodiments, the first semiconductor structure further comprises a first source drain metal formed over the first source drain structure; forming a first semiconductor structure based on the first portion, comprising: removing a first part of the first source drain metal in the first semiconductor structure by adopting a back etching process to form a second groove; the projection area of the second groove projected towards the first source drain structure is smaller than the projection area of the first source drain metal projected towards the first source drain structure; the depth of the second groove is smaller than that of the first source drain metal; depositing a fourth insulating material in the second groove to form a second barrier layer; the selectivity of etching the fourth insulating material is different from the selectivity of etching the first insulating material.

In some possible embodiments, the interconnect via structure comprises: a first interconnect via structure and a second interconnect via structure; after forming the first single diffusion barrier structure, the method further comprises: etching the first single diffusion partition structure to form a second through hole; depositing a layer of insulating material on the inner wall of the second through hole to form a second isolation layer; depositing a metal material inside the second via to form a first interconnect via structure; the second isolation layer is used for isolating the first interconnection through hole structure and the first part of the fin-shaped structure; after forming the second single diffusion barrier structure, the method further comprises: etching the second single diffusion partition structure until the first interconnection through hole structure is exposed, so as to form a third through hole; depositing a layer of insulating material on the inner wall of the third through hole to form a third isolation layer; depositing a metal material inside the third via to form a second interconnect via structure; the third isolation layer is used to isolate the second interconnect via structure from the second portion of the fin structure.

In some possible embodiments, etching the first single diffusion barrier structure to form the second via includes: selectively etching the first single diffusion barrier structure until a second portion of the fin structure is exposed to form a second via hole in self-alignment; etching the second single diffusion barrier structure until the first interconnect via structure is exposed to form a third via, comprising: the second single diffusion barrier structure is selectively etched until the first interconnect via structure is exposed to form a third via self-aligned.

In some possible embodiments, removing the first portion of the second source drain metal in the second semiconductor structure using an etch back process to form a first recess comprises: and removing a first part of the second source drain metal adjacent to the single diffusion isolation region in the second semiconductor structure by adopting a back etching process so as to form a first groove. Removing the first portion of the first source drain metal in the first semiconductor structure by using a back etching process to form a second groove, including: and removing a first part of the first source drain metal adjacent to the single diffusion isolation region in the first semiconductor structure by adopting a back etching process so as to form a second groove.

In a second aspect, embodiments of the present application provide a stacked transistor, the stacked transistor comprising: a plurality of lower layer transistors; a plurality of upper layer transistors, each of the plurality of upper layer transistors and each of the plurality of lower layer transistors being disposed opposite each other; the first active structure of the lower transistor and the second active structure of the upper transistor in the two transistors arranged in opposite directions form an active structure, and the first source drain structure of the lower transistor and the second source drain structure of the upper transistor in the two transistors arranged in opposite directions are self-aligned; a first interconnection through hole structure is formed in a single diffusion isolation region among the plurality of lower-layer transistors; a second interconnection through hole structure is formed in the single diffusion isolation region between the plurality of upper layer transistors; the first interconnect via structure communicates with the second interconnect via structure, and the first interconnect via structure communicates with the first metal interconnect layer of the underlying transistor, and the second interconnect via structure communicates with the second metal interconnect layer of the overlying transistor.

In a third aspect, embodiments of the present application provide a semiconductor device, including: stacked transistors as in the above embodiments.

In the embodiment of the application, in the preparation process of the upper transistor layer and the lower transistor layer, the single diffusion isolation structure for isolating the two transistors can be formed by removing the grid structure and the fin structure which are positioned in the single diffusion isolation region. An interconnection through hole structure is formed in the single diffusion partition structure, and can be connected with a first metal interconnection layer positioned in a lower-layer transistor and a second metal interconnection layer positioned in an upper-layer transistor, so that the metal interconnection layer between the upper-layer transistor and the lower-layer transistor can be directly connected. Therefore, in the embodiment of the application, the interconnection through hole structure capable of directly connecting the upper layer transistor and the lower layer transistor is located in the single diffusion partition structure inside the stacked transistor unit, so that more space is not required to be occupied, the area of the standard stacked transistor unit is not increased, and the integration level of the stacked transistor is effectively improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a flow chart of an implementation of a method of interconnecting stacked transistors in an embodiment of the present application;

FIG. 2 is a schematic top view of a stacked transistor in an embodiment of the present application;

fig. 3 to 22 are schematic views of a first manufacturing process of a stacked transistor in an embodiment of the present application;

fig. 23 to 30 are schematic views of a second manufacturing process of a stacked transistor in the embodiment of the present application;

fig. 31 is a schematic view of a first structure of a stacked transistor in an embodiment of the present application;

fig. 32 is a schematic diagram of a second structure of a stacked transistor in an embodiment of the present application.

The figures above: 10. stacking transistors; 111. a first dummy gate sidewall; 112. a first source drain structure; 113. a first interlayer dielectric layer; 114. a first gate dielectric layer; 115. a first gate electrode layer; 116. a first source drain metal; 117. a first single diffusion barrier structure; 118. a first metal interconnect layer; 121. a second dummy gate sidewall; 122. a second source drain structure; 123. a second interlayer dielectric layer; 124. a second gate dielectric layer; 125. a second gate electrode layer; 126. a second source drain metal; 127. a second single diffusion barrier structure; 128. a second metal interconnect layer; 21. a substrate; 22. shallow trench isolation structures; 23. a first dummy gate structure; 24. a first source drain groove; 25. a second groove; 26. a second barrier layer; 27. a first photoresist; 28. a second through hole; 29. a second isolation layer; 30. a first interconnect via structure; 31. an insulating layer; 32. a carrier wafer; 33. a third barrier layer; 34. a second interconnect via structure; 35. a first barrier layer; 36. a first through hole; 37. a first isolation layer; 38. an interconnect via structure; 39. and a third isolation layer.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application.

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits.

In one embodiment, the fabrication process of the stacked transistor (stacked transistors) has two schemes, a single-chip scheme and a sequential scheme.

In the first approach, N-channel field effect transistors (N field effect transistors, NFET) and P-channel field effect transistors (P field effect transistors, PFET) are fabricated on the same substrate, and wafer bonding techniques are not employed. This determines that the same layer transistors must be of the same type, i.e., NFET or PFET. And the transistors on the upper layer and the lower layer are strictly in the same plane space, and no alignment deviation exists. The advantage of this solution is a better integration density. Drawbacks of this approach include the following two points: (1) The process is complex, and a large number of process technologies need to be developed and optimized; (2) Each layer of transistors has a fixed polarity, and two layers of transistors must be relied upon to form a basic Complementary Metal Oxide Semiconductor (CMOS) circuit, which has poor design flexibility.

The second scheme is based on wafer bonding and layer-by-layer processing. Specifically, the two transistors are stacked vertically by bonding a wafer on top of the fabricated lower transistor to prepare the upper transistor. However, this approach requires tight temperature control during the thermal process of processing the upper layer transistors, avoiding affecting the lower layer transistors and the interconnect lines. The scheme has the advantages that the device structure, the channel crystal orientation and even the channel material adopted by the upper layer transistor and the lower layer transistor can be correspondingly optimized to obtain better and more matched device performance due to wafer bonding.

However, in some schemes for preparing the stacked transistor (stacked transistor), when forming the direct connection structure of the upper and lower transistors, the positions of the channel structure and the source-drain structure in the upper and lower transistors are often needed to be avoided, so that more space is required in the process of forming the direct connection structure, the area of the standard stacked transistor unit is increased, and the integration of the stacked transistor is not facilitated.

In order to solve the above technical problems, embodiments of the present application provide an interconnection method of stacked transistors, so as to not increase the area of standard stacked transistor units while forming a direct connection structure between the upper and lower layers of transistors of the stacked transistors, and effectively improve the integration level of the stacked transistors.

In an embodiment, the stacked transistor may include at least four transistors, for example, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor and the second transistor may be both lower-layer transistors and are both connected to the first metal interconnection layer (i.e., the metal interconnection layer of the lower-layer transistor). The third transistor and the fourth transistor may be the same as the upper transistor, and are both connected to the second metal interconnection layer (i.e., the metal interconnection layer of the upper transistor). The first transistor and the third transistor may be disposed opposite each other, and the second transistor and the fourth transistor may be disposed opposite each other, such that the first metal interconnection layer and the second metal interconnection layer are located at opposite ends of the stacked transistor.

Further, the active structure in the first transistor (i.e., the first active structure) and the active structure in the third transistor (i.e., the second active structure) are formed by the same process, and at this time, it can be understood that the first transistor is self-aligned with the third transistor. Similarly, the active structure in the second transistor (i.e., the first active structure) and the active structure in the fourth transistor (i.e., the second active structure) are formed by the same process, and at this time, it can be understood that the second transistor and the fourth transistor are self-aligned.

In an embodiment of the present application, the first transistor, the second transistor, the third transistor, and the fourth transistor in the stacked transistor may be fin field effect transistors with active structures in fin structures.

Fig. 1 is a schematic flow chart of an implementation of an interconnection method of stacked transistors in an embodiment of the present application, and referring to fig. 1, the interconnection method of stacked transistors may include:

s101, forming a fin structure on a semiconductor substrate.

It is to be understood that a semiconductor substrate may be provided first, and the semiconductor substrate may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, or the like. Second, fin structures may be formed on the semiconductor substrate that stand upright on the semiconductor substrate.

In an embodiment, forming a fin structure on a semiconductor substrate in S101 includes: providing a semiconductor substrate, and forming a semiconductor epitaxial layer on the surface of the semiconductor substrate through an epitaxial growth process; etching the semiconductor epitaxial layer to a certain depth in the semiconductor epitaxial layer or to the surface of the semiconductor substrate or to a certain depth in the substrate, thereby forming a plurality of fin structures.

Here, each fin structure includes a first portion and a second portion, the first portion being remote from the semiconductor substrate relative to the second portion.

It can be appreciated that in the embodiment of the present application, since the upper and lower transistors in the stacked transistor share the fin structure, that is, the first active structure of the lower transistor and the second active structure of the upper transistor are formed by the same etching process. Thus, a greater etch depth may be used when forming fin structures on a semiconductor substrate. For example, the depth of the etched fin structure may be made greater than 100nm.

In an embodiment, forming a fin structure on a semiconductor substrate in S101 further includes: after forming the fin structure, a shallow trench isolation structure is formed that wraps around a second portion of the fin structure.

It will be appreciated that an insulating material may be deposited over the semiconductor substrate and the surfaces of the fin structures and a chemical mechanical planarization process may be used to remove the top surface of the insulating material until the top surface of the fin structures is exposed, thereby forming shallow trench isolation structures (shallow trench isolation, STI) having a top surface flush with the top surface of the fin structures, and further etching back the shallow trench isolation structures to a depth such that the shallow trench isolation structures encapsulate the second portion of the fin structures, exposing the first portion of the fin structures.

The insulating material for forming the shallow trench isolation structure can be any one of the following materials: silicon nitride (SiN, si) ₃ N ₄ ) Silicon dioxide (SiO) ₂ ) Or silicon oxycarbide (SiCO), and the like.

S102, forming a first semiconductor structure based on the first part.

Here, the first semiconductor structure is sequentially arranged with a first gate structure and a first source-drain structure in an extension direction of the fin structure.

It will be appreciated that, based on the first portion of the fin structure, the first source-drain structure and the first gate structure may be formed alternately in sequence in the extending direction of the fin structure using standard processes for semiconductor fabrication.

The first source-drain structure and the first gate structure may be a source-drain structure and a gate structure in the underlying transistor, respectively. The first source-drain structure and the first gate structure may form a plurality of underlying transistors.

It should be noted that, for convenience of description, the first source-drain structure in the embodiments of the present application is referred to simply as a first source structure and/or a first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, the source-drain groove and the like are similar to those of the first source-drain structure, wherein 'source-drain' is abbreviated as 'source electrode and/or drain electrode'.

It is to be appreciated that a plurality of first dummy gate structures can be formed on the first portion of the fin structures based on the exposed first portion of the plurality of fin structures. The first dummy gate structure overlies the top surface and sidewalls of the fin structure located within the gate region. And forming a first dummy gate side wall on the side wall of the first dummy gate structure. And then forming a first source drain structure in the first dummy gate structure and the first part of the fin structure at two sides of the first dummy gate side wall. And depositing a semiconductor material on the first source drain structure, and removing the top surface of the semiconductor material by adopting a chemical mechanical planarization process to form a first interlayer dielectric layer with the top surface flush with the top surface of the first pseudo gate structure. And then removing the virtual first pseudo gate structure by adopting a wet etching process and/or a dry etching process to form a gate trench. Depositing an insulating material at the gate trench to form a first gate dielectric layer; a metal material is deposited to form a first gate electrode layer.

In an embodiment, the method for forming the first dummy gate structure and the first dummy gate sidewall may include: and a deposition process can be adopted to deposit materials such as silicon dioxide and the like on the surface of the fin structure to form a pseudo gate dielectric layer. And then, at least one of polysilicon, amorphous silicon, germanium (Ge), silicon germanium (SiGe) and silicon carbon (SiC) is deposited on the surface of the pseudo gate dielectric layer to form a first pseudo gate structure. And forming first pseudo gate side walls on the side walls of the first pseudo gate structures through a side wall process, so that the side walls of the first pseudo gate structures are prevented from being damaged in the subsequent process of forming the first source drain structures.

In an embodiment, a method for forming a first source drain structure may include: and forming source and drain grooves in gaps formed by the first dummy gate structures by utilizing a fin structure deep etching process. Thereafter, a first source-drain structure may be formed by epitaxially growing materials such as silicon (Si), silicon-carbon (SiC), carbon silicon-phosphorus (CSiP), silicon germanium (SiGe), silicon germanium boron (SiGeB), silicon germanium gallium (sigga), silicon germanium indium (sigin), and silicon germanium boron indium (sigbin) in the source-drain grooves based on the source-drain grooves.

In one embodiment, the semiconductor material forming the first interlayer dielectric layer is an insulating material, and has high insulating properties.

In one embodiment, the first gate structure includes: a first gate dielectric layer and a first gate electrode layer. The materials of the gate dielectric layer and the gate electrode layer may be set according to actual requirements, which is not specifically limited in the embodiment of the present application.

By way of example, the first gate dielectric layer may be formed of a silicon oxide layer plus a K-value hafnium oxide layer, and the thickness of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

By way of example, the first gate electrode layer may be composed of multiple layers of electrode materials, each layer of electrode material including, but not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

In an example, the first gate dielectric layer may include: a 0.6nm silicon oxide layer and a 1.7nm hafnium oxide layer.

In one embodiment, after forming the first interlayer dielectric layer and the first gate structure, a source-drain contact hole may be formed in the first interlayer dielectric layer, and a conductive material may be deposited in the source-drain contact hole, thereby forming a first source-drain metal.

Here, the top surface of the first source drain metal is flush with the top surface of the first interlayer dielectric layer.

In some possible embodiments, after forming the first source drain metal, forming the first semiconductor structure based on the first portion in S102 includes: a back etching process is used to remove a first portion of the first source drain metal in the first semiconductor structure to form a recess (i.e., a second recess). An insulating material (i.e., a fourth insulating material) is deposited within the recess to form a barrier layer (i.e., a second barrier layer).

The insulating material for forming the barrier layer is different from the insulating material for forming the first single diffusion partition structure in the subsequent step, so that the selectivity of the etching barrier layer is different from the selectivity of the first single diffusion partition structure formed in the subsequent step.

Here, a projection area of the groove formed in the first source drain metal toward the first source drain structure is smaller than a projection area of the first source drain metal toward the first source drain structure. And the depth of the groove formed in the first source drain metal is smaller than that of the first source drain metal.

It can be appreciated that the first portion on the first source drain metal can be removed by a back etching process, and the second portion is left, so that a recess is formed without exposing the first source drain structure. And the top surface of the second part of the first source drain metal is flush with the top surface of the first interlayer dielectric layer, so that the first metal interconnection layer can be in direct contact with the second part of the first source drain metal when the first metal interconnection layer is formed later, and the electric connection between the first source drain structure and the first metal interconnection layer is ensured.

It can be understood that the selectivity of the second barrier layer is different from the selectivity of the first single diffusion partition structure formed in the subsequent step of etching, so that in the subsequent step of etching the first single diffusion partition structure, the existence of the second barrier layer can ensure that the first source drain metal is not damaged by etching, and on the other hand, the etching precision requirement can be reduced, so that under the condition of low etching precision, the self-aligned etching of the first single diffusion partition structure can be realized based on the etching selectivity between the isolation layer and the first single diffusion partition structure, and the through hole (namely the second through hole) for forming the interconnection through hole structure is obtained.

By way of example, the insulating material forming the barrier layer may be titanium oxide (TiOx), aluminum oxide (AlOx), or the like.

In some embodiments, removing the first portion of the first source drain metal in the first semiconductor structure using the etch back process to form the second recess may include: and removing a first part of the first source drain metal adjacent to the single diffusion isolation region in the first semiconductor structure by adopting a back etching process so as to form a second groove.

Wherein the single diffusion isolation region is used to form a single diffusion barrier structure (Singlediffusion break, SDB) that can separate the fin structure into a plurality of small fins, thereby being used to form a plurality of transistors.

It may be appreciated that when forming the recess on the first source-drain metal in the first semiconductor structure, a first portion of the first source-drain metal adjacent to the single diffusion isolation region may be selectively removed by a back etching process based on a positional relationship between the source-drain metal and the single diffusion isolation region in the plurality of transistors, and a barrier layer may be formed at the first portion, so that the first single diffusion isolation structure may be self-aligned etched in a subsequent step. Meanwhile, the first source drain metal which is not adjacent to the single diffusion isolation region is not required to be etched, so that the process steps are effectively reduced, and the preparation efficiency is improved.

And S103, after removing the first gate structure and the first part of the fin structure in the single diffusion isolation region of the first semiconductor structure, depositing a first insulating material in the single diffusion isolation region to form a first single diffusion isolation structure.

It is appreciated that the first gate structure in the single diffusion isolation region of the first semiconductor structure may be removed by an etching process, followed by removal of the first portion of the fin structure in the single diffusion isolation region such that a blocking trench is formed in the single diffusion isolation region. Subsequently, an insulating material (i.e., a first insulating material) is deposited within the isolation trenches, forming a first single diffusion isolation structure.

The first single diffusion separation structure is used for at least isolating the first transistor and the second transistor in the first semiconductor structure. The first transistor and the second transistor are lower-layer transistors, and are formed by the first source-drain structure, the first grid structure, the first source-drain metal and other structures formed in the steps.

Here, the insulating material forming the first single diffusion barrier structure is different from the insulating material forming the barrier layer, and the two materials can be selectively removed by a selective etching process.

For example, the insulating material forming the first single diffusion barrier structure may be silicon nitride (SiN).

In some possible embodiments, an interconnect via structure is formed within the single diffusion isolation region, the interconnect via structure comprising: a first interconnect via structure and a second interconnect via structure. After forming the first single diffusion barrier structure at S103, the method further comprises: etching the first single diffusion partition structure to form a second through hole; depositing a layer of insulating material on the inner wall of the second through hole to form a second isolation layer; a metal material is deposited inside the second via to form a first interconnect via structure.

Wherein the second isolation layer is for isolating the first interconnect via structure and the first portion of the fin structure.

It is appreciated that a photoresist forming an interconnect via structure may be deposited over the first single diffusion barrier structure and used as an etch mask. And under the protection of the etching mask, etching is performed on the first single diffusion partition structure which is not protected by the etching mask, so as to form a through hole (namely, a second through hole). Here, the depth of the via is the same as the depth of the first single diffusion barrier structure, such that the second portion of the fin structure may be exposed after the via is formed. Then, depositing a layer of insulating material on the inner wall of the through hole, and etching the insulating material at the bottom of the through hole to form an isolation layer (namely a second isolation layer); and depositing a metal material in the through hole, so that the isolation layer wraps the metal material, and forming a first interconnection through hole structure.

Here, the insulating material forming the isolation layer may be silicon nitride (SiN), silicon oxide (SiOx), or the like.

Wherein the steps of the lithographic technique may include: depositing photoresist material, exposing and developing the photoresist material, removing a portion of the photoresist material, etching to remove a material layer corresponding to the portion of the photoresist material, and the like.

In some possible embodiments, a barrier layer is formed on the first source drain metal prior to etching the first single diffusion barrier structure, and the first single diffusion barrier structure may be selectively etched until a second portion of the fin structure is exposed to form the second via hole in a self-aligned manner while etching the first single diffusion barrier structure.

It can be appreciated that since the selectivity of the etching to the first dummy gate sidewall and the barrier layer outside the first single diffusion barrier structure is different, self-aligned etching of the first single diffusion barrier structure can be achieved.

In some possible embodiments, after S103, the method further comprises: a first metal interconnect layer is formed over the first single diffusion barrier structure.

It will be appreciated that the first metal interconnect layer may be formed over the first single diffusion barrier structure, or over the first single diffusion barrier structure with the first interconnect via structure formed therein, by a subsequent process of semiconductor fabrication (e.g., dielectric deposition between interconnect lines, metal line formation, lead-out pad formation, etc.).

In some embodiments, the first metal interconnect layer comprises: the first interconnection sub-layer is in direct contact with the first source-drain metal and the first interconnection through hole structure and can be also understood as M0 metal; the second interconnect sublayer is in direct contact with the first interconnect sublayer and can also be understood as the M1 metal.

It is understood that the first source drain metal is electrically connected to the first interconnect via structure by the M0 metal and the M1 metal.

S104, rewinding the first semiconductor structure and removing the semiconductor substrate to expose the second portion of the fin structure.

It is appreciated that after forming the first semiconductor structure comprising the first source drain structure, the first gate structure, the first source drain metal, and the first metal interconnect layer, the first semiconductor structure is bonded to the carrier wafer. And then, turning over the first semiconductor structure and removing the semiconductor substrate to expose the second part of the fin structure, so that the second part of the fin structure is convenient for subsequent preparation of the upper transistor.

In one embodiment, an insulating material (e.g., silicon oxide) may be deposited over the first metal interconnect layer to form a first insulating layer and bond the first insulating layer to the carrier wafer.

In one embodiment, the semiconductor substrate may be removed after rewinding using a polishing process or a chemical mechanical planarization process.

S105, forming a second semiconductor structure based on the second portion.

Here, the second semiconductor structure is sequentially arranged with a second gate structure and a second source-drain structure in an extension direction of the fin structure.

It is appreciated that, based on the second portion of the fin structure, the second source-drain structure and the second gate structure may be formed alternately in sequence in the extending direction of the fin structure using standard processes for semiconductor fabrication.

The second source-drain structure and the second gate structure may be a source-drain structure and a gate structure in an upper transistor, respectively. The second source-drain structure and the second gate structure may form a plurality of upper layer transistors.

It should be noted that, the process of forming the second semiconductor structure may refer to the process of forming the first semiconductor structure, and will not be described herein for brevity.

It should be noted that the semiconductor material forming the second semiconductor structure may be the same as or different from the semiconductor material forming the first semiconductor structure, which is not specifically limited in the embodiments of the present application.

In some possible embodiments, after forming the second source drain metal, forming a second semiconductor structure based on the second portion in S105 includes: a back etching process is used to remove the first portion of the second source drain metal in the second semiconductor structure to form a recess (i.e., a first recess). An insulating material (i.e., a third insulating material) is deposited within the recess to form a barrier layer (i.e., a first barrier layer).

The semiconductor material forming the first barrier layer is different from the material forming the second single diffusion partition structure in the subsequent step, so that the selectivity of etching the first barrier layer is different from the selectivity of etching the second single diffusion partition structure formed in the subsequent step.

In one embodiment, the second single diffusion barrier structure and the first single diffusion barrier structure are etched simultaneously when the interconnect via structure is formed, and therefore, the selectivity of etching the first barrier layer may also be different from the selectivity of etching the second single diffusion barrier structure and the first single diffusion barrier structure.

Here, a projection area of the groove formed in the second source drain metal toward the second source drain structure is smaller than a projection area of the second source drain metal toward the second source drain structure. And the depth of the groove formed in the second source drain metal is smaller than that of the second source drain metal.

It can be appreciated that the first portion on the second source drain metal can be removed by a back etching process, and the second portion is retained, forming a recess that does not expose the second source drain structure. And the top surface of the second part of the second source drain metal is flush with the top surface of the second interlayer dielectric layer, so that the second metal interconnection layer can be in direct contact with the second part of the second source drain metal when the second metal interconnection layer is formed later, and the electrical connection between the second source drain structure and the second metal interconnection layer is ensured.

It can be understood that the selectivity of etching the first barrier layer is different from the selectivity of the second single diffusion partition structure formed in the subsequent step of etching, so that in the subsequent step of etching the second single diffusion partition structure, the presence of the first barrier layer can ensure that the second source drain metal is not damaged by etching, and on the other hand, the etching precision requirement can be reduced, so that under the condition of low etching precision, the self-aligned etching of the second single diffusion partition structure can be realized based on the etching selectivity between the first barrier layer and the second single diffusion partition structure, and the through hole (i.e., the first through hole) for forming the interconnection through hole structure is obtained.

In some embodiments, removing the first portion of the second source drain metal in the first semiconductor structure using the etch back process to form the first recess may include: and removing a first part of the second source drain metal adjacent to the single diffusion isolation region in the second semiconductor structure by adopting a back etching process so as to form a first groove.

It will be appreciated that when forming the recess on the second source-drain metal in the second semiconductor structure, a first portion of the second source-drain metal adjacent to the single diffusion isolation region may be selectively removed by a back etching process based on a positional relationship between the source-drain metal and the single diffusion isolation region in the plurality of transistors, and a barrier layer may be formed at the first portion, so that the second single diffusion isolation structure may be self-aligned etched in a subsequent step. Meanwhile, the second source drain metal which is not adjacent to the single diffusion isolation region is not required to be etched, so that the process steps are effectively reduced, and the preparation efficiency is improved.

And S106, removing the second gate structure and the second part of the fin structure in the single diffusion isolation region of the second semiconductor structure, and depositing a second insulating material in the single diffusion isolation region to form a second single diffusion isolation structure.

It is appreciated that the second gate structure within the single diffusion isolation region of the second semiconductor structure may be removed by an etching process followed by removal of the second portion of the fin structure within the single diffusion isolation region such that a blocking trench is formed within the single diffusion isolation region. Subsequently, an insulating material (i.e., a second insulating material) is deposited within the isolation trenches, forming a second single diffusion isolation structure.

Wherein the second single diffusion barrier structure is at least used to isolate the third transistor and the fourth transistor in the second semiconductor structure. The third transistor and the fourth transistor are upper-layer transistors, and are formed by the second source-drain structure, the second grid structure, the second source-drain metal and other structures formed in the steps.

Here, the insulating material forming the second single diffusion barrier structure is different from the insulating material forming the first barrier layer, and the two materials can be selectively removed by a selective etching process.

In some possible implementations, the interconnect via structure includes: a first interconnect via structure and a second interconnect via structure, the first interconnect via structure having been formed in the first semiconductor structure, the second interconnect via structure may be formed in the second semiconductor structure. Then, after forming the second single diffusion barrier structure at S106, the method further comprises: etching the second single diffusion partition structure until the first interconnection through hole structure is exposed, so as to form a third through hole; depositing a layer of insulating material on the inner wall of the third through hole to form a third isolation layer; a metal material is deposited inside the third via to form a second interconnect via structure.

Wherein the third isolation layer is for isolating the second interconnect via structure and the second portion of the fin structure.

It will be appreciated that a photoresist forming the interconnect via structure may be deposited over the second single diffusion barrier structure and used as an etch mask. Etching is performed on the second single diffusion barrier structure which is not protected by the etching mask under the protection of the etching mask, so as to form a through hole (namely a third through hole) exposing the first interconnection through hole structure. Here, the depth of the via hole is the same as the depth of the second single diffusion barrier structure, so that the first interconnection via structure may be exposed after the via hole is formed. Then, depositing a layer of insulating material on the inner wall of the through hole, and etching the insulating material at the bottom of the through hole to form an isolation layer (namely a third isolation layer); and depositing a metal material in the through hole, so that the isolation layer wraps the metal material, and forming a second interconnection through hole structure.

In some possible embodiments, a barrier layer is formed on the second source drain metal prior to etching the second single diffusion barrier structure, and the second single diffusion barrier structure may be selectively etched until the first interconnect via structure is exposed to form a third via in self-alignment while the second single diffusion barrier structure is etched.

It can be appreciated that since the selectivity of the etching to the second dummy gate sidewall and the barrier layer outside the second single diffusion barrier structure is different, self-aligned etching of the second single diffusion barrier structure can be achieved.

In some possible embodiments, when only the first single diffusion partition structure is formed in the first semiconductor structure and the interconnection via structure is not formed, the interconnection via structure may be formed after the second single diffusion partition structure is formed, and the interconnection via structure may pass through the second single diffusion partition structure and the first single diffusion partition structure. As such, after forming the second single diffusion barrier structure at S106, the method further comprises: sequentially etching the second single diffusion barrier structure and the first single diffusion barrier structure to form a through hole (i.e., a first through hole); depositing a layer of insulating material on the inner wall of the through hole to form an isolation layer (namely a first isolation layer); a metal material is deposited inside the first via to form an interconnect via structure.

The first isolation layer is used for isolating the interconnection through hole structure and the fin-shaped structure.

It is understood that the method of forming the first via hole and the first isolation layer may refer to the method of forming the third via hole and the third isolation layer. The difference is that the depth of the first via is equal to the sum of the depths of the second single diffusion barrier structure and the first single diffusion barrier structure, so that after depositing the metal material in the first via, an interconnect via structure that communicates the first metal interconnect layer and the second metal interconnect layer formed in a subsequent step can be directly formed.

In some possible embodiments, a barrier layer is formed on the second source drain metal prior to etching the second single diffusion barrier structure, and the second single diffusion barrier structure and the first single diffusion barrier structure may be selectively etched until the first metal interconnect layer is exposed to form the first via hole in self-alignment while the second single diffusion barrier structure is etched.

In some possible embodiments, after S106, the method further comprises: a second metal interconnect layer is formed over the second single diffusion barrier structure.

It is understood that the process of forming the second metal interconnection layer on the second single diffusion barrier structure may refer to the description in S103, and will not be repeated herein for brevity of the description.

Further, in the embodiment of the application, by performing one-step back etching after the source and drain metal is formed and backfilling with the insulating material, when the interconnection through hole structure is formed in the single diffusion partition structure, the through holes required by the interconnection through hole structure can be etched in the single diffusion partition structure in a self-aligned manner and the metal is filled, so that the self-aligned direct connection of the stacked transistors is realized.

The following is a brief description of the fabrication process of the stacked transistor in the embodiment of the present application, in conjunction with the fabrication method of the stacked transistor shown in fig. 1. Fig. 2 is a schematic top view of a stacked transistor in an embodiment of the present application. It should be noted that, for ease of understanding, only fin structures, gate structures, source-drain structures, single diffusion barrier structures, interconnect via structures, and metal interconnect structures are shown in top view. Fig. 3 to 22 are schematic diagrams illustrating a first process of manufacturing a stacked transistor according to an embodiment of the present application, wherein (a) in fig. 3 to (a) in fig. 22 are cross-sectional views along a tangential direction (i.e., A-A 'direction) of a single diffusion barrier structure, and (B) in fig. 3 to (B) in fig. 22 are cross-sectional views along a tangential direction (i.e., B-B' direction) of a source-drain structure; fig. 3 (C) to 22 (C) are sectional views taken along the sectional direction (i.e., the C-C' direction) of the fin structure.

In one example, the first fabrication process of stacked transistor 10 may include the steps of:

the first step: a fin structure is formed on the silicon substrate 21 and the filling and etching back of the shallow trench isolation structure 22 is completed, resulting in the structure shown in fig. 3.

Here, the shallow trench isolation structure 22 wraps around the second portion of the fin structure, exposing the first portion of the fin structure. The fin structure is used to form the active structure of the upper and lower transistor layers, and thus the fin structure may have a thickness greater than 100nm.

And a second step of: polysilicon material is deposited in the gate region on the substrate shown in fig. 3 to form a first dummy gate structure 23, and a first dummy gate sidewall 111 is formed on the sidewall of the first dummy gate structure 23. Subsequently, the first portion of the fin structure of the source drain region is etched to a predetermined height to form a first source drain recess 24 in the source drain region, resulting in the structure shown in fig. 4.

And a third step of: a first source-drain structure 112 is epitaxially grown based on the first source-drain recess 24, followed by deposition of an insulating material in the source-drain region to form a first interlayer dielectric layer 113, resulting in the structure shown in fig. 5.

Fourth step: the first dummy gate structure 23 in the structure shown in fig. 5 is removed, and an insulating material and a metal material are sequentially deposited in the removed gate region to form a first gate dielectric layer 114 and a first gate electrode layer 115, thereby obtaining the structure shown in fig. 6.

Fifth step: a hole is formed in the first interlayer dielectric layer 113 shown in fig. 6, and a metal material is deposited to form a first source drain metal 116, so as to obtain the structure shown in fig. 7.

Sixth step: the first source drain metal 116 shown in fig. 7 is etched back to form a second recess 25, resulting in the structure shown in fig. 8.

It should be noted that only the source drain metal adjacent to the single diffusion barrier region may be etched back here.

Seventh step: a fourth insulating material (e.g., titanium oxide) is deposited at the second recess 25 shown in fig. 8 to form a second barrier layer 26, resulting in the structure shown in fig. 9.

Eighth step: the first gate structure (including the first gate dielectric layer 114 and the first gate electrode layer 115) within the single diffusion break region and the first portion of the fin structure within the single diffusion break region are removed to obtain the structure shown in fig. 10.

Ninth step: a first insulating material (e.g., silicon nitride) is deposited in the single diffusion barrier region shown in fig. 10 to form a first single diffusion barrier structure 117, resulting in the structure shown in fig. 11.

It should be noted that the single diffusion barrier region may be any single diffusion barrier region within the semiconductor standard cell.

Tenth step: a first photoresist 27 is deposited over the structure shown in fig. 11, resulting in the structure shown in fig. 12.

Here, the first photoresist 27 may serve as a mask to block etching of the structure covered by the first photoresist 27.

Eleventh step: the first single diffusion barrier structure 117 of the single diffusion barrier region is etched self-aligned under the protection of the first photoresist 27 shown in fig. 12 to form a second via 28, resulting in the structure shown in fig. 13.

Here, the second via is used to form an interconnect via structure after subsequent deposition of the metal material.

Note that, since the selectivity of the etching to the backfill of the second barrier layer 26 on the first dummy gate sidewall 111 and the first source drain metal 116 adjacent to the first single diffusion barrier structure 117 is different, the self-aligned etching of the first single diffusion barrier structure 117 may be achieved.

Twelfth step: the first photoresist 27 shown in fig. 13 is removed and a layer of insulating material (e.g., silicon nitride) is deposited on the inner walls of the second via 28 to form a second isolation layer 29, resulting in the structure shown in fig. 14.

Thirteenth step: a metal material is deposited in the second via 28 shown in fig. 14, forming a first interconnect via structure 30, resulting in the structure shown in fig. 15.

It should be noted that the second isolation layer 29 may protect the first interconnect via structure 30 from contact with the first portion of the fin structure.

Fourteenth step: a first metal interconnect layer 118 is formed over the structure shown in fig. 15 using a subsequent process in the semiconductor fabrication method, resulting in the structure shown in fig. 16.

Fifteenth step: depositing an insulating oxide over the structure shown in fig. 16, forming an insulating layer 31; above the insulating layer 31, a carrier wafer 32 is bonded to the insulating layer 31, and then rewound, resulting in the structure shown in fig. 17.

Sixteenth step: the substrate 21 in the structure shown in fig. 17 is removed using a chemical mechanical planarization process, exposing a second portion of the active structure, resulting in the structure shown in fig. 18.

Seventeenth step: the shallow trench isolation structure 22 shown in fig. 18 is etched to a depth to expose a second portion of the fin structure. Based on the second portion of the fin structure, the second dummy gate sidewall 121, the second source-drain structure 122, the second interlayer dielectric layer 123, and the second gate structure (including the second gate dielectric layer 124 and the second gate electrode layer 125) are formed by the same process as in the second step to the fourth step, to obtain the structure shown in fig. 19.

Eighteenth step: the second source drain metal 126 and the third barrier layer 33 are formed using the same process as in the fifth to seventh steps, resulting in the structure shown in fig. 20.

Nineteenth step: the second gate structure and the shallow trench isolation structure 22 in the single diffusion barrier structure region are removed, and a second single diffusion barrier structure 127 is formed in the single diffusion barrier structure region, and a third isolation layer 39 and a second interconnect via structure 34 are formed in the second single diffusion barrier structure 127, by the same process as in the eighth to thirteenth steps, to obtain the structure shown in fig. 21.

The second insulating material forming the second single diffusion barrier structure 127 may be the same as or different from the first insulating material forming the first single diffusion barrier structure 117.

Twenty-step: a second metal interconnect layer 128 is formed over the structure shown in fig. 21 using a subsequent process in the semiconductor fabrication method, resulting in the structure shown in fig. 22.

Thus, the preparation of the stacked transistor is completed, and the upper layer transistor and the lower layer transistor of the stacked transistor are self-aligned.

Fig. 23 to 30 are schematic views illustrating a second process for manufacturing a stacked transistor according to an embodiment of the present application, wherein (a) in fig. 23 to (a) in fig. 30 are cross-sectional views along a tangential direction (i.e., A-A 'direction) of a single diffusion barrier structure, and (B) in fig. 23 to (B) in fig. 30 are cross-sectional views along a tangential direction (i.e., B-B' direction) of a source-drain structure; fig. 23 (C) to 30 (C) are sectional views taken along the sectional direction (i.e., the C-C' direction) of the fin structure.

In one example, the second fabrication process of stacked transistor 10 may include the steps of:

the first step: the structure shown in fig. 23 is obtained by the same process as in the first to ninth steps in the first production process.

The sixth and seventh steps in the first preparation process are not necessarily performed in the second preparation process.

And a second step of: a first metal interconnect layer 118 is formed over the structure shown in fig. 23 using a subsequent process in the semiconductor fabrication method, resulting in the structure shown in fig. 24.

And a third step of: the second dummy gate sidewall 121, the second source-drain structure 122, the second interlayer dielectric layer 123, the second gate structure (including the second gate dielectric layer 124 and the second gate electrode layer 125), the second source-drain metal 126 and the first barrier layer 35 are formed by the same process as in the fifteenth to eighteenth steps in the first manufacturing process, to obtain the structure shown in fig. 25.

Fourth step: the second gate structure (including the second gate dielectric layer 124 and the second gate electrode layer 125) within the single diffusion break region and the second portion of the fin structure within the single diffusion break region are removed. And a second insulating material (e.g., silicon nitride) is deposited within the single diffusion barrier regions to form a second single diffusion barrier structure 127, resulting in the structure shown in fig. 26.

Fifth step: a second photoresist (not shown) is deposited over the structure shown in fig. 26, and under the protection of the second photoresist, the second single diffusion barrier structure 127 and the first single diffusion barrier structure 117 of the single diffusion barrier region are etched in a self-aligned manner to form a first via 36; the second photoresist is then removed, resulting in the structure shown in fig. 27.

Sixth step: a layer of insulating material (e.g., silicon nitride) is deposited on the inner walls in the first via holes 36 shown in fig. 27 to form a first isolation layer 37, resulting in the structure shown in fig. 28.

Seventh step: a metal material is deposited in the first via 36 shown in fig. 28 to form an interconnect via structure 38, resulting in the structure shown in fig. 29.

It should be noted that the first isolation layer 37 may protect the interconnect via structure 38 from contact with the fin structure.

Eighth step: a second metal interconnect layer 128 is formed over the structure shown in fig. 29 using a subsequent process in the semiconductor fabrication method, resulting in the structure shown in fig. 30.

Fig. 31 is a schematic diagram of a first structure of a stacked transistor in an embodiment of the present application. Fig. 32 is a schematic diagram of a second structure of a stacked transistor in an embodiment of the present application. Fig. 31 and 32 (a) are schematic top views of stacked transistors in the embodiment of the present application. It should be noted that, for ease of understanding, only fin structures, gate structures, source-drain structures, single diffusion barrier structures, interconnect via structures, and metal interconnect structures are shown in top view. Fig. 31 and 32 (B) are sectional views taken along the tangential direction (i.e., the A-A 'direction) of the single diffusion barrier structure, and fig. 31 and 32 (c) are sectional views taken along the tangential direction (i.e., the B-B' direction) of the metal interconnection structure.

In the embodiment of the present application, as shown in conjunction with fig. 22, 30, 31 and 32, the stacked transistor 10 may include at least four transistors, for example, a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor and the second transistor are both upper-layer transistors, and the third transistor and the fourth transistor are both lower-layer transistors. The first transistor and the third transistor may be disposed opposite each other, and the second transistor and the fourth transistor may be disposed opposite each other.

In one embodiment, electrical isolation between the first transistor and the second transistor in the upper layer transistor may be achieved by the first single diffusion barrier structure 117 and the second isolation layer 29. Electrical isolation between the third and fourth ones of the underlying transistors may be achieved by the second single diffusion barrier structure 127 and the third isolation layer 39.

In one embodiment, electrical isolation may be achieved between the first transistor and the second transistor in the upper layer transistor and between the third transistor and the fourth transistor in the lower layer transistor by the first single diffusion barrier structure 117, the second single diffusion barrier structure 127, and the first isolation layer 37.

In one embodiment, the upper layer transistor communicates with the first metal interconnect layer 118 and the lower layer transistor communicates with the second metal interconnect layer 128. The first metal interconnection layer 118 and the second metal interconnection layer 128 are located at two opposite ends of the stacked transistor 10, so that space occupied by the metal interconnection layers is saved, and the size of the vertical transistor is further reduced; on the other hand, when a plurality of stacked transistors are stacked, the upper transistor and the lower transistor can be aligned, so that the symmetry of the device is improved, and the wiring length of the metal interconnection layer is effectively shortened.

In one embodiment, in the stacked transistor 10, the first active structure in the upper transistor and the second active structure in the lower transistor are formed by the same process, and at this time, it can be understood that the upper transistor and the lower transistor are self-aligned.

It will be appreciated that, as shown by the dashed boxes in fig. 31 and 32, the first interconnect via structure 30 and the second interconnect via structure 34 are formed before and after rewinding in the first manufacturing process, respectively, and the first interconnect via structure 30 and the second interconnect via structure 34 are connected at the junction of the upper and lower layers of the stacked transistor 10, thereby achieving the direct connection of the upper and lower metal interconnect layers.

After rewinding in the second manufacturing process, the interconnection via structure 38 passing through the second single diffusion barrier structure 127 and the first single diffusion barrier structure 117 is formed at one time, so as to realize the direct connection of the upper and lower metal interconnection layers.

In the two preparation processes, the interconnection through hole structure of the upper and lower transistors is located in the single diffusion partition structure inside the stacked transistor unit, so that more space is not occupied, the area of the standard stacked transistor unit is not increased, and the integration level of the stacked transistor is effectively improved.

In one or more embodiments for preparing the stacked transistor, not only the process flow of the stacked transistor can be greatly simplified, but also the consistency of the active structure and the gate structure of the upper and lower transistors can be considered. In particular, the grid electrode structure and the active structure of the upper and lower layers of transistors are self-aligned and stacked, so that the problems of complex process, difficult alignment and the like in the existing mainstream technical scheme of stacked transistors are solved, and the promotion of the industrialization of transistor stacking technology is realized. On the other hand, by the self-aligned back-to-back active structure and grid structure, the upper transistor and the lower transistor can have independent signal and power supply network and are connected through local interconnection, and under the condition of not changing the design of the extremely miniature 4T track unit, the metal wiring resource is greatly released.

Finally, the scheme of realizing the upper and lower transistors through the rewinding is compatible with the existing mainstream device architecture, and the front and back stacking comprising a planar transistor, a FinFET, a GAA Nanosheet and even a vertical transistor (VTFET) can be realized without special process development aiming at a specific device architecture, so that the flexibility is high, and the extensibility is very high from the iteration point of a semiconductor processing node. The flip-chip transistor is very advanced in concept, has important industrial value, and has strong practicability and wide expansion prospect.

The embodiment of the application provides a semiconductor device, which comprises: stacked transistors as in the above embodiments. Specific limitations of the stacked transistor can be found in the stacked transistors shown in fig. 22, 30, 31 and 32, and are not described herein.

An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device comprises the semiconductor structure. The specific limitation of the semiconductor structure may be referred to the semiconductor structure shown in fig. 1 and will not be described herein.

In the description of the present application, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In this application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described herein, as well as the features of the various embodiments or examples, may be combined by those skilled in the art without contradiction.

The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and variations may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method of interconnecting stacked transistors, the method comprising:

forming a fin structure on a semiconductor substrate; the fin structure includes a first portion and a second portion, the first portion being remote from the semiconductor substrate relative to the second portion;

forming a first semiconductor structure based on the first portion; the first semiconductor structures are sequentially and alternately arranged with first grid structures and first source-drain structures in the extending direction of the fin-shaped structures;

removing a first gate structure and a first part of a fin structure in a single diffusion isolation region of the first semiconductor structure, and depositing a first insulating material in the single diffusion isolation region to form a first single diffusion isolation structure; the first single diffusion barrier structure is used for isolating at least a first transistor and a second transistor in the first semiconductor structure;

Rewinding the first semiconductor structure and removing the semiconductor substrate to expose a second portion of the fin structure;

forming a second semiconductor structure based on the second portion; the second semiconductor structures are sequentially and alternately arranged with second grid structures and second source-drain structures in the extending direction of the fin-shaped structures;

removing the second gate structure and the second part of the fin structure in the single diffusion isolation region of the second semiconductor structure, and depositing a second insulating material in the single diffusion isolation region to form a second single diffusion isolation structure; the second single diffusion barrier structure is used for isolating at least a third transistor and a fourth transistor in the second semiconductor structure; the single diffusion isolation region of the second semiconductor structure is overlapped with the single diffusion isolation region of the first semiconductor structure;

wherein an interconnection through hole structure is formed in the first single diffusion partition structure and the second single diffusion partition structure; the interconnect via structure is for connecting with a first metal interconnect layer located on the first semiconductor structure and a second metal interconnect layer located on the second semiconductor structure.

2. The method of claim 1, wherein the second semiconductor structure further comprises a second source drain metal formed over the second source drain structure;

the forming a second semiconductor structure based on the second portion includes:

removing a first part of the second source drain metal in the second semiconductor structure by adopting a back etching process so as to form a first groove; the projection area of the first groove projected towards the second source drain structure is smaller than the projection area of the second source drain metal projected towards the second source drain structure; the depth of the first groove is smaller than that of the second source drain metal;

depositing a third insulating material in the first groove to form a first barrier layer; the selectivity of the third insulating material is different from the selectivity of the first insulating material and the second insulating material.

3. The method of claim 2, wherein after the forming the second single diffusion barrier structure, the method further comprises:

etching the second single diffusion partition structure and the first single diffusion partition structure in sequence to form a first through hole;

depositing a layer of insulating material on the inner wall of the first through hole to form a first isolation layer;

Depositing a metal material inside the first via to form the interconnect via structure; the first isolation layer is used for isolating the interconnection through hole structure and the fin-shaped structure.

4. The method of claim 3, wherein the sequentially etching the second single diffusion barrier structure and the first single diffusion barrier structure to form a first via comprises:

the second single diffusion barrier structure and the first single diffusion barrier structure are selectively etched to form the first via in self-alignment.

5. The method of claim 2, wherein the first semiconductor structure further comprises a first source drain metal formed over the first source drain structure;

the forming a first semiconductor structure based on the first portion includes:

removing a first part of the first source drain metal in the first semiconductor structure by adopting a back etching process so as to form a second groove; the projection area of the second groove projected towards the first source drain structure is smaller than the projection area of the first source drain metal projected towards the first source drain structure; the depth of the second groove is smaller than that of the first source drain metal;

Depositing a fourth insulating material in the second groove to form a second barrier layer; the selectivity of etching the fourth insulating material is different from the selectivity of etching the first insulating material.

6. The method of claim 5, wherein the interconnect via structure comprises: a first interconnect via structure and a second interconnect via structure;

after the forming the first single diffusion barrier structure, the method further comprises:

etching the first single diffusion partition structure to form a second through hole;

depositing a layer of insulating material on the inner wall of the second through hole to form a second isolation layer;

depositing a metal material inside the second via to form the first interconnect via structure; the second isolation layer is used for isolating the first interconnection through hole structure and the first part of the fin-shaped structure;

after the forming the second single diffusion barrier structure, the method further comprises:

etching the second single diffusion partition structure until the first interconnection through hole structure is exposed, so as to form a third through hole;

depositing a layer of insulating material on the inner wall of the third through hole to form a third isolation layer;

depositing a metal material inside the third via to form the second interconnect via structure; the third isolation layer is used to isolate the second interconnect via structure from the second portion of the fin structure.

7. The method of claim 6, wherein the etching the first single diffusion barrier structure to form a second via comprises:

selectively etching the first single diffusion barrier structure until a second portion of the fin structure is exposed to self-align to form the second via;

the etching the second single diffusion barrier structure until the first interconnect via structure is exposed to form a third via, comprising:

the second single diffusion barrier structure is selectively etched until the first interconnect via structure is exposed to form the third via self-aligned.

8. The method of claim 5, wherein removing the first portion of the second source drain metal in the second semiconductor structure using a back-etching process to form a first recess comprises:

removing a first part of the second source drain metal adjacent to the single diffusion isolation region in the second semiconductor structure by adopting a back etching process so as to form a first groove;

the removing the first portion of the first source drain metal in the first semiconductor structure by using an etching back process to form a second groove includes:

And removing a first part of the first source drain metal adjacent to the single diffusion isolation region in the first semiconductor structure by adopting a back etching process so as to form a second groove.

9. A stacked transistor fabricated using the interconnect method of any of claims 1 to 8, comprising:

a plurality of lower layer transistors;

a plurality of upper layer transistors, each of the plurality of upper layer transistors and each of the plurality of lower layer transistors being disposed opposite;

the first active structure of the lower transistor and the second active structure of the upper transistor in the two transistors arranged in opposite directions form an active structure, and the first source drain structure of the lower transistor and the second source drain structure of the upper transistor in the two transistors arranged in opposite directions are self-aligned;

a first interconnection through hole structure is formed in a single diffusion isolation region among the plurality of lower-layer transistors; a second interconnection through hole structure is formed in the single diffusion isolation region between the plurality of upper layer transistors; the first interconnection through hole structure is communicated with the second interconnection through hole structure, the first interconnection through hole structure is communicated with a first metal interconnection layer of an underlying transistor, and the second interconnection through hole structure is communicated with a second metal interconnection layer of an overlying transistor.

10. A semiconductor device, comprising: the stacked transistor of claim 9.