CN118016592A

CN118016592A - Method for preparing semiconductor structure, device and equipment

Info

Publication number: CN118016592A
Application number: CN202410120680.4A
Authority: CN
Inventors: 吴恒; 刘煜; 卢浩然; 葛延栋; 王润声; 黎明; 黄如
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2024-01-29
Filing date: 2024-01-29
Publication date: 2024-05-10

Abstract

The application provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment, wherein the method comprises the following steps: gate cutting is performed on the first front gate structure, the first back gate structure, the third front gate structure and the third back gate structure to form a first gate cutting groove and a second gate cutting groove, and gate cutting is performed on the second back gate structure to form a third gate cutting groove; filling insulating materials in the first grid cutting groove, the second grid cutting groove and the third grid cutting groove to form a first grid cutting structure, a second grid cutting structure and a third grid cutting structure; photoetching a part of the second grid cutting structure corresponding to the third back grid structure to form a fourth grid cutting structure and a first groove; and filling a metal material in the first groove to form a grid interconnection metal. By means of the application, a flexible design of electrical interconnections in semiconductor structures can be achieved.

Description

Method for preparing semiconductor structure, device and equipment

Technical Field

The present application relates to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor structure, a device, and equipment.

Background

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors further increase transistor integration density by integrating two or more layers of transistors in vertical space is one of the important technologies continuing the scaling of integrated circuits.

When the stacked transistor (stacked transistor) is fabricated using a conventional sequential scheme, the following technical difficulties exist: it is difficult to implement different metal routing and isolation patterns in multiple stacked transistors of an integrated circuit.

Disclosure of Invention

The application provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment, so as to realize flexible design of electrical interconnection in the semiconductor structure.

In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, where the semiconductor structure includes a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure on the same wafer, the first front gate structure and the first back gate structure of the first semiconductor structure are self-aligned, the second front gate structure and the second back gate structure of the second semiconductor structure are self-aligned, and the third front gate structure and the third back gate structure of the third semiconductor structure are self-aligned; the method comprises the following steps: gate cutting is performed on the first front gate structure, the first back gate structure, the third front gate structure and the third back gate structure to form a first gate cutting groove of the first semiconductor structure and a second gate cutting groove of the third semiconductor structure, and gate cutting is performed on the second back gate structure to form a third gate cutting groove of the second semiconductor structure; filling insulating materials in the first gate cutting groove, the second gate cutting groove and the third gate cutting groove to form a first gate cutting structure of the first semiconductor structure, a second gate cutting structure of the third semiconductor structure and a third gate cutting structure of the second semiconductor structure; photoetching a part of the second grid cutting structure corresponding to the third back grid structure to form a fourth grid cutting structure and a first groove, wherein the fourth grid cutting structure corresponds to the third front grid structure; and filling a metal material in the first groove to form a gate interconnection metal, wherein the gate interconnection metal is used for metal interconnection of the third back gate structure.

In some possible embodiments, the method further comprises: forming an active structure on a substrate; the active structures comprise a first active structure, a second active structure and a third active structure; forming a first semiconductor structure based on the first active structure; forming a second semiconductor structure based on the second active structure; a third semiconductor structure is formed based on the third active structure.

In some possible embodiments, gate cutting is performed on the first front side gate structure, the first back side gate structure, the third front side gate structure, and the third back side gate structure to form a first gate cut groove of the first semiconductor structure and a second gate cut groove of the third semiconductor structure, comprising: coating photoresist above the first back gate structure and the third back gate structure; developing the photoresist to form a first photoresist layer; the first photoresist layer covers a first region in the first back gate structure and a second region in the third back gate structure, the first region is located above the first active structure, and the second region is located above the third active structure; and etching the first back grid structure, the first front grid structure, the third back grid structure and the third front grid structure by taking the first photoresist layer as a mask to form a first grid cutting groove and a second grid cutting groove.

In some possible embodiments, gate cutting is performed on the second back gate structure to form a third gate cut recess of the second semiconductor structure, including: coating photoresist on the second back gate structure; developing the photoresist to form a second photoresist layer; the second photoresist layer covers a third region in the second back gate structure, and the third region is positioned above the second active structure; and etching the second back gate structure by using the second photoresist layer as a mask to form a third gate cutting groove.

In some possible embodiments, photolithography is performed on a portion of the second gate cut structure corresponding to the third back gate structure to form a fourth gate cut structure and a first recess, including: coating photoresist above the third back gate structure; developing the photoresist to form a third photoresist layer; the third photoresist layer covers a fourth region of the third back gate structure, and the fourth region is positioned above the third active structure; and etching a part of the second grid cutting structure corresponding to the third back grid structure by taking the third photoresist layer as a mask so as to form a fourth grid cutting structure and a first groove.

In some possible implementations, the first active structure includes a first portion of the first active structure and a second portion of the first active structure; forming a first semiconductor structure based on the first active structure, comprising: sequentially forming a first front-side source-drain structure, a first front-side interlayer dielectric layer and a first front-side metal interconnection layer of a first semiconductor structure based on a first part of the first active structure; rewinding the first semiconductor structure and removing the substrate; forming a first back source drain structure, a first back interlayer dielectric layer and a first back metal interconnection layer of the first semiconductor structure in sequence based on a second part of the first active structure; wherein the first portion of the first active structure is remote from the substrate relative to the second portion of the first active structure.

In some possible implementations, the wafer further includes a fourth semiconductor structure, the fourth front-side gate structure and the fourth back-side gate structure of the fourth semiconductor structure being self-aligned, the active structure further including a fourth active structure; the method further comprises the steps of: forming a fourth semiconductor structure based on the fourth active structure; the fourth front gate structure and the fourth back gate structure do not perform a gate cut process.

In a second aspect, an embodiment of the present application provides a semiconductor structure, where the semiconductor structure includes at least two of: a first semiconductor structure; the first front grid structure and the first back grid structure of the first semiconductor structure are self-aligned, and the first semiconductor structure comprises a grid cutting structure formed by conducting grid cutting treatment on the first front grid structure and the first back grid structure; a second semiconductor structure; the second front gate structure and the second back gate structure of the second semiconductor structure are self-aligned, and the second semiconductor structure comprises a gate cutting structure formed by performing gate cutting treatment on the second back gate structure; a third semiconductor structure; the third front gate structure and the third back gate structure of the third semiconductor structure are self-aligned, and the third semiconductor structure comprises a gate cutting structure formed by performing gate cutting treatment on the third front gate.

In some possible embodiments, the semiconductor structure further includes: a fourth semiconductor structure; the fourth front gate structure and the fourth back gate structure of the fourth semiconductor structure are self-aligned, and the fourth semiconductor structure does not include a gate cut structure formed by performing a gate cut process on the fourth front gate and the fourth back gate structure.

In a third aspect, an embodiment of the present application provides a semiconductor device including: such as the semiconductor structures of the above embodiments.

In a fourth aspect, an embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board.

In the application, three different forms of grid cutting structures can be realized by cutting the grid of the first front grid structure, the first back grid structure, the third front grid structure and the third back grid structure, cutting the grid of the second back grid structure and photoetching the part of the second grid cutting structure corresponding to the third back grid structure, so that the electrical interconnection in the semiconductor structure is more flexible.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a first semiconductor structure according to an embodiment of the present application;

Fig. 3A to 3E are schematic views illustrating a process for manufacturing a first semiconductor structure according to an embodiment of the present application;

FIG. 4 is a cross-sectional view of a semiconductor structure along a cross-sectional direction of a gate structure according to an embodiment of the present application;

FIG. 5 is a layout of a semiconductor structure in an embodiment of the present application;

FIGS. 6A-6K are schematic diagrams illustrating a process for fabricating a semiconductor structure according to embodiments of the present application;

The figures above:

10. A semiconductor structure; 11. a first semiconductor structure; 12. a second semiconductor structure; 13. a third semiconductor structure; 14. a fourth semiconductor structure; 111. a first front-side transistor; 112. a first back side transistor; 113. an insulating layer; 114. a carrier wafer; 115. a gate dielectric layer; 116. a gate isolation layer; 1111. a first fin structure; 1112. a first front-side source drain structure; 1113. a first front side interlayer dielectric layer; 1114. a first front-side source drain metal; 1115. a first front side metal interconnect layer; 1116. a first front spacer; 1117. a first front gate structure; 1121. a second fin structure; 1122. a first back source drain structure; 1123. a first backside interlayer dielectric layer; 1124. a first back source drain metal; 1125. a first backside metal interconnect layer; 1126. a first back spacer; 1127. a first back gate structure; 1217. a second front gate structure; 1227. a second back gate structure; 1317. a third front gate structure; 1327. a third back gate structure; 1417. a fourth front gate structure; 1427. a fourth back gate structure; 21. a substrate; 211. a bottom Si layer; 212. a sacrificial layer; 213. a top Si layer; 22. a fin structure; 23. a dummy gate structure; 24. shallow trench isolation structures; 241. shallow trench isolation layers; 25. a gate structure; 31. a first photoresist layer; 32. a second photoresist layer; 33. a third photoresist layer; 41. a first gate cut-off structure; 42. a second gate cut-off structure; 43. a third gate cut-off structure; 44. a fourth gate cut-off structure; 45. gate interconnect metal.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.

While moore's law is continually deepening, continuing to advance transistor scaling after the technology node of the full-round gate transistor (GAA) is a hot spot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits.

In one embodiment, the fabrication process of the stacked transistor (stacked transistors) has two schemes, the first is a monolithic stacking scheme and the second is a sequential scheme.

In the first approach, N-channel field effect transistors (N FIELD EFFECT transistors, NFETs) and P-channel field effect transistors (P FIELD EFFECT transistors, PFETs) are fabricated on the same substrate, and wafer bonding techniques are not used. This determines that the same layer transistors must be of the same type, i.e., NFET or PFET. And the transistors on the upper layer and the lower layer are strictly in the same plane space, and no alignment deviation exists. The advantage of this solution is a better integration density. Drawbacks of this approach include the following two points: (1) The process is complex, and a large number of process technologies need to be developed and optimized; (2) Each layer of transistors has a fixed polarity, and two layers of transistors must be relied upon to form a basic Complementary Metal Oxide Semiconductor (CMOS) circuit, which has poor design flexibility.

The second scheme is based on wafer bonding and layer-by-layer processing. Specifically, the two transistors are stacked vertically by bonding a wafer on top of the fabricated lower transistor to prepare the upper transistor. However, this approach requires tight temperature control during the thermal process of processing the upper layer transistors, avoiding affecting the lower layer transistors and the interconnect lines. The scheme has the advantages that the device structure, the channel crystal orientation and even the channel material adopted by the upper layer transistor and the lower layer transistor can be correspondingly optimized to obtain better and more matched device performance due to wafer bonding. This solution currently presents the following technical challenges: (1) preparation of a high-quality upper transistor active layer; (2) thinning and defect control of the upper bonded wafer; (3) The upper and lower layer transistors have alignment errors and have extremely high requirements on photoetching precision.

When a plurality of stacked transistors are integrated in an integrated circuit, since the plurality of stacked transistors in the integrated circuit are prepared in the same batch, the electrical interconnections between the plurality of stacked transistors and the adjacent region adopt the same metal wiring mode, and similarly, the isolation between the plurality of stacked transistors and the adjacent region also adopts the same isolation mode, which makes it impossible to realize different metal wiring modes and isolation modes in the plurality of stacked transistors.

In order to solve the technical problems, the embodiment of the application provides a preparation method of a semiconductor structure, so as to realize flexible design of electrical interconnection in the semiconductor structure.

In the embodiment of the application, the semiconductor structure can be applied to semiconductor devices such as memories, processors and the like.

In one embodiment, the semiconductor structure may be part of an integrated circuit; in the embodiment of the application, four transistors are integrated in the semiconductor structure, for example, a first semiconductor structure, a second semiconductor structure, a third semiconductor structure and a fourth semiconductor structure. The first semiconductor structure, the second semiconductor structure, the third semiconductor structure and the fourth semiconductor structure are stacked transistors, each stacked transistor is composed of a front side transistor and a back side transistor, and the front side transistor and the back side transistor are self-aligned in a direction perpendicular to the active region.

In the embodiment of the application, the active region is a combination of a source region, a drain region and a channel region.

In an embodiment, the front side transistor and the back side transistor in the stacked transistor are disposed opposite to each other, and the active structures in the front side transistor and the back side transistor are formed by the same process. For example, after the first active structure of the first semiconductor structure is once formed, the front-side transistor in the first semiconductor structure may be fabricated based on the upper half of the first active structure and the back-side transistor in the first semiconductor structure may be fabricated based on the lower half of the first active structure. In this manner, the front side and back side transistors are fabricated based on a one-shot active structure, which may be such that the active regions of the front side and back side transistors in the first semiconductor structure are self-aligned.

In an embodiment of the present application, the first semiconductor structure, the second semiconductor structure, the third semiconductor structure and the fourth semiconductor structure in the semiconductor structure may be stacked transistors of the same type, and the types of stacked transistors may include, but are not limited to: fin field effect transistors, nano-plate field effect transistors, planar transistors, and vertical field effect transistors.

In the embodiment of the application, the first semiconductor structure, the second semiconductor structure, the third semiconductor structure and the fourth semiconductor structure are identical except for the gate cutting structure. That is, the manufacturing methods of the first, second, third, and fourth semiconductor structures are the same before the gate cutting process is performed.

Fig. 4 is a semiconductor structure formed by a fin field effect transistor, and a method for manufacturing the semiconductor structure according to an embodiment of the present application is described below with reference to the semiconductor structure shown in fig. 4.

FIG. 1 is a schematic flow chart of an embodiment of a method for manufacturing a semiconductor structure according to the present application, wherein the semiconductor structure may include a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure on the same wafer; wherein the first front gate structure and the first back gate structure of the first semiconductor structure are self-aligned, the second front gate structure and the second back gate structure of the second semiconductor structure are self-aligned, and the third front gate structure and the third back gate structure of the third semiconductor structure are self-aligned; referring to fig. 1, the method for preparing the semiconductor structure may include:

s101, performing gate cutting on the first front gate structure, the first back gate structure, the third front gate structure and the third back gate structure to form a first gate cutting groove of the first semiconductor structure and a second gate cutting groove of the third semiconductor structure, and performing gate cutting on the second back gate structure to form a third gate cutting groove of the second semiconductor structure.

It should be noted that, in the embodiment of the present application, the order between forming the first gate cutting groove and the second gate cutting groove and forming the third gate cutting groove is not limited; the first gate cutting groove and the second gate cutting groove may be formed first, and then the third gate cutting groove may be formed; the third gate cutting groove may be formed first, and then the first gate cutting groove and the second gate cutting groove may be formed. For convenience of explanation, the following describes a preparation method of the semiconductor structure in a preparation sequence of forming the first gate cutting groove and the second gate cutting groove and then forming the third gate cutting groove.

It can be appreciated that after the first front gate structure and the first back gate structure of the first semiconductor structure, the second front gate structure and the second back gate structure of the second semiconductor structure, and the third front gate structure and the third back gate structure of the third semiconductor structure are prepared, etching partial regions of the first front gate structure and the first back gate structure located at both sides of the first active structure of the first semiconductor structure to form a first gate cut groove; and etching the third front gate structure and the third back gate structure by adopting the same gate cutting process while forming the first gate cutting groove so as to form a second gate cutting groove. Removing the first photoresist layer after forming the first gate cutting groove and the second gate cutting groove, coating photoresist on the first back gate structure, the second back gate structure and the third back gate structure again, and performing photoresist exposure and development treatment; then, the gate cutting process is performed only on the second back gate structure in the second semiconductor structure, and the second front gate structure is not affected (i.e., the second front gate structure may not be subjected to the gate cutting process).

In some possible embodiments, before S101, the method for manufacturing a semiconductor structure according to the embodiment of the present application may further include: forming an active structure on a substrate; the active structures comprise a first active structure, a second active structure and a third active structure; forming a first semiconductor structure based on the first active structure; forming a second semiconductor structure based on the second active structure; a third semiconductor structure is formed based on the third active structure.

It will be appreciated that in the fabrication of semiconductor structures, a substrate is provided which may include, but is not limited to: silicon (Si) substrates, silicon-on-insulator (SOI) substrates, fully depleted silicon-on-insulator (FDSOI) substrates, stacked substrates formed by alternating deposition of silicon and silicon germanium (SiGe), and the like.

In some embodiments, the substrate in embodiments of the present application may be a multilayer structure. Specifically, a sacrificial layer (e.g., siGe) is epitaxially grown on the underlying silicon layer, and a top silicon layer is epitaxially grown over the sacrificial layer (see fig. 3A).

In the subsequent preparation process, the semiconductor structure is subjected to a rewinding process, the substrate is removed through a chemical-mechanical planarization (CMP) process, and the sacrificial layer can be used as a CMP stop layer.

In some embodiments, the sacrificial layer has a thickness of about 10-20 nm and the top silicon layer has a thickness of greater than 100nm. It should be noted that, the thicknesses of the sacrificial layer and the top silicon layer may be selected according to practical requirements, for example, in a fin field effect transistor, the top silicon layer has a larger thickness, so as to facilitate etching the fin structure.

In some embodiments, forming an active structure on a substrate may include: patterning of the active structure is performed by standard process steps and the substrate is etched to form the active structure.

The active structures may include a first active structure for preparing a first semiconductor structure, a second active structure for preparing a second semiconductor structure, and a third active structure for preparing a third semiconductor structure.

It will be appreciated that the first semiconductor structure is a self-aligned stacked transistor, the first front side transistor and the first back side transistor in the first semiconductor structure are disposed opposite one another, and then the upper half of the first active structure (i.e., the first portion of the first active structure) may be used with the active structure in the first front side transistor, and the lower half of the first active structure (i.e., the second portion of the first active structure) may be used with the active structure in the first back side transistor; similarly, the first and second portions of the second active structure are active structures in the second front side transistor and the second back side transistor, respectively, and the first and second portions of the third active structure are active structures in the third front side transistor and the third back side transistor, respectively.

In some embodiments, when the substrate is etched, the etching depth is the sum of the thicknesses of the top silicon layer and the sacrificial layer in the substrate, and the etching depth is immediately up to the connection position of the sacrificial layer and the bottom silicon layer.

For example, the etching of the substrate may employ anisotropic etching to form fin structures extending in the same direction in the active region (see (b) of fig. 3A).

It should be noted that, the etching process mentioned in the embodiment of the present application may include any of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal processes, to which embodiments of the present application are not limited.

In the embodiment of the present application, for convenience of description, the first front gate structure and the first back gate structure are collectively referred to as a first gate structure; similarly, the second gate structure represents a second front gate structure and a second back gate structure, the third gate structure represents a third front gate structure and a third back gate structure, and the fourth gate structure represents a fourth front gate structure and a fourth back gate structure.

In some possible embodiments, the gate cutting the first front gate structure, the first back gate structure, the third front gate structure, and the third back gate structure to form the first gate cutting groove of the first semiconductor structure and the second gate cutting groove of the third semiconductor structure may include: coating photoresist above the first back gate structure and the third back gate structure; developing the photoresist to form a first photoresist layer; the first photoresist layer covers a first region in the first back gate structure and a second region in the third back gate structure, the first region is located above the first active structure, and the second region is located above the third active structure; and etching the first back grid structure, the first front grid structure, the third back grid structure and the third front grid structure by taking the first photoresist layer as a mask to form a first grid cutting groove and a second grid cutting groove.

It is understood that the photoresist may be coated over the first back gate structure of the first semiconductor structure, the second back gate structure of the second semiconductor structure, and the third back gate structure of the third semiconductor structure prior to performing the first gate cut process. Forming a notch at a preset position after exposing and developing the photoresist (namely forming a first photoresist layer), wherein the notch corresponds to a gate cutting-off region of the first semiconductor structure (namely the first region) and a gate cutting-off region of the third semiconductor structure (namely the second region); and the photoresist above the second back gate structure has no notch and completely covers the second back gate structure. Next, a portion of the first gate structure and a portion of the third gate structure are etched (i.e., first photolithography) using the first photoresist layer as a mask to form a first gate cut groove and a second gate cut groove.

It should be noted that, the thicknesses of the first gate cutting groove and the second gate cutting groove (i.e. the size of the notch of the first photoresist layer) may be designed according to practical situations, which is not particularly limited in the embodiment of the present application.

In some possible embodiments, the gate cutting the second back gate structure to form the third gate cutting groove of the second semiconductor structure may include: coating photoresist on the second back gate structure; developing the photoresist to form a second photoresist layer; the second photoresist layer covers a third region in the second back gate structure, and the third region is positioned above the second active structure; and etching the second back gate structure by using the second photoresist layer as a mask to form a third gate cutting groove.

It will be appreciated that after the removal of the first photoresist layer, a photoresist is applied over the first back gate structure of the first semiconductor structure, the second back gate structure of the second semiconductor structure, and the third back gate structure of the third semiconductor structure; and, the first gate cut groove and the second gate cut groove are also filled with photoresist to protect the first gate structure and the third gate structure during a subsequent etching process. After the photoresist is developed (i.e., a second photoresist layer is formed), forming a notch at a preset position, wherein the notch corresponds to a gate cutting region (i.e., the third region) of the second semiconductor structure; and the photoresist above the first back gate structure and the third back gate structure has no notch. And then, using the second photoresist layer as a mask, etching a part of the second back gate structure, and stopping etching the gate isolation layer between the second front gate structure and the second back gate structure (namely, performing second photoetching) to form a third gate cutting groove.

And S102, filling insulating materials in the first grid cutting groove, the second grid cutting groove and the third grid cutting groove to form a first grid cutting structure of the first semiconductor structure, a second grid cutting structure of the third semiconductor structure and a third grid cutting structure of the second semiconductor structure.

It will be appreciated that after the second photoresist layer is removed, the first gate cut groove, the second gate cut groove, and the third gate cut groove are filled with an insulating material, and a first gate cut structure located on both sides of the first gate structure, a second gate cut structure located on both sides of the third gate structure, and a third gate cut structure located on both sides of the second back gate structure may be formed.

Wherein, the insulating material filling the first gate cutting groove, the second gate cutting groove and the third gate cutting groove may be silicon nitride (SiN).

And S103, photoetching a part of the second grid cutting structure corresponding to the third back grid structure to form a fourth grid cutting structure and a first groove, wherein the fourth grid cutting structure corresponds to the third front grid structure.

It is understood that the second gate cutting structure is located at two sides of the third back gate structure and the third front gate structure, and the portions of the second gate cutting structure located at two sides of the third back gate structure may be removed by photolithography to form the fourth gate cutting structure and the first groove, wherein the first groove is located at two sides of the third back gate structure, and the fourth gate cutting structure is located at two sides of the third front gate structure.

In some possible embodiments, the step S103 may include: coating photoresist above the third back gate structure; developing the photoresist to form a third photoresist layer; the third photoresist layer covers a fourth region of the third back gate structure, and the fourth region is positioned above the third active structure; and etching a part of the second gate cutting structure corresponding to the third back gate structure (namely third photoetching) by taking the third photoresist layer as a mask to form a fourth gate cutting structure and the first groove.

It is understood that photoresist is coated over the first back gate structure of the first semiconductor structure, the second back gate structure of the second semiconductor structure, and the third back gate structure of the third semiconductor structure; exposing and developing the photoresist, and forming a notch at a preset position of the photoresist after developing (namely forming a third photoresist layer), wherein the notch corresponds to a gate cutting area (namely the fourth area) of the third semiconductor structure; and the photoresist above the first back gate structure and the second back gate structure has no notch. And then, using the third photoresist layer as a mask, etching a part of the third back gate structure, and stopping etching the gate isolation layer between the third front gate structure and the third back gate structure to form a fourth gate cutting structure and the first groove.

And S104, filling a metal material in the first groove to form a gate interconnection metal, wherein the gate interconnection metal is used for metal interconnection of the third back gate structure.

It will be appreciated that after the third photoresist layer is removed, a metal material different from the third back gate structure is filled in the first recess to form a gate interconnect metal, where the gate interconnect metal is used for metal interconnection between the third back gate structure and other devices in the semiconductor structure, i.e. the third back transistor is in a conductive state, and accordingly, the third front transistor is in an isolated state due to the presence of the fourth gate cut structure.

In some possible embodiments, the wafer on which the semiconductor structure is located may further include a fourth semiconductor structure, where a fourth front gate structure and a fourth back gate structure of the fourth semiconductor structure are self-aligned, and the active structure may further include a fourth active structure, correspondingly; the method for manufacturing the semiconductor structure may further include: forming a fourth semiconductor structure based on the fourth active structure; the fourth front gate structure and the fourth back gate structure do not perform a gate cut process.

In some embodiments, when the fourth semiconductor structure is included in the semiconductor structure, the first photoresist layer covers a surface of the fourth back gate structure during the forming of the first photoresist layer, such that the first back gate structure does not undergo a gate cut process during the first photolithography; also, during the forming of the second photoresist layer and the third photoresist layer, the second photoresist layer and the third photoresist layer both cover the surface of the fourth back gate structure, so that the first back gate structure does not perform the gate cutting process during the second photolithography and the third photolithography. That is, after the three times of lithography are completed, neither the fourth back gate structure nor the fourth front gate structure is etched, and the conductive state with other devices in the semiconductor structure is maintained.

In some possible implementations, the first active structure includes a first portion of the first active structure and a second portion of the first active structure; the forming a first semiconductor structure based on the first active structure may include: sequentially forming a first front-side source-drain structure, a first front-side interlayer dielectric layer and a first front-side metal interconnection layer of a first semiconductor structure based on a first part of the first active structure; rewinding the first semiconductor structure and removing the substrate; forming a first back source drain structure, a first back interlayer dielectric layer and a first back metal interconnection layer of the first semiconductor structure in sequence based on a second part of the first active structure; wherein the first portion of the first active structure is remote from the substrate relative to the second portion of the first active structure.

It will be appreciated that taking the first semiconductor structure as the stacked transistor as an example, in the process of manufacturing the first semiconductor structure, the first front-side transistor in the first semiconductor structure is manufactured according to a standard process, and after the first front-side transistor is reworked, the first back-side transistor in the first semiconductor structure is manufactured according to a standard process.

In some embodiments, after forming the first active structure, depositing a semiconductor material, such as polysilicon (poly Si) and amorphous silicon, on the first active structure to form a dummy gate structure; forming a first front-side source drain structure, a first front-side interlayer dielectric layer and a first front-side metal interconnection layer based on the first active structure; rewinding the first semiconductor structure, and removing the bottom substrate and the sacrificial layer; removing the pseudo gate structure, exposing a gate region of the first semiconductor structure, filling a metal material in the gate region, and wrapping the first active structure in the gate region of the first semiconductor structure by the filled metal material; removing a portion of the metal material located in the gate region of the first back side transistor to form a first front side gate structure and exposing the gate region of the first back side transistor; depositing an insulating material over the first front side gate structure to form a gate isolation layer of the first semiconductor structure; depositing a metal material over the gate isolation layer to form a first back gate structure; after the gate cutting process is performed on the first semiconductor structure, a back-pass process is performed on the first back-side gate structure to form a first back-side metal interconnection layer.

It should be noted that, for convenience of description, the first front-side source-drain structure in the embodiment of the present application is a short for source and/or drain in the first front-side transistor; similarly, in the embodiments of the present application, other structures related to "source and drain" (e.g., a first back source and drain structure, a second front source and drain structure, etc.), where "source and drain" are abbreviated as "source and/or drain".

In the embodiment of the present application, the manufacturing processes for forming the second front gate structure and the second back gate structure, the third front gate structure and the third back gate structure, and the fourth front gate structure and the fourth back gate structure are the same as the manufacturing processes for forming the first front gate structure and the first back gate structure, which are not described in detail herein.

In some embodiments, isolation between active regions is achieved by performing an ion implantation process between the active structure of the first front side transistor in the first semiconductor structure and the active structure in the first back side transistor. Specifically, after the first active structure is formed, ion implantation may be performed at a junction between the first portion and the second portion of the first active structure to form an electrical isolation layer, where the electrical isolation layer is used to electrically isolate the upper half and the lower half of the active structure.

It should be noted that, the second active structure, the third active structure and the fourth active structure may be all isolated from each other by the above ion implantation treatment, which is not described in detail in the embodiment of the present application.

The ion implanted ions may include, but are not limited to, P-type ions, N-type ions, oxygen ions, and the like. The P-type ion may be one of: boron (B), gallium (Ga), aluminum (Al). The N-type ion may be one of: phosphorus (P), arsenic (As), antimony (Sb).

In some embodiments, taking the first semiconductor structure as an example, after forming the dummy gate structure, an area except for the gate area on the substrate may be further filled with an insulating material to form a shallow trench isolation structure (shallow trench isolation, STI).

In the embodiment of the present application, the insulating material forming the shallow trench isolation structure may be any one of the following: silicon nitride (SiN, si ₃N₄), silicon dioxide (SiO ₂), silicon oxycarbide (SiCO), or the like.

In some embodiments, taking the first semiconductor structure as an example, the height of the shallow trench isolation structure is greater than that of the first active structure, for convenience of subsequent processing, after the shallow trench isolation structure is formed, polishing or CMP may be further performed on the shallow trench isolation structure, so that when the shallow trench isolation structure is etched subsequently, the corresponding etching depths of the shallow trench isolation structures in different areas are the same, and thus the heights of the exposed first active structures are the same.

In some embodiments, taking the first semiconductor structure as an example, after performing the CMP process on the shallow trench isolation structure, the method may further include: removing the upper half part of the shallow trench isolation structure by etching to expose the first part of the first active structure covered by the shallow trench isolation structure, and then exposing the upper half part of the dummy gate structure; forming spacers (spacers) on two sides of the upper half of the dummy gate structure, and epitaxially growing a first front-side source-drain structure in the first front-side transistor by using the spacers as a mask; depositing an interlayer dielectric on the first active structure and between the dummy gate structures to form a first front interlayer dielectric layer; and then, completing metal contact of the first front-side source-drain structure in the first front-side transistor, and performing a subsequent process above the first front-side source-drain structure to form a first front-side metal interconnection layer of the first front-side transistor.

In an embodiment of the present application, the solvent used for etching the shallow trench isolation structure may include, but is not limited to: DHF solution or BOE solution.

In some embodiments, taking the first semiconductor structure as an example, after forming the first front side metal interconnection layer, the method may further include: depositing an insulating material (e.g., silicon oxide) on the first front side metal interconnect layer to form a first insulating layer and bonding the first insulating layer to the carrier wafer; next, the as yet unfinished first semiconductor structure is flipped so that the substrate (i.e., the underlying silicon layer) is placed up, and then the substrate and the lower half of the shallow trench isolation structure are etched to expose the second portion of the first active structure.

In some embodiments, taking the first semiconductor structure as an example, based on the second portion of the first active structure, a method for forming the first back source drain structure, the first back interlayer dielectric layer and the first back metal interconnection layer in the first back transistor is the same as the method for forming the first front source drain structure, the first front interlayer dielectric layer and the first front metal interconnection layer described above, which is not described herein.

In the embodiment of the present application, taking the first semiconductor structure as an example, the materials of the first front gate structure and the first back gate structure may be made of the same or different metal materials according to practical situations, which is not particularly limited in the embodiment of the present application. Wherein the metal material for preparing the first front gate structure and the first back gate structure may include, but is not limited to: the materials of the tantalum nitride (TaN), the titanium nitride (TiN), the aluminum nitride (AlN), the titanium aluminum carbide (TiAlC), the titanium aluminum nitride (TiAlN), the first front-side gate structure and the first back-side gate structure may be selected according to actual situations, and are not limited to the above-listed metal materials.

In the embodiment of the present application, when the semiconductor structure includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a fourth semiconductor structure, the first front side transistor and the first back side transistor, the second front side transistor and the second back side transistor, the third front side transistor and the third back side transistor, and the fourth front side transistor and the fourth back side transistor may be the same type of transistor, such as any of the following: fin field effect transistors, fully surrounding gate transistors and planar transistors, etc.

In the embodiment of the application, the first semiconductor structure, the second semiconductor structure, the third semiconductor structure and the fourth semiconductor structure are identical except for the gate cutting structure. The first semiconductor structure in the semiconductor structure provided by the embodiment of the application is described below by taking the first front-side transistor and the first back-side transistor in the first semiconductor structure as fin field effect transistors as examples. Fig. 2 is a schematic structural diagram of a first semiconductor structure according to an embodiment of the present application. In fig. 2, (a) is a design layout of the first semiconductor structure, and for convenience of understanding, only fin structures, gate structures and source-drain structures are shown in the design layout; (b) A cut-away view of the first semiconductor structure taken along a cut-away direction (i.e., A-A') of the gate structure; (c) A cut-out view of the first semiconductor structure along the cut-out direction (i.e., the B-B' direction) of the source-drain structure; (d) A cut-out of the first semiconductor structure is made along the cut-out direction (i.e., the C-C' direction) of the fin structure.

Referring to fig. 2, the first semiconductor structure 11 includes a first front side transistor 111 and a first back side transistor 112, and the first active structure in the first semiconductor structure 11 is a plurality of fin structures 22. The fin structure 22 is divided into upper and lower portions, respectively designated as a first fin structure 1111 and a second fin structure 1121, the first fin structure 1111 functioning as an active structure in the first front side transistor 111, and the second fin structure 1121 functioning as an active structure in the first back side transistor 112.

The process of fabricating the first semiconductor structure 11 shown in fig. 2 will be described below in conjunction with the above-described method of fabricating the semiconductor structure. The first semiconductor structure 11 shown in fig. 2 may be prepared by the process shown in fig. 3A to 3E, and fig. 3A to 3E are schematic views illustrating a preparation process of the first semiconductor structure according to an embodiment of the present application.

It should be noted that fig. 3A to 3E only show the preparation process of the first semiconductor structure 11 before the gate cutting process is performed.

In an example, taking the first front side transistor 111 and the first back side transistor 112 in the first semiconductor structure 11 as fin field effect transistors as an example, one manufacturing process of the first semiconductor structure 11 may include the following steps:

The first step: a Si substrate 21 is provided. Wherein the Si substrate 21 is composed of a bottom Si layer 211, a sacrificial layer 212, and a top Si layer 213 (see (a) in fig. 3A). The sacrificial layer is made of SiGe.

And a second step of: the Si substrate 21 is etched to form a plurality of fin structures (see (b) in fig. 3A).

The Si substrate 21 is anisotropically etched to form a plurality of fin structures 22 extending in the same direction, and the fin structures 22 are divided into an upper portion and a lower portion, which are respectively a first fin structure 1111 and a second fin structure 1121. The fin structure has a height greater than 100nm. The sacrificial layer 212 has a height of 10-20nm. The etch depth is the sum of the heights of top Si layer 213 and sacrificial layer 212.

And a third step of: the gate region in the first semiconductor structure 11 is opened by a photolithography process, and polysilicon (poly Si) is deposited in the gate region as a dummy gate structure 23 (see A-A' direction of (c) in fig. 3A). Next, STI is filled in the other region than the gate region, a shallow trench isolation structure 24 is formed (see B-B' direction in (c) of fig. 3A), and a planarization process is performed by CMP.

Wherein the heights of the dummy gate structures 23 and the shallow trench isolation structures 24 are both greater than the thickness of the fin structures. Referring to the C-C' direction in fig. 3A, dummy gate structures 23 and shallow trench isolation structures 24 are alternately deposited around the fin structures.

Fourth step: the dummy gate structure 23 is removed by etching, exposing the fin structure 22 and the sacrificial layer 212 located in the gate region (see (a) in fig. 3B).

Fifth step: the exposed sacrificial layer 212 is selectively removed using wet etching (see (B) in fig. 3B).

Sixth step: poly Si is again deposited in the gate region to reform the dummy gate structure 23 (see (c) in fig. 3B).

Note that the bottom of the fin structure surrounded by the dummy gate structure 23 formed in the second time is not provided with the sacrificial layer 212.

Seventh step: the upper half of the shallow trench isolation structure 24 is removed by etching, exposing the upper half of the fin structure (i.e., the first fin structure 1111); next, forming a first front spacer 1116 on the exposed sidewall of the dummy gate structure 23, and epitaxially growing a first front source drain structure 1112 in the first front transistor 111 on the first fin structure 1111 using the first front spacer 1116 as a mask; and an oxide is deposited over the first front-side source drain structure 1112 and between the dummy gate structures 23 to form a first front-side interlayer dielectric layer 1113 (see (a) in fig. 3C).

Meanwhile, ion implantation is performed at the connection of the exposed plurality of first fin structures 1111 and the unexposed second fin structures 1121 to form an electrical isolation layer (not shown) for isolating the first fin structures 1111 and the second fin structures 1121.

Eighth step: depositing a metal material over the first front-side source-drain structures 1112 of the first front-side transistor 111 to form a first front-side source-drain metal 1114; next, a subsequent process is performed over the first front-side source drain metal 1114 and the first front-side interlayer dielectric layer 1113 to form a first front-side metal interconnect layer 1115 in the first front-side transistor 111 (see (b) in fig. 3C).

Ninth step: an insulating material is deposited over the first front side metal interconnect layer 1115 to form an insulating layer 113, the first insulating layer 113 is bonded to a carrier wafer 114, and then the now-fabricated wafer is reworked (see (C) in fig. 3C).

In the embodiment of the present application, the bonded carrier wafer 114 may provide physical support for the flipped wafer after rewinding, so as to effectively prevent the wafer from being broken during the process of preparing the first back side transistor 112.

Tenth step: thinning the wafer subjected to film pouring by adopting a CMP (chemical mechanical polishing) process to remove the bottom Si layer 211 until the sacrificial layer 212 wrapped by the shallow trench isolation structure 24 is exposed; next, the exposed sacrificial layer 212 is selectively removed by wet etching (see (a) in fig. 3D).

Eleventh step: the lower half of the shallow trench isolation structure 24 is etched until the lower half of the fin structure 22 (i.e., the second fin structure 1121) is exposed, and the first back spacer 1126, the first back source drain structure 1122, and the first back interlayer dielectric layer 1123 in the first back side transistor 112 are prepared based on the second fin structure 1121 (see (c) in fig. 3D).

In the process of etching the shallow trench isolation structure 24, the shallow trench isolation structure 24 with a certain thickness is reserved as a shallow trench isolation layer 241, and the shallow trench isolation layer 241 is used for isolating the first front-side transistor 111 and the first back-side transistor 112. The thickness of the shallow trench isolation layer 241 may be selected according to practical situations, and the embodiment of the present application is not limited thereto.

Twelfth step: removing the dummy gate structure 23 by etching, and forming a gate dielectric layer 115 on the surface of the fin structure; a metal material is then deposited in the gate region to form a gate structure 25 (see (c) in fig. 3D).

Thirteenth step: the upper half of the gate structure 25 is etched to expose the second fin structure 1121, and the gate structure 25 that is not etched is the first front side gate structure 1117 in the first front side transistor 111 (see (a) in fig. 3E).

Fourteenth step: a layer of insulating material is deposited over the first front side gate structure 1117 to form a gate spacer 116 (see (b) in fig. 3E).

Fifteenth step: a metal material is deposited over the gate spacer 116 (i.e., the gate region of the first back side transistor) to form a first back side gate structure 1127 (see (c) in fig. 3E).

Thus, the first semiconductor structure 11 is prepared after the gate cutting process is completed.

In the embodiment of the application, in the process of integrating the first semiconductor structure, the second semiconductor structure, the third semiconductor structure and the fourth semiconductor structure in the semiconductor structure, the first front side transistor and the first back side transistor in the first semiconductor structure are subjected to a gate cutting process, the second back side transistor in the second semiconductor structure is subjected to a gate cutting process, the third front side transistor in the third semiconductor structure is subjected to a gate cutting process, and the fourth semiconductor structure is not subjected to a gate cutting process. That is, the first gate structure of the first semiconductor structure, the second gate structure of the second semiconductor structure, the third gate structure of the third semiconductor structure, and the fourth gate structure of the fourth semiconductor structure are all designed differently, and four different types of gate structures may be included in the semiconductor structures.

It should be noted that, the positions of the first semiconductor structure, the second semiconductor structure, the third semiconductor structure and the fourth semiconductor structure in the design layout of the semiconductor structure may be arranged side by side, or may be distributed in different positions in the design layout of the semiconductor structure. Therefore, in the following embodiments, the relative positions among the first semiconductor structure, the second semiconductor structure, the third semiconductor structure, and the fourth semiconductor structure are not specifically limited, and only the semiconductor structures integrating the four stacked transistors (i.e., the first semiconductor structure, the second semiconductor structure, the third semiconductor structure, and the fourth semiconductor structure) are described with the sectional views of the first semiconductor structure, the second semiconductor structure, the third semiconductor structure, and the fourth semiconductor structure in the sectional directions of the gate structure, respectively.

In some embodiments, in the process of preparing the first semiconductor structure before the gate cutting process, the second semiconductor structure, the third semiconductor structure and the fourth semiconductor structure before the gate cutting process are prepared simultaneously according to the preparation method of the first semiconductor structure. The following describes a semiconductor structure provided by the embodiment of the present application by taking a fin field effect transistor as an example of stacked transistors in the semiconductor structure. Fig. 4 is a cross-sectional view of a semiconductor structure along a cross-sectional direction (i.e., A-A' direction) of a gate structure in an embodiment of the present application. Wherein (a) in fig. 4 is a cross-sectional view of the first semiconductor structure in the A-A' direction; fig. 4 (b) is a cross-sectional view of the second semiconductor structure in the A-A' direction; fig. 4 (c) is a cross-sectional view of the third semiconductor structure in the A-A' direction; fig. 4 (d) is a cross-sectional view of the fourth semiconductor structure in the A-A' direction.

Referring to fig. 4, a first semiconductor structure 11, a second semiconductor structure 12, a third semiconductor structure 13, and a fourth semiconductor structure 14 are included in a semiconductor structure 10. Wherein the first front side gate structure 1117 of the first front side transistor 111 in the first semiconductor structure 11 and the first back side gate structure 1127 in the first back side transistor 112 are both cut off; the second back gate structure 1227 in the second back transistor in the second semiconductor structure 12 is cut off; third front side gate structure 1317 in the third front side transistor in third semiconductor structure 13 is cut off; neither the fourth front side gate structure 1417 of the fourth front side transistor in the fourth semiconductor structure 14 nor the fourth back side gate structure 1427 of the fourth back side transistor is gate-off processed.

The process of fabricating the semiconductor structure 10 shown in fig. 4 will be described below in conjunction with the above fabrication method. Fig. 5 is a layout diagram of a semiconductor structure according to an embodiment of the present application, where (a) in fig. 5 is a layout diagram of a first semiconductor structure during gate cutting, (b) in fig. 5 is a layout diagram of a second semiconductor structure during gate cutting, (c) in fig. 5 is a layout diagram of a third semiconductor structure during gate cutting, and (d) in fig. 5 is a layout diagram of a fourth semiconductor structure during gate cutting. Fig. 6A to 6K are schematic views illustrating a process for manufacturing a semiconductor structure according to an embodiment of the present application. The semiconductor structure 10 shown in fig. 4 may be prepared by the process shown in fig. 6A to 6K according to the design layout shown in fig. 5.

Note that fig. 6A to 6K only show the manufacturing process of the semiconductor structure 10 after the gate cutting process is performed.

In an example, where the stacked transistors in semiconductor structure 10 are fin field effect transistors, a process for fabricating semiconductor structure 10 may include the steps of:

the first step: according to one of the above-described fabrication processes of the first semiconductor structure shown in fig. 3A to 3E, the first semiconductor structure 11, the second semiconductor structure 12, the third semiconductor structure 13 and the fourth semiconductor structure 14.

As shown in fig. 6A, the first front gate structure 1117, the first back gate structure 1127, the second front gate structure 1217, the second back gate structure 1227, the third front gate structure 1317, the third back gate structure 1327, the fourth front gate structure 1417, and the fourth back gate structure 1427 are not subjected to a gate cutting process.

And a second step of: photoresist is coated over the first back gate structure 1127 of the first semiconductor structure 11, the second back gate structure 1227 of the second semiconductor structure 12, the third back gate structure 1327 of the third semiconductor structure 13, and the fourth back gate structure 1427 of the fourth semiconductor structure 14 (see fig. 6A).

And a third step of: exposing and developing the photoresist coated in the second step to form a first photoresist layer 31; after the development process, the first photoresist layer 31 is formed into a photolithography pattern (see fig. 6B).

Therein, referring to fig. 6B, the first photoresist layer 31 covers a portion of the first back gate structure 1127 (i.e., a portion of the first back gate structure 1127 that is located above the first active structure), the first photoresist layer 31 completely covers the second back gate structure 1227, the first photoresist layer 31 covers a portion of the third back gate structure 1327 (i.e., a portion of the third back gate structure 1327 that is located above the third active structure), and the first photoresist layer 31 completely covers the fourth back gate structure 1427.

Fourth step: etching the first front gate structure 1117 and the first back gate structure 1127, the third front gate structure 1317, and the third back gate structure 1327 under the mask of the first photoresist layer 31 to form a first gate cut groove of the first semiconductor structure 10 and a second gate cut groove of the third semiconductor structure 13; the first photoresist layer 31 is then removed (see fig. 6C).

Fifth step: photoresist is coated over the first back gate structure 1127 of the first semiconductor structure 11, the second back gate structure 1227 of the second semiconductor structure 12, the third back gate structure 1327 of the third semiconductor structure 13, and the fourth back gate structure 1427 of the fourth semiconductor structure 14, and in the first gate cut groove and the second gate cut groove (see fig. 6D).

Sixth step: exposing and developing the photoresist coated in the fifth step to form a second photoresist layer 32; the second photoresist layer 32 is subjected to a development process to form a photolithography pattern (see fig. 6E).

Wherein, referring to fig. 6E, the second photoresist layer 32 completely covers the first back gate structure 1127, the second photoresist layer 32 covers a portion of the second back gate structure 1227 (i.e., a portion of the second back gate structure 1227 that is located above the second active structure), the second photoresist layer 32 completely covers the third back gate structure 1327, and the second photoresist layer 32 completely covers the fourth back gate structure 1427.

Seventh step: the second back gate structure 1227 in the second semiconductor structure 12 is etched under the mask of the second photoresist layer 32, the etching is stopped to the upper surface of the gate isolation layer 116 to form a third gate cut groove, and then the second photoresist layer 32 is removed (see fig. 6F).

Eighth step: siN material is deposited in the first, second, and third gate cut grooves to form a first gate cut structure 41 corresponding to the first gate cut groove, a second gate cut structure 42 corresponding to the second gate cut groove, and a third gate cut structure 43 corresponding to the third gate cut groove (see fig. 6G).

Ninth step: photoresist is coated over the first back gate structure 1127 of the first semiconductor structure 11, the second back gate structure 1227 of the second semiconductor structure 12, the third back gate structure 1327 of the third semiconductor structure 13, and the fourth back gate structure 1427 of the fourth semiconductor structure 14 (see fig. 6H).

Tenth step: exposing and developing the photoresist coated in the ninth step to form a third photoresist layer 33; after the development process, the third photoresist layer 33 is formed into a photolithography pattern (see fig. 6I).

Wherein, referring to fig. 6I, the third photoresist layer 33 completely covers the first back gate structure 1127, the third photoresist layer 33 completely covers the second back gate structure 1227, the third photoresist layer 33 covers a portion of the third back gate structure 1327 (i.e., a portion of the third back gate structure 1327 that is located above the third active structure), and the third photoresist layer 33 completely covers the fourth back gate structure 1427.

Eleventh step: the upper half of the second gate cut structure 42 (i.e., the portion corresponding to the third back gate structure 1327) is etched under the mask of the third photoresist layer 33 to form the first recess and the fourth gate cut structure 44, and then the third photoresist layer 33 is removed (see fig. 6J).

The fourth gate cut structure is a lower half of the second gate cut structure that is not etched, and corresponds to the third front gate structure 1317.

Twelfth step: a metal material is filled in the first recess to form a gate interconnect metal 45 (see fig. 6K).

Thirteenth step: first, second, third and fourth back source drain metals 1124, second, third and fourth back source drain metals in the first, second, third and fourth semiconductor structures 11,12,13 and 14, respectively, and first, second, third and fourth back metal interconnect layers 1125, 1125 (see fig. 4) are prepared.

Thus, a semiconductor structure 10 is prepared that includes four different gate turn-off processes.

In some embodiments, in the case that the semiconductor structure includes only the first semiconductor structure, the gate cut structure (i.e., the first gate cut structure) corresponding to the first semiconductor structure may be formed by performing photolithography only once; that is, after the first gate cutting groove is formed by the first photolithography, siN is filled in the first gate cutting groove to form the first gate cutting structure.

In other embodiments, in the case that the semiconductor structure includes only the second semiconductor structure, the gate cut structure (i.e., the third gate cut structure) corresponding to the second semiconductor structure may be formed by performing photolithography only once; that is, after the first photolithography forms the third gate cutting groove, siN is filled in the third gate cutting groove to form the third gate cutting structure.

In still other embodiments, in the case that the semiconductor structure includes only the third semiconductor structure, the gate cut structure (i.e., the fourth gate cut structure) corresponding to the third semiconductor structure may be formed by performing photolithography twice; that is, after the first photolithography forms the second gate cut groove, siN is filled in the second gate cut groove to form the second gate cut structure, and then, a portion of the second gate cut structure located in the third back side transistor is subjected to the second photolithography, and a portion of the second gate cut structure which is not etched serves as the fourth gate cut structure.

In the embodiment of the application, three different forms of grid cutting structures can be realized by cutting the grid of the first front grid structure, the first back grid structure, the third front grid structure and the third back grid structure, cutting the grid of the second back grid structure and photoetching the part of the second grid cutting structure corresponding to the third back grid structure, so that wiring interconnection in the semiconductor structure is more flexible.

Further, the three different types of gate cutting structures can cover all the situations that stacked transistors are electrically interconnected with adjacent areas, and the process is simple and mature, so that the method can be popularized to gate cutting process designs of other stacked transistors.

Further, the semiconductor structure provided by the embodiment of the application can be detected by using a detection and analysis instrument, for example: scanning electron microscope (scanning electron microscope, SEM), transmission electron microscope (transmission electron microscope, TEM), scanning transmission electron microscope (scanning transmission electron microscopy, STEM), and the like. Taking TEM as an example, the semiconductor structure provided in the embodiment of the present application may adopt a TEM slicing manner to detect the above three different types of gate cut structures.

An embodiment of the present application provides a semiconductor device including: such as the semiconductor structures of the above embodiments. The specific limitation of the semiconductor structure may be referred to the semiconductor structure shown in fig. 4, and will not be described herein.

An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device comprises the semiconductor structure. The specific limitation of the semiconductor structure may be referred to the semiconductor structure shown in fig. 4, and will not be described herein.

In the description of the present application, a description of the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. The preparation method of the semiconductor structure is characterized in that the semiconductor structure comprises a first semiconductor structure, a second semiconductor structure and a third semiconductor structure which are positioned on the same wafer, wherein a first front grid structure and a first back grid structure of the first semiconductor structure are self-aligned, a second front grid structure and a second back grid structure of the second semiconductor structure are self-aligned, and a third front grid structure and a third back grid structure of the third semiconductor structure are self-aligned;

The method comprises the following steps:

Gate cutting is performed on the first front gate structure, the first back gate structure, the third front gate structure and the third back gate structure to form a first gate cutting groove of a first semiconductor structure and a second gate cutting groove of a third semiconductor structure, and gate cutting is performed on the second back gate structure to form a third gate cutting groove of a second semiconductor structure;

Filling insulating materials in the first gate cutting groove, the second gate cutting groove and the third gate cutting groove to form a first gate cutting structure of a first semiconductor structure, a second gate cutting structure of a third semiconductor structure and a third gate cutting structure of the second semiconductor structure;

Photoetching a part of the second grid cutting structure corresponding to the third back grid structure to form a fourth grid cutting structure and a first groove, wherein the fourth grid cutting structure corresponds to the third front grid structure;

And filling a metal material in the first groove to form a gate interconnection metal, wherein the gate interconnection metal is used for metal interconnection of the third back gate structure.

2. The method according to claim 1, wherein the method further comprises:

Forming an active structure on a substrate; the active structures comprise a first active structure, a second active structure and a third active structure;

Forming the first semiconductor structure based on the first active structure;

Forming the second semiconductor structure based on the second active structure;

the third semiconductor structure is formed based on the third active structure.

3. The method of claim 2, wherein gate cutting the first front side gate structure, the first back side gate structure, the third front side gate structure, and the third back side gate structure to form a first gate cut recess of a first semiconductor structure and a second gate cut recess of a third semiconductor structure comprises:

coating photoresist above the first back gate structure and the third back gate structure;

Developing the photoresist to form a first photoresist layer; the first photoresist layer covers a first region in the first back gate structure and a second region in the third back gate structure, the first region is located above the first active structure, and the second region is located above the third active structure;

And etching the first back grid structure, the first front grid structure, the third back grid structure and the third front grid structure by taking the first photoresist layer as a mask to form the first grid cutting groove and the second grid cutting groove.

4. The method of claim 2, wherein gate cutting the second back gate structure to form a third gate cut recess of a second semiconductor structure comprises:

Coating photoresist above the second back gate structure;

Developing the photoresist to form a second photoresist layer; the second photoresist layer covers a third region in the second back gate structure, and the third region is located above the second active structure;

and etching the second back gate structure by taking the second photoresist layer as a mask to form the third gate cutting groove.

5. The method of claim 2, wherein the lithographically exposing a portion of the second gate cut structure corresponding to the third back gate structure to form a fourth gate cut structure and a first recess, comprising:

coating photoresist above the third back gate structure;

Developing the photoresist to form a third photoresist layer; the third photoresist layer covers a fourth region of the third back gate structure, and the fourth region is located above the third active structure;

And etching a part of the second grid cutting structure corresponding to the third back grid structure by taking the third photoresist layer as a mask so as to form the fourth grid cutting structure and the first groove.

6. The method of claim 2, wherein the first active structure comprises a first portion of the first active structure and a second portion of the first active structure;

the forming the first semiconductor structure based on the first active structure includes:

sequentially forming a first front-side source drain structure, a first front-side interlayer dielectric layer and a first front-side metal interconnection layer of the first semiconductor structure based on a first part of the first active structure;

Rewinding the first semiconductor structure and removing the substrate;

forming a first back source drain structure, a first back interlayer dielectric layer and a first back metal interconnection layer of the first semiconductor structure in sequence based on the second part of the first active structure;

Wherein a first portion of the first active structure is remote from the substrate relative to a second portion of the first active structure.

7. The method of claim 2, further comprising a fourth semiconductor structure on the wafer, the fourth front side gate structure and the fourth back side gate structure of the fourth semiconductor structure being self-aligned, the active structure further comprising a fourth active structure;

the method further comprises the steps of:

Forming the fourth semiconductor structure based on the fourth active structure; the fourth front gate structure and the fourth back gate structure do not perform a gate cut process.

8. A semiconductor structure, the semiconductor structure comprising at least two of:

A first semiconductor structure; the first front gate structure and the first back gate structure of the first semiconductor structure are self-aligned, and the first semiconductor structure comprises a gate cutting structure formed by performing gate cutting treatment on the first front gate structure and the first back gate structure;

a second semiconductor structure; the second front gate structure and the second back gate structure of the second semiconductor structure are self-aligned, and the second semiconductor structure comprises a gate cutting structure formed by performing gate cutting treatment on the second back gate structure;

A third semiconductor structure; the third front-side grid electrode structure and the third back-side grid electrode structure of the third semiconductor structure are self-aligned, and the third semiconductor structure comprises a grid electrode cutting structure formed by conducting grid electrode cutting processing on the third front-side grid electrode.

9. The semiconductor structure of claim 8, wherein the semiconductor structure further comprises:

A fourth semiconductor structure; the fourth front-side grid structure and the fourth back-side grid structure of the fourth semiconductor structure are self-aligned, and the fourth semiconductor structure does not comprise a grid cutting structure formed by conducting grid cutting treatment on the fourth front-side grid and the fourth back-side grid structure.

10. A semiconductor device, comprising: the semiconductor structure of claim 8.

11. An electronic device, comprising: a circuit board and the semiconductor device according to claim 10, wherein the semiconductor device is provided on the circuit board.