CN117855145A - Source-drain interconnection method of self-aligned transistor, self-aligned transistor and device - Google Patents

Source-drain interconnection method of self-aligned transistor, self-aligned transistor and device Download PDF

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Publication number
CN117855145A
CN117855145A CN202311694549.0A CN202311694549A CN117855145A CN 117855145 A CN117855145 A CN 117855145A CN 202311694549 A CN202311694549 A CN 202311694549A CN 117855145 A CN117855145 A CN 117855145A
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source
transistor
dielectric layer
interlayer dielectric
drain
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吴恒
王润声
黎明
卢浩然
孙嘉诚
黄如
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Peking University
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Peking University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application provides a source-drain interconnection method of a self-aligned transistor, the self-aligned transistor and a device, wherein the method comprises the following steps: forming an active structure on a semiconductor substrate, wherein the active structure comprises a first active structure and a second active structure; forming a first source-drain structure, a first interlayer dielectric layer and first source-drain metal in sequence based on the first active structure, wherein the first interlayer dielectric layer wraps the first active structure, the first source-drain structure and the first source-drain metal; rewinding and removing the semiconductor substrate; forming a second source-drain structure, a second interlayer dielectric layer and second source-drain metal in sequence based on the second active structure, wherein the second active structure, the second source-drain structure and the second source-drain metal are wrapped by the second interlayer dielectric layer; the first source drain metal and the second source drain metal are communicated through an interconnection through hole structure, and the interconnection through hole structure penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer. By the method and the device, the difficulty in controlling etching time in a source-drain interconnection scheme can be reduced.

Description

Source-drain interconnection method of self-aligned transistor, self-aligned transistor and device
Technical Field
The present disclosure relates to the field of semiconductors, and in particular, to a source-drain interconnection method for a self-aligned transistor, and a device.
Background
While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors further increase transistor integration density by integrating two or more layers of transistors in vertical space is one of the important technologies continuing the scaling of integrated circuits.
When the stacked transistor (stacked transistor) is prepared using a conventional sequential scheme, the following technical difficulties exist: when the problem of source-drain interconnection of the upper transistor and the lower transistor is solved, the etching time needs to be precisely controlled to ensure the depth of the source-drain contact metal of the lower transistor.
Disclosure of Invention
The application provides a source-drain interconnection method of a self-aligned transistor, the self-aligned transistor and a device, so as to reduce the difficulty in controlling etching time in a source-drain interconnection scheme.
In a first aspect, an embodiment of the present application provides a method for source-drain interconnection of a self-aligned transistor, where the method includes: forming an active structure on a semiconductor substrate, wherein the active structure comprises a first active structure and a second active structure; forming a first source-drain structure, a first interlayer dielectric layer and first source-drain metal in sequence based on the first active structure, wherein the first interlayer dielectric layer wraps the first active structure, the first source-drain structure and the first source-drain metal; rewinding and removing the semiconductor substrate; forming a second source-drain structure, a second interlayer dielectric layer and second source-drain metal in sequence based on the second active structure, wherein the second active structure, the second source-drain structure and the second source-drain metal are wrapped by the second interlayer dielectric layer; the first source drain metal and the second source drain metal are communicated through an interconnection through hole structure, and the interconnection through hole structure penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer.
In some possible embodiments, based on the first active structure, sequentially forming a first source-drain structure, a first interlayer dielectric layer, and a first source-drain metal, including: etching a part of the first active structure to form a first source drain structure; depositing a semiconductor material on the first active structure and the first source drain structure to form a first interlayer dielectric layer; etching a first part of the first interlayer dielectric layer to form first source drain metal; and etching a second part of the first interlayer dielectric layer to form a first interconnection through hole structure, wherein the first interconnection through hole structure is connected with the first source drain metal.
In some possible embodiments, based on the second active structure, sequentially forming a second source-drain structure, a second interlayer dielectric layer, and a second source-drain metal, including: etching a part of the second active structure to form a second source drain structure; depositing a semiconductor material on the second active structure and the second source drain structure to form a second interlayer dielectric layer; etching the first part of the second interlayer dielectric layer to form second source drain metal; and etching a second part of the second interlayer dielectric layer until the second part is communicated with the first interconnection through hole structure to form a second interconnection through hole structure, wherein the second interconnection through hole structure and the first interconnection through hole structure form an interconnection through hole structure.
In some possible embodiments, based on the first active structure, sequentially forming a first source-drain structure, a first interlayer dielectric layer, and a first source-drain metal, including: etching a part of the first active structure to form a first source drain structure; depositing a semiconductor material on the first active structure and the first source drain structure to form a first interlayer dielectric layer; and etching the third part of the first interlayer dielectric layer to form a first source drain metal.
In some possible embodiments, based on the second active structure, sequentially forming a second source-drain structure, a second interlayer dielectric layer, and a second source-drain metal, including: etching a part of the second active structure to form a second source drain structure; depositing a semiconductor material on the second active structure and the second source drain structure to form a second interlayer dielectric layer; etching a third part of the second interlayer dielectric layer to form second source drain metal; and etching the fourth part of the second interlayer dielectric layer until penetrating the first interlayer dielectric layer to form an interconnection through hole structure.
In some possible implementations, the interconnect via structure is located on one side of the active structure; or, the interconnection through hole structure is positioned at two sides of the active structure; or, the interconnect via structure is located in the middle of the active structure.
In some possible embodiments, before rewinding and removing the semiconductor substrate, the method further includes: forming a first transistor based on the first interlayer dielectric layer; the first transistor is bonded to a carrier wafer.
In some possible embodiments, after forming the second source-drain structure, the second interlayer dielectric layer, and the second source-drain contact structure in sequence based on the second active structure, the method further includes: and forming a second transistor based on the second interlayer dielectric layer, wherein the second transistor and the first transistor are self-aligned in the vertical direction of the semiconductor substrate.
In a second aspect, embodiments of the present application provide a self-aligned transistor, including: a first transistor; a second transistor disposed opposite to the first transistor; the first source-drain metal of the first transistor is communicated with the second source-drain metal of the second transistor through an interconnection through hole structure, and the interconnection through hole structure penetrates through the first interlayer dielectric layer of the first transistor and the second interlayer dielectric layer of the second transistor.
In a third aspect, embodiments of the present application provide a semiconductor device, including: a self-aligned transistor as in the above embodiments.
In a fourth aspect, embodiments of the present application provide an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board.
In the application, the interconnection through hole structure in the self-aligned transistor is respectively connected with the first source drain metal and the second source drain metal, so that interconnection between the first source drain structure and the second source drain structure can be realized;
furthermore, the interconnection through hole structure penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer, so that etching can be automatically stopped at the source and drain metal by means of selective etching, and the difficulty in controlling etching time in a source and drain interconnection scheme is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic flow chart of a first implementation of a source-drain interconnection method of a self-aligned transistor in an embodiment of the present application;
fig. 2 is a schematic diagram of a first structure of a self-aligned transistor according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a first structure of an interconnect via structure in an embodiment of the present application;
FIGS. 4A-4E are schematic diagrams illustrating a first process for fabricating a self-aligned transistor according to embodiments of the present application;
fig. 5 is a schematic diagram of a second structure of a self-aligned transistor according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a second configuration of an interconnect via structure in an embodiment of the present application;
fig. 7 is a schematic diagram of a third structure of a self-aligned transistor according to an embodiment of the present application;
fig. 8 is a schematic diagram of a fourth structure of a self-aligned transistor according to an embodiment of the present application;
fig. 9 is a schematic diagram of a fifth structure of a self-aligned transistor according to an embodiment of the present application;
fig. 10 is a schematic diagram of a sixth structure of a self-aligned transistor according to an embodiment of the present application;
the figures above:
10. a self-aligned transistor; 11. a first transistor; 111. a first active structure; 112. a first source drain structure; 113. a first source drain metal; 114. a first interlayer dielectric layer; 115. a first gate structure; 116. a first spacer; 117. a first metal interconnect layer; 12. a second transistor; 121. a second active structure; 122. a second source drain structure; 123. a second source drain metal; 124. a second interlayer dielectric layer; 125. a second gate structure; 126. a second spacer; 127. a second metal interconnect layer; 13. an interconnect via structure; 131. a first interconnect via structure; 132. a second interconnect via structure; 14. shallow groove isolation layer; 15. a first insulating layer; 16. a carrier wafer; 21. a semiconductor substrate; 22. a fin structure; 23. shallow trench isolation structure; 241. a first dummy gate structure; 242. and a second dummy gate structure.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application.
While moore's law is continually deepening, continuing to advance transistor scaling after the technology node of the full-round gate transistor (GAA) is a hot spot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits.
In one embodiment, the fabrication process of the stacked transistor (stacked transistors) has two schemes, a single-chip scheme and a sequential scheme.
In the first approach, N-channel field effect transistors (N field effect transistors, NFET) and P-channel field effect transistors (P field effect transistors, PFET) are fabricated on the same substrate, and wafer bonding techniques are not employed. This determines that the same layer transistors must be of the same type, i.e., NFET or PFET. And the transistors on the upper layer and the lower layer are strictly in the same plane space, and no alignment deviation exists. The advantage of this solution is a better integration density. Drawbacks of this approach include the following two points: (1) The process is complex, and a large number of process technologies need to be developed and optimized; (2) Each layer of transistors has a fixed polarity, and two layers of transistors must be relied upon to form a basic Complementary Metal Oxide Semiconductor (CMOS) circuit, which has poor design flexibility.
The second scheme is based on wafer bonding and layer-by-layer processing. Specifically, the two transistors are stacked vertically by bonding a wafer on top of the fabricated lower transistor to prepare the upper transistor. However, this approach requires tight temperature control during the thermal process of processing the upper layer transistors, avoiding affecting the lower layer transistors and the interconnect lines. The scheme has the advantages that the device structure, the channel crystal orientation and even the channel material adopted by the upper layer transistor and the lower layer transistor can be correspondingly optimized to obtain better and more matched device performance due to wafer bonding. This solution currently presents the following technical challenges: (1) preparation of a high-quality upper transistor active layer; (2) thinning and defect control of the upper bonded wafer; (3) The upper and lower layer transistors have alignment errors, and the requirement on photoetching precision is extremely high; (4) When the problem of source-drain interconnection of the upper transistor and the lower transistor is solved, the etching time needs to be precisely controlled so as to ensure the depth of the source-drain contact metal of the lower transistor; (5) In layout design, the location of the active structure (e.g., fin structure) in the transistor is fixed, which limits the width of the source-drain metal, resulting in a larger resistance of the source-drain metal, which is detrimental to the performance of the circuit.
In order to solve the above technical problems, embodiments of the present application provide a source-drain interconnection method of a self-aligned transistor, so as to reduce the difficulty in controlling the etching time for manufacturing an interconnection via structure.
In the embodiment of the application, the self-aligned transistor can be applied to a semiconductor device such as a memory, a processor and the like.
In an embodiment, the self-aligned transistor may comprise at least two transistors, for example a first transistor and a second transistor. The first transistor and the second transistor are arranged opposite to each other. The first active structure in the first transistor and the second active structure in the second transistor are formed through the same process, and at this time, it can be understood that the first transistor and the second transistor share the same active structure, and the first active structure and the second active structure are self-aligned.
In the embodiment of the application, the first transistor and the second transistor in the self-aligned transistor may be transistors of the same type, such as any one of the following: fin field effect transistors, fully surrounding gate transistors and planar transistors.
Fig. 2 is a schematic diagram of a self-aligned transistor formed by a fin field effect transistor, and a method for manufacturing the self-aligned transistor according to an embodiment of the present application is described below with reference to the structure of the self-aligned transistor shown in fig. 2.
Fig. 1 is a schematic flow chart of a first implementation of a source-drain interconnection method of a self-aligned transistor in an embodiment of the present application, and referring to fig. 1, the source-drain interconnection method of the self-aligned transistor may include:
s101, forming an active structure on a semiconductor substrate, wherein the active structure comprises a first active structure and a second active structure.
The semiconductor substrate in the embodiments of the present application may be a silicon (Si) substrate, or may be a silicon-on-insulator (SOI) substrate, or may be a substrate made of other semiconductor materials, which is not specifically limited in the embodiments of the present application.
It will be appreciated that when the types of self-aligned transistors are different, the arrangement of the substrates is correspondingly different. For example, when the self-aligned transistor is a fin field effect transistor or a planar transistor, the semiconductor substrate may be a single-layer structure, that is, a substrate made of one semiconductor material is used; when the self-aligned transistor is a fully-around gate transistor, the semiconductor substrate may be a stacked structure, i.e., a stack in which a Si material and a silicon germanium (SiGe) material are stacked.
In some embodiments, when the self-aligned collective transistor is a finfet, the S101 may include: etching the semiconductor substrate to form a plurality of fin structures; the upper half of the fin structure is a first active structure, and the lower half of the fin structure is a second active structure.
In other embodiments, when the self-aligned collective transistor is a fully-around gate transistor, S101 may include: etching a semiconductor substrate to form a columnar structure, wherein the semiconductor substrate is formed by alternately depositing silicon layers and silicon germanium layers; the upper half part of the columnar structure is a first active structure, and the lower half part of the columnar structure is a second active structure.
In still other embodiments, when the self-aligned collective tube is a planar transistor, S101 described above may include: etching the semiconductor substrate to form a block structure; the upper half part of the block structure is a first active structure, and the lower half part of the block structure is a second active structure.
In the embodiment of the application, since the self-aligned transistor includes two transistors (i.e., the first transistor and the second transistor), and the first active structure of the first transistor and the second active structure of the second transistor are formed by the same etching process, a larger etching depth can be used when etching the semiconductor substrate. For example, the height of the etched fin structure (which may also be a columnar structure or a bulk structure) may be greater than 100nm. It should be noted that the height of the fin structure may be set according to practical situations, which is not specifically limited in the embodiments of the present application.
In some embodiments, after the active structure, the method may further include: oxide is filled over the active structure to form a shallow trench isolation structure (shallow trench isolation, STI). The height of the shallow trench isolation structure is greater than that of the active structure.
In the embodiment of the present application, the oxide forming the shallow trench isolation structure may be any one of the following: silicon nitride (SiN, si) 3 N 4 ) Silicon dioxide (SiO) 2 ) Or silicon oxycarbide (SiCO), and the like.
In some embodiments, after forming the shallow trench isolation structure, the method may further include: a chemical-mechanical planarization (CMP) process is performed on the shallow trench isolation structure.
In the embodiment of the application, the shallow trench isolation structure is subjected to chemical mechanical planarization, so that the corresponding corrosion depths of the shallow trench isolation structures in different areas are the same when the shallow trench isolation structure is etched later, and the heights of the tops of the exposed active structures are the same.
In some embodiments, after forming the shallow trench isolation structure, the method may further include: a portion of the shallow trench isolation structure is removed by etching to expose the first active structure.
It will be appreciated that in order to perform subsequent fabrication of the first transistor on the first active structure, such as fabricating the first source drain structure, the upper half of the shallow trench isolation structure may be etched first, so that the first active structure is exposed for subsequent fabrication processes.
It should be noted that, the etching process mentioned in the embodiments of the present application may include any of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal processes, to which embodiments of the present application are not limited.
In the embodiment of the present application, the solvent used for etching the shallow trench isolation structure may be: DHF solution or BOE solution. The solvent used in the etching process according to the embodiment of the present application may be selected according to the actual situation, and is not limited to the DHF solution or the BOE solution described above.
In some embodiments, after exposing the first active structure, ion implantation may be performed at the junction of the first active structure and the second active structure to form an electrical isolation layer for electrically isolating the first active structure from the second active structure.
Wherein the ion implanted ions comprise P-type ions, N-type ions or oxygen ions. The P-type ion may be one of: boron (B), gallium (Ga), aluminum (Al). The N-type ion may be one of: phosphorus (P), arsenic (As), antimony (Sb).
S102, based on the first active structure, a first source drain structure, a first interlayer dielectric layer and first source drain metal are sequentially formed, and the first active structure, the first source drain structure and the first source drain metal are wrapped by the first interlayer dielectric layer.
It will be appreciated that the removal of the shallow trench isolation structure and the exposure of the first active structure may provide a gate region and a source drain recess of the first transistor. Depositing a semiconductor material in a gate region of the first transistor may result in a first dummy gate structure of the first transistor. And carrying out source-drain epitaxial growth on the source-drain groove of the first transistor to obtain a first source-drain structure. And depositing a semiconductor material above the first active structure to obtain a first interlayer dielectric layer. And depositing a metal material above the first source drain structure to obtain the first source drain metal.
In some embodiments, a method of forming a first dummy gate structure may include: the gate region of the first transistor is opened by photolithography and a semiconductor material (e.g., polysilicon) is deposited in the gate region to form a first dummy gate structure of the first transistor.
In some embodiments, after forming the first dummy gate structure, spacers may be formed on both sides of the first dummy gate structure.
In some possible embodiments, the step S102 may include: etching a part of the first active structure to form a first source drain structure; depositing a semiconductor material on the first active structure and the first source drain structure to form a first interlayer dielectric layer; etching a first part of the first interlayer dielectric layer to form first source drain metal; and etching a second part of the first interlayer dielectric layer to form a first interconnection through hole structure, wherein the first interconnection through hole structure is connected with the first source drain metal.
In some embodiments, etching a portion of the first active structure to form a first source drain structure may include: the source drain recess of the first transistor may be provided by etching away a portion of the first active structure. And forming a strained material such as silicon germanium or silicon carbide in the source-drain grooves by using the spacer as a mask through selective epitaxial growth so as to fill the source-drain grooves of the first transistor, and then forming a first source-drain structure on the strained material through a heavy doping process.
It should be noted that, for convenience of description, the first source-drain structure in the embodiments of the present application is referred to simply as a first source structure and/or a first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, the source-drain groove and the like are similar to those of the first source-drain structure, wherein 'source-drain' is abbreviated as 'source electrode and/or drain electrode'.
In some embodiments, depositing a semiconductor material over the first active structure and the first source drain structure to form a first interlayer dielectric layer may include: depositing an insulating material (e.g., silicon dioxide (SiO) 2 ) Forming a first interlayer dielectric layer; the first interlayer dielectric layer can cover the first active structure and the first source drain structure.
In some embodiments, etching a first portion of the first interlayer dielectric layer to form a first source drain metal; etching the second portion of the first interlayer dielectric layer to form a first interconnect via structure, the first interconnect via structure being connected to the first source drain metal, may include: and etching the part of the first interlayer dielectric layer above the first source-drain structure (namely the first part of the first interlayer dielectric layer) until the upper surface of the first source-drain structure is exposed to form a first source-drain metal groove. And depositing a metal material in the first source drain metal groove to obtain the first source drain metal. And then, etching the part of the first interlayer dielectric layer positioned on the side surface of the first source-drain groove (namely the second part of the first interlayer dielectric layer), wherein the etching depth can be lower than that of the epitaxy of the first source-drain structure, forming a groove-shaped hole, and depositing a metal material which is the same as the metal of the first source-drain in the groove-shaped hole to obtain the first interconnection through hole structure.
It should be noted that, in the above embodiment, the order of preparing the first source drain metal first and then preparing the first interconnection via structure is only an example, and the first interconnection via structure may be prepared first and then preparing the first source drain metal, or the first source drain metal and the first interconnection via structure may be prepared simultaneously. The prepared first source drain metal and the first interconnection through hole structure are mutually connected, and the first source drain metal and the first interconnection through hole structure can be understood as a whole structure.
In other possible embodiments, during the preparation of the first transistor, the first interconnect via structure in the first transistor may not be prepared, and in the case where the first interconnect via structure is not prepared, S102 may include: etching a part of the first active structure to form a first source drain structure; depositing a semiconductor material on the first active structure and the first source drain structure to form a first interlayer dielectric layer; and etching the third part of the first interlayer dielectric layer to form a first source drain metal.
It should be noted that, the process of forming the first source-drain structure, the first interlayer dielectric layer and the first source-drain metal is the same as that of the above embodiment, and this is not repeated in this embodiment.
S103, rewinding and removing the semiconductor substrate.
It will be appreciated that after forming the first source-drain structure, the first interlayer dielectric layer and the first source-drain metal, other structures in the first transistor may be fabricated according to standard procedures. After the preparation of the first transistor is finished, the first transistor is turned over, and the semiconductor substrate is removed, so that the second active structure is placed upwards, and the subsequent preparation of the second transistor is facilitated.
In some embodiments, before S103, the method may further include: forming a first transistor based on the first interlayer dielectric layer; the first transistor is bonded to a carrier wafer.
It is understood that subsequent processes (e.g., dielectric deposition between interconnect lines, metal line formation, lead-out pad formation, etc.) are performed on top of the first interlayer dielectric layer to form a first metal interconnect layer of the first transistor. An insulating material (e.g., silicon oxide) is deposited over the first metal interconnect layer to form a first insulating layer and the first insulating layer is bonded to the carrier wafer.
In the embodiment of the application, the bonded wafer carrier can provide physical support for the turned first transistor after rewinding, so that the first transistor is effectively prevented from being broken due to external force in the process of preparing the second transistor.
In some embodiments, the method may further include, prior to forming the first metal interconnect layer: and removing the first dummy gate structure by etching to expose the gate region of the first transistor, and depositing a metal material in the gate region of the first transistor to form the first gate structure of the first transistor.
In some embodiments, after removing the semiconductor substrate, the method may further include: a portion of the shallow trench isolation structure is removed by etching to expose the second active structure.
It will be appreciated that for subsequent fabrication of the second transistor on the second active structure, such as for the fabrication of the second source drain structure, the lower half of the shallow trench isolation structure may be etched first so that the second active structure is exposed for subsequent fabrication processes.
It should be noted that, when etching the lower half portion of the shallow trench isolation structure, a shallow trench isolation structure with a certain thickness may be reserved, and the reserved shallow trench isolation structure may be used to isolate the first transistor and the second transistor.
S104, forming a second source drain structure, a second interlayer dielectric layer and second source drain metal in sequence based on the second active structure, wherein the second active structure, the second source drain structure and the second source drain metal are wrapped by the second interlayer dielectric layer.
The first source drain metal and the second source drain metal are communicated through an interconnection through hole structure, and the interconnection through hole structure penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer.
It will be appreciated that the removal of the shallow trench isolation structure and the exposure of the second active structure may provide a gate region and a source drain recess of the second transistor. Depositing semiconductor material in the gate region of the second transistor may result in a second dummy gate structure of the second transistor. And (3) carrying out source-drain epitaxial growth on the source-drain grooves of the second transistor to obtain a second source-drain structure. And depositing a semiconductor material above the second active structure to obtain a second interlayer dielectric layer. And depositing a metal material above the second source-drain structure to obtain a second source-drain metal.
In some embodiments, a method of forming a second dummy gate structure may include: the gate region of the second transistor is opened by photolithography and a semiconductor material (e.g., polysilicon) is deposited in the gate region to form a first dummy gate structure of the second transistor.
In some embodiments, after forming the second dummy gate structure, spacers may be formed on both sides of the second dummy gate structure.
In some possible embodiments, the step S104 may include: etching a part of the second active structure to form a second source drain structure; depositing a semiconductor material on the second active structure and the second source drain structure to form a second interlayer dielectric layer; etching the first part of the second interlayer dielectric layer to form second source drain metal; and etching a second part of the second interlayer dielectric layer until the second part is communicated with the first interconnection through hole structure to form a second interconnection through hole structure, wherein the second interconnection through hole structure and the first interconnection through hole structure form an interconnection through hole structure.
In some embodiments, etching a portion of the second active structure to form a second source drain structure may include: the source drain recess of the second transistor may be provided by etching away a portion of the second active structure. And forming a strained material such as silicon germanium or silicon carbide in the source-drain grooves by using the spacer as a mask through selective epitaxial growth so as to fill the source-drain grooves of the second transistor, and then forming a second source-drain structure on the strained material through a heavy doping process.
In some embodiments, depositing a semiconductor material over the second active structure and the second source drain structure to form a second interlayer dielectric layer may include: depositing insulating materials (such as silicon dioxide) above the second active structure and the second source drain structure to form a second interlayer dielectric layer; the second interlayer dielectric layer can cover the second active structure and the second source drain structure.
It should be noted that, in the embodiments of the present application, the first interlayer dielectric layer and the second interlayer dielectric layer may be formed of the same material or different materials.
In some embodiments, etching the first portion of the second interlayer dielectric layer to form a second source drain metal; etching the second portion of the second interlayer dielectric layer until communicating with the first interconnect via structure to form a second interconnect via structure, the second interconnect via structure and the first interconnect via structure forming an interconnect via structure, may include: and etching the part of the second interlayer dielectric layer above the second source-drain structure (namely the first part of the second interlayer dielectric layer) until the upper surface of the second source-drain structure is exposed to form a second source-drain metal groove. And depositing a metal material in the second source-drain metal groove to obtain the second source-drain metal. And etching a part of the second interlayer dielectric layer (namely a second part of the second interlayer dielectric layer) positioned on the side surface of the second source-drain groove, wherein the second part of the second interlayer dielectric layer is aligned with the second part of the first interlayer dielectric layer, and stopping etching when the second interlayer dielectric layer is etched to a position communicated with the first interconnection through hole structure, so as to form a groove-shaped hole, and depositing a metal material which is the same as the second source-drain metal in the groove-shaped hole, so as to obtain the second interconnection through hole structure.
In the embodiment of the application, since the first interconnection through hole structure is connected with the first source drain metal, the second interconnection through hole structure is connected with the second source drain metal, and the second interconnection through hole structure is communicated with the first interconnection through hole structure, the interconnection between the first source drain metal and the second source drain metal is realized.
It should be noted that the above scheme for preparing the second interconnection via structure corresponds to the above scheme for preparing the first interconnection via structure, and the first interconnection via structure and the second interconnection via structure together form an interconnection via structure in the self-aligned transistor, so as to implement interconnection of the first source drain metal and the second source drain metal.
It should be noted that, in the above embodiment, the order of preparing the second source drain metal first and then preparing the second interconnection via structure is only an example, and the second interconnection via structure may be prepared first and then preparing the second source drain metal, or the second source drain metal and the second interconnection via structure may be prepared simultaneously. The second source drain metal and the second interconnection through hole structure are connected with each other, which can be understood as that the second source drain metal and the second interconnection through hole structure are a whole structure.
In other possible embodiments, during the process of preparing the first transistor, the first interconnect via structure in the first transistor may not be prepared, and in the case where the first interconnect via structure is not prepared, S104 may include: etching a part of the second active structure to form a second source drain structure; depositing a semiconductor material on the second active structure and the second source drain structure to form a second interlayer dielectric layer; etching a third part of the second interlayer dielectric layer to form second source drain metal; and etching the fourth part of the second interlayer dielectric layer until penetrating the first interlayer dielectric layer to form an interconnection through hole structure.
It should be noted that, the process of forming the second source-drain structure, the second interlayer dielectric layer and the second source-drain metal is the same as that of the above embodiment, and this is not repeated in this embodiment.
In some embodiments, etching the fourth portion of the second interlayer dielectric layer until penetrating the first interlayer dielectric layer to form the interconnect via structure may include: etching the part of the second interlayer dielectric layer positioned on the side surface of the second source drain metal groove (namely the fourth part of the second interlayer dielectric layer), stopping etching until the side surface of the first source drain metal is etched, forming a groove-shaped hole, and depositing a metal material which is the same as the second source drain metal in the groove-shaped hole to obtain the interconnection through hole structure. The interconnection through hole structure penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer.
In some possible implementations, the interconnect via structure is located on one side of the active structure; or, the interconnection through hole structure is positioned at two sides of the active structure; or, the interconnect via structure is located in the middle of the active structure.
It will be appreciated that for a finfet, the active structure is a plurality of fin structures and the interconnect via structure may be located on one side of the plurality of fin structures; may also be located on both sides of the plurality of fin structures; when the spacing between the plurality of fin structures is large and the source and drain extensions do not merge together, the interconnect via structure may be located between adjacent source and drain (it is also understood that the interconnect via structure may be located in the middle of the left and right fin structures). For a fully-surrounding gate transistor, the active structure is a nano-lamellar structure arranged at intervals, and the interconnection through-hole structure can be positioned at one side of the nano-lamellar structure; or can be located on both sides of the nanolaminate structure. For planar transistors, the active structure is a bulk structure, and the interconnect via structure may be located on one side of the bulk structure; or may be located on both sides of the block structure.
In other possible embodiments, the location of the active structure may be biased to the left or right of the self-aligned transistor during layout design such that the location of the active structure is not in the middle of the semiconductor substrate; on the other side (i.e., right or left), an interconnect via structure of greater width is formed.
In the embodiment of the application, the position of the active structure is moved to one side, so that a larger space can be reserved for the interconnection through hole structure, the width of the interconnection through hole structure is increased, and the resistance of the first source drain metal and the second source drain metal during interconnection is reduced.
In some possible embodiments, after the step S104, the method may further include: and forming a second transistor based on the second interlayer dielectric layer.
Wherein the second transistor is self-aligned with the first transistor in a vertical direction of the semiconductor substrate.
It will be appreciated that subsequent processes (e.g., dielectric deposition between interconnect lines, metal line formation, lead-out pad formation, etc.) are performed on top of the second interlayer dielectric layer to form a second metal interconnect layer for the second transistor, to which the second transistor in the self-aligned transistor is completed.
In some embodiments, the method may further include, prior to forming the second metal interconnect layer: and removing the second pseudo gate structure by etching to expose a gate region of the second transistor, and depositing a metal material in the gate region of the second transistor to form a second gate structure of the second transistor.
In the embodiment of the present application, the metal materials of the first gate structure and the second gate structure may be any of the following: the materials of the tantalum nitride (TaN), the titanium nitride (TiN), the aluminum nitride (AlN), the titanium aluminum carbide (TiAlC), the titanium aluminum nitride (TiAlN), the first gate structure and the second gate structure may be selected according to actual situations, and are not limited to the above listed metal materials.
In the embodiment of the present application, the materials of the first gate structure and the second gate structure may be made of the same or different metal materials according to practical situations, which is not specifically limited in the embodiment of the present application.
In some embodiments, before preparing the first gate structure, the method may further include: and depositing a semiconductor material on the surface of the first active structure to form a first gate dielectric layer of the first transistor, wherein the first gate dielectric layer is used for isolating the first active structure and the first gate structure.
In this embodiment of the present application, a method for preparing a second gate dielectric layer of a second transistor is the same as a method for preparing a first gate dielectric layer, which is not described in detail in this embodiment of the present application.
It should be noted that the materials for preparing the first gate dielectric layer and the second gate dielectric layer may be the same or different, which is not particularly limited in the embodiment of the present application.
The self-aligned transistor provided in the embodiments of the present application will be described below by taking the first transistor and the second transistor as fin field effect transistors as an example. Fig. 2 is a schematic diagram of a first structure of a self-aligned transistor according to an embodiment of the present application. In fig. 2 (a) is a top view of the self-aligned transistor, it should be noted that, for ease of understanding, only fin structures, gate structures, and source/drain structures are shown in the top view; (b) A cut-out view of the self-aligned transistor along the cut-out direction (i.e., the A-A' direction) of the source-drain structure; (c) A cut-away view of the self-aligned transistor is taken along the cut-away direction (i.e., the B-B' direction) of the gate structure.
Referring to fig. 2, the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of fin structures. The fin structure is divided into an upper and a lower part, denoted as a first part, which serves as a first active structure 111 in the first transistor 11, and a second part, which serves as a second active structure 121 in the second transistor 12. The first source drain metal 113 in the first transistor 11 and the second source drain metal 123 in the second transistor 12 are in communication with each other through the interconnect via structure 13. A shallow trench isolation layer 14 is arranged between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used for isolating the first transistor 11 and the second transistor 12.
Fig. 3 is a first schematic structure of an interconnect via structure in an embodiment of the present application. Fig. 3 shows a schematic exploded view of the interconnect via structure 13, the first source drain metal 113, and the second source drain metal 123. Referring to fig. 3, the interconnection via structure 13 may include two parts, one part being a first interconnection via structure 131, the first interconnection via structure 131 being connected with the first source-drain metal 113; another part is a second interconnection via structure 132, and the second interconnection via structure 132 is connected to the second source drain metal 123; the first interconnect via structure 131 and the second interconnect via structure 132 are connected.
It should be noted that, the interconnect via structure 13 in fig. 3 corresponds to the interconnect via structure 13 in the self-aligned transistor shown in fig. 2, and the interconnect via structure 13 in the embodiment of the present application may also be other structures.
In the embodiment of the present application, the first active structure 111 of the first transistor 11 and the second active structure 121 of the second transistor 12 are formed by the same etching process, so that self-alignment of the first transistor 11 and the second transistor 12 can be achieved.
The process of fabricating the self-aligned transistor shown in fig. 2 will be described below in conjunction with the above fabrication method. The self-aligned transistor shown in fig. 2 can be prepared by the process shown in fig. 4A to 4E, and fig. 4A to 4E are schematic diagrams of a first preparation process of the self-aligned transistor according to the embodiments of the present application.
In an example, taking the first transistor 11 and the second transistor 12 as fin field effect transistors as an example, the first manufacturing process of the self-aligned transistor 10 with source-drain interconnection may include the following steps:
the first step: a semiconductor substrate 21 such as a Si substrate is provided (see (a) in fig. 4A).
And a second step of: the semiconductor substrate 21 is etched to form a plurality of fin structures 22 (see (b) in fig. 4A).
And a third step of: oxide is filled over fin structure 22 to form shallow trench isolation structure 23 (see (c) in fig. 4A). The height of the shallow trench isolation structure 23 is greater than that of the fin structure 22, and may cover a plurality of fin structures 22. Then, the shallow trench isolation structure 23 is subjected to a chemical mechanical planarization process.
Fourth step: a portion of shallow trench isolation structure 23 is etched using standard procedures to expose a first portion of fin structure 22 (i.e., first active structure 111) (see (a) in fig. 4B).
Fifth step: a first portion of fin structure 22 is etched to form source-drain recesses for first transistor 11. The gate region of the first transistor 11 is then opened by photolithography, and polysilicon is deposited at the gate region to form a first dummy gate structure 241. First spacers 116 are formed on both sides of the first dummy gate structure 241 (see (B) in fig. 4B).
Sixth step: at the source-drain recesses of the first transistor 11, source-drain epitaxial growth is performed to form first source-drain structures 112. Then, a semiconductor material is deposited over the first active structure 111 to form a first interlayer dielectric layer 114 (see (c) in fig. 4B).
Seventh step: a portion of the first interlayer dielectric layer 114 is removed by etching to form a first source drain metal recess, and a metal material is deposited in the first source drain metal recess to form a first source drain metal 113. Next, a first trench-shaped hole is formed at the side of the first source-drain metal 113 (i.e., the side of the source-drain epitaxy), a metal material is deposited in the first trench-shaped hole, and a first interconnection via structure 131 is formed, the first interconnection via structure 131 being connected to the first source-drain metal 113 (see (a) in fig. 4C).
Eighth step: the first dummy gate structure 241 is removed and metal is deposited in the gate region to form the first gate structure 115. Then, over the first interlayer dielectric layer 114, a subsequent process is performed to form a first metal interconnection layer 117 (see (b) in fig. 4C).
Ninth step: an oxide is deposited over the first metal interconnect layer 117 forming a first insulating layer 15, the first insulating layer 15 being bonded to a carrier wafer 16. Next, the first transistor 11 after bonding the carrier wafer 16 is rewound so that the semiconductor substrate 21 is placed upward (see (C) in fig. 4C).
Tenth step: the semiconductor substrate 21 is removed by etching, and the shallow trench isolation structure 23 is etched, exposing the second portion of the fin structure 22 (see (a) in fig. 4D).
When the shallow trench isolation structure 23 is etched, the etching depth is controlled, and the shallow trench isolation structure 23 having a certain thickness is reserved and used as the shallow trench isolation layer 14. The shallow trench isolation layer 14 is used to isolate the first transistor 11 and the second transistor 12.
Eleventh step: a second source-drain structure 122, a second dummy gate structure 242, a second spacer 126, and a second interlayer dielectric layer 124 are formed on a second portion of the fin structure 22 (see (b) in fig. 4D) (see fifth and sixth steps for specific fabrication processes).
Twelfth step: a portion of the second interlayer dielectric layer 124 is removed by etching to form a second source drain metal recess, and a metal material is deposited in the second source drain metal recess to form a second source drain metal 123. The first source drain metal 113 and the second source drain metal 123 have the same shape and are disposed opposite to each other. Next, a second trench-shaped hole is formed at the side of the second source-drain metal 123 (aligned to the position of the first interconnect via structure 131) by etching. And when the second groove-shaped hole is etched, stopping etching until the second groove-shaped hole is communicated with the first groove-shaped hole. A metal material is deposited in the second trench-shaped hole to form a second interconnect via structure 132, the second interconnect via structure 132 being connected to the second source drain metal 123 (see (c) in fig. 4D).
Thirteenth step: the second gate structure 125 and the second metal interconnection layer 127 are formed (see eighth step for specific manufacturing process) (see fig. 4E).
Thus, the self-aligned transistor 10 is prepared, in which the first transistor 11 and the second transistor 12 are fin field effect transistors, and the first source drain metal 113 and the second source drain metal 123 are interconnected through the first interconnection via structure 131 and the second interconnection via structure 132.
The interconnect via structure 13 in the self-aligned transistor 10 shown in fig. 2 described above is composed of two parts (i.e., the first interconnect via structure 131 and the second interconnect via structure 132), and it is understood that the interconnect via structure 13 in the self-aligned transistor 10 shown in fig. 2 described above is formed by two processes. In another embodiment, the interconnect via structure 13 in the self-aligned transistor 10 may be formed in one process. Fig. 5 is a schematic diagram of a second structure of a self-aligned transistor according to an embodiment of the present application. In fig. 5 (a) is a top view of the self-aligned transistor, it should be noted that, for ease of understanding, only fin structures, gate structures, and source/drain structures are shown in the top view; (b) A cut-out view of the self-aligned transistor along the cut-out direction (i.e., the A-A' direction) of the source-drain structure; (c) A cut-away view of the self-aligned transistor is taken along the cut-away direction (i.e., the B-B' direction) of the gate structure.
Referring to fig. 5, the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of fin structures. The fin structure is divided into an upper and a lower part, denoted as a first part, which serves as a first active structure 111 in the first transistor 11, and a second part, which serves as a second active structure 121 in the second transistor 12. The first source drain metal 113 in the first transistor 11 and the second source drain metal 123 in the second transistor 12 are in communication with each other through the interconnect via structure 13. The interconnect via structure 13 is located on one side of the active structure. Both ends of the interconnection via structure 13 are connected to the first source-drain metal 113 and the second source-drain metal 123, respectively. A shallow trench isolation layer 14 is arranged between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used for isolating the first transistor 11 and the second transistor 12.
Fig. 6 is a schematic diagram of a second structure of an interconnect via structure in an embodiment of the present application. Fig. 6 shows a schematic exploded view of the interconnect via structure 13, the first source drain metal 113 and the second source drain metal 123, and the interconnect via structure 13 extends from the second source drain metal 123 to the first source drain metal 113, as shown in fig. 6. Both ends of the interconnection via structure 13 are connected to the first source-drain metal 113 and the second source-drain metal 123, respectively.
The process of fabricating the self-aligned transistor shown in fig. 5 will be described below in conjunction with the above fabrication method.
The first step: a silicon substrate is provided.
And a second step of: the silicon substrate is etched to form a plurality of fin structures.
And a third step of: shallow trench isolation structures are formed (see, for example, the third step in the first fabrication process of the self-aligned transistor).
Fourth step: a first portion of the fin structure (i.e., the first active structure) is exposed (see, in particular, the fourth step in the first fabrication process of the self-aligned transistor).
Fifth step: the first dummy gate structure and spacers are formed (see, for example, the fifth step in the first fabrication process of the self-aligned transistor).
Sixth step: a first source-drain structure and a first interlayer dielectric layer are formed (see, for example, the sixth step in the first fabrication process of the self-aligned transistor).
Seventh step: and removing a part of the first interlayer dielectric layer by etching to form a first source drain metal groove, and depositing a metal material in the first source drain metal groove to form a first source drain metal.
Eighth step: a first gate structure and a first metal interconnect layer are formed (see, for example, the eighth step in the first fabrication process of the self-aligned transistor).
Ninth step: the semiconductor substrate is reworked, removed and a second portion of the fin structure is exposed (see, in particular, the ninth and tenth steps in the first fabrication process of the self-aligned transistor).
Tenth step: a second source-drain structure, a second dummy gate structure, and a second interlayer dielectric layer are formed on the second portion of the fin structure (see fifth and sixth steps in the first fabrication process of the alignment transistor for a specific fabrication process).
Eleventh step: and removing a part of the second interlayer dielectric layer by etching to form a second source drain metal groove, and depositing a metal material in the second source drain metal groove to form a second source drain metal. The first source drain metal and the second source drain metal have the same shape and are arranged oppositely. Then, a third groove-shaped hole is formed on the side surface of the second source drain metal by etching. And when the third groove-shaped hole is etched, stopping etching until the third groove-shaped hole is contacted with the first source drain metal and the third groove-shaped hole penetrates through the first interlayer dielectric layer. And depositing a metal material in the third groove-shaped hole to form an interconnection through hole structure, wherein two ends of the interconnection through hole structure are respectively connected with the first source drain metal and the second source drain metal.
Twelfth step: a second gate structure, a second metal interconnect layer, is formed (see for example, the eighth step in the first fabrication process of the self-aligned transistor).
Thus, the self-aligned transistor 10 is fabricated, in which the first transistor 11 and the second transistor 12 are fin field effect transistors, and the first source drain metal 113 and the second source drain metal 123 are interconnected by the interconnection via structure 13.
In some embodiments, fig. 7 is a schematic diagram of a third structure of a self-aligned transistor according to an embodiment of the present application. In fig. 7 (a) is a top view of the self-aligned transistor, it should be noted that, for ease of understanding, only fin structures, gate structures, and source/drain structures are shown in the top view; (b) A cut-out view of the self-aligned transistor along the cut-out direction (i.e., the A-A' direction) of the source-drain structure; (c) A cut-away view of the self-aligned transistor is taken along the cut-away direction (i.e., the B-B' direction) of the gate structure.
Referring to fig. 7, the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of fin structures. In the A-A' direction, the plurality of fin structures are positioned offset to one side (e.g., the a side) of the semiconductor substrate. The fin structure is divided into an upper and a lower part, denoted as a first part, which serves as a first active structure 111 in the first transistor 11, and a second part, which serves as a second active structure 121 in the second transistor 12. The first source drain metal 113 in the first transistor 11 and the second source drain metal 123 in the second transistor 12 are in communication with each other through the interconnect via structure 13. Both ends of the interconnection via structure 13 are connected to the first source-drain metal 113 and the second source-drain metal 123, respectively. A shallow trench isolation layer 14 is arranged between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used for isolating the first transistor 11 and the second transistor 12.
Referring to fig. 7 and 2, the interconnect via structure 13 in fig. 7 has a larger width than the interconnect via structure 13 in fig. 2. This is because the active structure of the self-aligned transistor 10 shown in fig. 7 is not arranged in the middle of the semiconductor substrate, but is biased to one side of the semiconductor substrate, leaving more room for the interconnect via structure 13. The increased width of the interconnect via structure 13 may reduce the resistance of the first and second source-drain structures 112 and 122 when interconnected.
In some embodiments, in the process of fabricating the self-aligned transistor 10 shown in fig. 7, when etching the semiconductor substrate to form the fin structure, the etching position is controlled such that the position of the formed fin structure is biased to one side of the semiconductor substrate, and a larger space is reserved on the other side of the semiconductor substrate for subsequent fabrication of the interconnect via structure 13. In forming the interconnect via structure 13, a trench-shaped hole having a larger diameter is etched, and then a metal material is deposited in the trench-shaped hole to form the interconnect via structure 13. The method for manufacturing other structures in the self-aligned transistor 10 shown in fig. 7 is the same as the method for manufacturing the self-aligned transistor 10 shown in fig. 2, and reference may be made to the first manufacturing process of the self-aligned transistor 10, which is not described in detail in the embodiments of the present application.
In some embodiments, fig. 8 is a schematic diagram of a fourth structure of a self-aligned transistor according to an embodiment of the present application. In fig. 6 (a) is a top view of the self-aligned transistor, it should be noted that, for ease of understanding, only fin structures, gate structures, and source/drain structures are shown in the top view; (b) A cut-out view of the self-aligned transistor along the cut-out direction (i.e., the A-A' direction) of the source-drain structure; (c) A cut-away view of the self-aligned transistor is taken along the cut-away direction (i.e., the B-B' direction) of the gate structure.
Referring to fig. 8, the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of fin structures. The fin structure is divided into an upper and a lower part, denoted as a first part, which serves as a first active structure 111 in the first transistor 11, and a second part, which serves as a second active structure 121 in the second transistor 12. The first source drain metal 113 in the first transistor 11 and the second source drain metal 123 in the second transistor 12 are in communication with each other through the interconnect via structure 13. The interconnection via structure 13 is located at two sides of the active structure, and two ends of the interconnection via structure 13 are connected to the first source drain metal 113 and the second source drain metal 123, respectively. A shallow trench isolation layer 14 is arranged between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used for isolating the first transistor 11 and the second transistor 12.
In some embodiments, in the process of fabricating the self-aligned transistor shown in fig. 8, trench-shaped holes are etched simultaneously on both sides of the active structure to form the interconnect via structures 13 on both sides of the active structure when forming the interconnect via structures 13. The method for manufacturing other structures in the self-aligned transistor 10 shown in fig. 8 is the same as the method for manufacturing the self-aligned transistor 10 shown in fig. 2, and reference may be made to the first manufacturing process of the self-aligned transistor 10, which is not described in detail in the embodiments of the present application.
In some embodiments, fig. 9 is a schematic diagram of a fifth structure of a self-aligned transistor according to an embodiment of the present application. In fig. 9 (a) is a top view of the self-aligned transistor, it should be noted that, for ease of understanding, only fin structures, gate structures, and source/drain structures are shown in the top view; (b) A cut-out view of the self-aligned transistor along the cut-out direction (i.e., the A-A' direction) of the source-drain structure; (c) A cut-away view of the self-aligned transistor is taken along the cut-away direction (i.e., the B-B' direction) of the gate structure.
Referring to fig. 9, the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of fin structures. The fin structure is divided into an upper and a lower part, denoted as a first part, which serves as a first active structure 111 in the first transistor 11, and a second part, which serves as a second active structure 121 in the second transistor 12. The first source drain metal 113 in the first transistor 11 and the second source drain metal 123 in the second transistor 12 are in communication with each other through the interconnect via structure 13. The interconnect via structure 13 is located in the middle of the adjacent source-drain extensions (which may be understood as being located in the middle of the plurality of fin structures), and both ends of the interconnect via structure 13 are connected to the first source-drain metal 113 and the second source-drain metal 123, respectively. A shallow trench isolation layer 14 is arranged between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used for isolating the first transistor 11 and the second transistor 12.
In some embodiments, in the process of fabricating the self-aligned transistor 10 shown in fig. 9, when etching a plurality of fin structures on a semiconductor substrate, the pitch between the fin structures is increased, and when growing source-drain epitaxy, the source-drain epitaxy is not fused together, and the positions of the interconnection via structures 13 are reserved in the middle of the fin structures and the source-drain epitaxy. In forming the interconnect via structure 13, a trench-shaped hole is etched in the middle of the active structure to form the interconnect via structure 13 in the middle of the active structure. The method for manufacturing other structures in the self-aligned transistor 10 shown in fig. 9 is the same as the method for manufacturing the self-aligned transistor shown in fig. 2, and reference may be made to the first manufacturing process of the self-aligned transistor, which is not described in detail in the embodiment of the present application.
In some embodiments, fig. 10 is a schematic diagram of a sixth structure of a self-aligned transistor according to an embodiment of the present application. In fig. 10, (a) is a top view of the self-aligned transistor, and for ease of understanding, only the nano-lamellar structure, the gate structure, and the source-drain structure are shown in the top view; (b) A cut-out view of the self-aligned transistor along the cut-out direction (i.e., the A-A' direction) of the source-drain structure; (c) A cut-away view of the self-aligned transistor is taken along the cut-away direction (i.e., the B-B' direction) of the gate structure.
Referring to fig. 10, the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of nano-lamellar structures. The nano-platelet structure is divided into an upper and a lower part, denoted as a first part, which serves as a first active structure 111 in the first transistor 11, and a second part, which serves as a second active structure 121 in the second transistor 12. The first source drain metal 113 in the first transistor 11 and the second source drain metal 123 in the second transistor 12 are in communication with each other through the interconnect via structure 13. The interconnection via structure 13 is located at one side of the active structure, and both ends of the interconnection via structure 13 are connected to the first source drain metal 113 and the second source drain metal 123, respectively. A shallow trench isolation layer 14 is arranged between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used for isolating the first transistor 11 and the second transistor 12.
In some embodiments, in the process of fabricating the self-aligned transistor 10 shown in fig. 10, when etching the semiconductor substrate to form the nano-platelet structure, the etching position is controlled such that the position of the formed nano-platelet structure is biased to one side of the semiconductor substrate, leaving a larger space on the other side of the semiconductor substrate for subsequent fabrication of the interconnect via structure 13. In forming the interconnect via structure 13, a trench-shaped hole having a larger diameter is etched, and then a metal material is deposited in the trench-shaped hole to form the interconnect via structure 13. The method for manufacturing other structures in the self-aligned transistor 10 shown in fig. 10 is the same as the method for manufacturing the self-aligned transistor 10 shown in fig. 2, and reference may be made to the first manufacturing process of the self-aligned transistor 10, which is not described in detail in the embodiments of the present application.
In the embodiment of the present application, the interconnection through hole structure 13 in the self-aligned transistor 10 penetrates through the first interlayer dielectric layer 114 and the second interlayer dielectric layer 124, and interconnection between the first source drain structure 112 and the second source drain structure 122 is realized;
further, since the interconnection through hole structure 13 penetrates through the first interlayer dielectric layer 114 and the second interlayer dielectric layer 124, etching can be stopped at the source-drain metal by means of selective etching, so that the difficulty in controlling etching time in a source-drain interconnection scheme is reduced;
further, the interconnect via structure 13 may be disposed at any one of the following positions: one side of the active structure, both sides of the active structure, the middle of the active structure, which makes the interconnection of the first and second source drain structures 112, 122 in the self-aligned transistor 10 more flexible.
Further, the self-aligned transistor 10 provided in the embodiments of the present application may be detected using a detection analyzer, for example: scanning electron microscope (scanning electron microscope, SEM), transmission electron microscope (transmission electron microscope, TEM), scanning transmission electron microscope (scanning transmission electron microscopy, STEM), and the like. Taking TEM as an example, the self-aligned transistor 10 provided in the embodiments of the present application may detect the interconnection between the first source drain metal 113 and the second source drain metal 123 in a TEM slicing manner.
The embodiment of the application provides a semiconductor device, which comprises: a self-aligned transistor as in the above embodiments. Specific limitations of the self-aligned transistor can be seen from the self-aligned transistors shown in fig. 2, 5, 7, 8, 9 and 10, and will not be described herein.
An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device includes the self-aligned transistor described above. Specific limitations of the self-aligned transistor can be seen from the self-aligned transistors shown in fig. 2, 5, 7, 8, 9 and 10, and will not be described herein.
In the description of the present application, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In this application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described herein, as well as the features of the various embodiments or examples, may be combined by those skilled in the art without contradiction.
The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and variations may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (11)

1. A method of source-drain interconnection of a self-aligned transistor, the method comprising:
forming an active structure on a semiconductor substrate, wherein the active structure comprises a first active structure and a second active structure;
forming a first source drain structure, a first interlayer dielectric layer and first source drain metal in sequence based on the first active structure, wherein the first interlayer dielectric layer wraps the first active structure, the first source drain structure and the first source drain metal;
rewinding and removing the semiconductor substrate;
forming a second source-drain structure, a second interlayer dielectric layer and second source-drain metal in sequence based on the second active structure, wherein the second interlayer dielectric layer wraps the second active structure, the second source-drain structure and the second source-drain metal;
the first source drain metal and the second source drain metal are communicated through an interconnection through hole structure, and the interconnection through hole structure penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer.
2. The method of claim 1, wherein forming a first source-drain structure, a first interlayer dielectric layer, and a first source-drain metal in sequence based on the first active structure comprises:
etching a part of the first active structure to form the first source drain structure;
depositing a semiconductor material on the first active structure and the first source drain structure to form a first interlayer dielectric layer;
etching a first part of the first interlayer dielectric layer to form the first source drain metal;
and etching a second part of the first interlayer dielectric layer to form a first interconnection through hole structure, wherein the first interconnection through hole structure is connected with the first source drain metal.
3. The method of claim 2, wherein forming a second source-drain structure, a second interlayer dielectric layer, and a second source-drain metal in sequence based on the second active structure comprises:
etching a portion of the second active structure to form the second source drain structure;
depositing a semiconductor material on the second active structure and the second source drain structure to form a second interlayer dielectric layer;
etching the first part of the second interlayer dielectric layer to form second source drain metal;
And etching a second part of the second interlayer dielectric layer until the second part is communicated with the first interconnection through hole structure to form a second interconnection through hole structure, wherein the second interconnection through hole structure and the first interconnection through hole structure form the interconnection through hole structure.
4. The method of claim 1, wherein forming a first source-drain structure, a first interlayer dielectric layer, and a first source-drain metal in sequence based on the first active structure comprises:
etching a part of the first active structure to form the first source drain structure;
depositing a semiconductor material on the first active structure and the first source drain structure to form a first interlayer dielectric layer;
and etching a third part of the first interlayer dielectric layer to form the first source drain metal.
5. The method of claim 4, wherein forming a second source-drain structure, a second interlayer dielectric layer, and a second source-drain metal in sequence based on the second active structure comprises:
etching a portion of the second active structure to form the second source drain structure;
depositing a semiconductor material on the second active structure and the second source drain structure to form a second interlayer dielectric layer;
Etching a third part of the second interlayer dielectric layer to form second source drain metal;
and etching a fourth part of the second interlayer dielectric layer until penetrating the first interlayer dielectric layer to form the interconnection through hole structure.
6. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the interconnection through hole structure is positioned on one side of the active structure; or alternatively, the first and second heat exchangers may be,
the interconnection through hole structure is positioned on two sides of the active structure; or alternatively, the first and second heat exchangers may be,
the interconnect via structure is located in the middle of the active structure.
7. The method of claim 1, wherein prior to the rewinding and removing the semiconductor substrate, the method further comprises:
forming a first transistor based on the first interlayer dielectric layer;
and bonding the first transistor with a carrier wafer.
8. The method of claim 7, wherein after sequentially forming a second source-drain structure, a second interlayer dielectric layer, and a second source-drain contact structure based on the second active structure, the method further comprises:
and forming a second transistor based on the second interlayer dielectric layer, wherein the second transistor and the first transistor are self-aligned in the vertical direction of the semiconductor substrate.
9. A self-aligned transistor, comprising:
a first transistor;
a second transistor disposed opposite to the first transistor;
the first source-drain metal of the first transistor is communicated with the second source-drain metal of the second transistor through an interconnection through hole structure, and the interconnection through hole structure penetrates through the first interlayer dielectric layer of the first transistor and the second interlayer dielectric layer of the second transistor.
10. A semiconductor device, comprising: the self-aligned transistor of claim 9.
11. An electronic device, comprising: a circuit board and the semiconductor device according to claim 10, the semiconductor device being provided to the circuit board.
CN202311694549.0A 2023-12-11 2023-12-11 Source-drain interconnection method of self-aligned transistor, self-aligned transistor and device Pending CN117855145A (en)

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