CN117855145A - Source-drain interconnection method of self-aligned transistor, self-aligned transistor and device - Google Patents

Abstract

The application provides a source-drain interconnection method of a self-aligned transistor, the self-aligned transistor and a device, wherein the method comprises the following steps: forming an active structure on a semiconductor substrate, wherein the active structure comprises a first active structure and a second active structure; forming a first source-drain structure, a first interlayer dielectric layer and first source-drain metal in sequence based on the first active structure, wherein the first interlayer dielectric layer wraps the first active structure, the first source-drain structure and the first source-drain metal; rewinding and removing the semiconductor substrate; forming a second source-drain structure, a second interlayer dielectric layer and second source-drain metal in sequence based on the second active structure, wherein the second active structure, the second source-drain structure and the second source-drain metal are wrapped by the second interlayer dielectric layer; the first source drain metal and the second source drain metal are communicated through an interconnection through hole structure, and the interconnection through hole structure penetrates through the first interlayer dielectric layer and the second interlayer dielectric layer. By the method and the device, the difficulty in controlling etching time in a source-drain interconnection scheme can be reduced.

Description

Source-drain interconnection method of self-aligned transistor, self-aligned transistor and device

Technical Field

The present application relates to the semiconductor field, and in particular to a source-drain interconnection method of a self-aligned transistor, a self-aligned transistor and a device.

Background technique

As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

When using the traditional sequential method to prepare stacked transistors, there are the following technical difficulties: when solving the problem of source-drain interconnection between upper and lower transistors, it is necessary to accurately control the etching time to ensure the depth of the source-drain contact metal of the lower transistor.

Summary of the invention

The present application provides a source-drain interconnection method of a self-aligned transistor, a self-aligned transistor and a device, so as to reduce the difficulty of controlling the etching time in a source-drain interconnection scheme.

In a first aspect, an embodiment of the present application provides a method for source-drain interconnection of a self-aligned transistor, the method comprising: forming an active structure on a semiconductor substrate, the active structure comprising a first active structure and a second active structure; based on the first active structure, forming a first source-drain structure, a first interlayer dielectric layer and a first source-drain metal in sequence, the first interlayer dielectric layer wrapping the first active structure, the first source-drain structure and the first source-drain metal; flipping the semiconductor substrate and removing it; based on the second active structure, forming a second source-drain structure, a second interlayer dielectric layer and a second source-drain metal in sequence, the second interlayer dielectric layer wrapping the second active structure, the second source-drain structure and the second source-drain metal; wherein the first source-drain metal and the second source-drain metal are connected through an interconnection through-hole structure, and the interconnection through-hole structure runs through the first interlayer dielectric layer and the second interlayer dielectric layer.

In some possible embodiments, based on the first active structure, a first source-drain structure, a first interlayer dielectric layer and a first source-drain metal are formed in sequence, including: etching a portion of the first active structure to form the first source-drain structure; depositing semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; etching a first portion of the first interlayer dielectric layer to form a first source-drain metal; etching a second portion of the first interlayer dielectric layer to form a first interconnection through-hole structure, and the first interconnection through-hole structure is connected to the first source-drain metal.

In some possible embodiments, based on the second active structure, a second source-drain structure, a second interlayer dielectric layer, and a second source-drain metal are formed in sequence, including: etching a portion of the second active structure to form a second source-drain structure; depositing semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; etching a first portion of the second interlayer dielectric layer to form a second source-drain metal; etching a second portion of the second interlayer dielectric layer until it is connected to the first interconnection through-hole structure to form a second interconnection through-hole structure, and the second interconnection through-hole structure and the first interconnection through-hole structure constitute an interconnection through-hole structure.

In some possible embodiments, based on the first active structure, a first source-drain structure, a first interlayer dielectric layer and a first source-drain metal are formed in sequence, including: etching a portion of the first active structure to form the first source-drain structure; depositing semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; etching a third portion of the first interlayer dielectric layer to form a first source-drain metal.

In some possible embodiments, based on the second active structure, a second source-drain structure, a second interlayer dielectric layer and a second source-drain metal are formed in sequence, including: etching a portion of the second active structure to form a second source-drain structure; depositing semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; etching a third portion of the second interlayer dielectric layer to form a second source-drain metal; etching a fourth portion of the second interlayer dielectric layer until it penetrates the first interlayer dielectric layer to form an interconnected through-hole structure.

In some possible implementations, the interconnection via structure is located at one side of the active structure; or, the interconnection via structure is located at both sides of the active structure; or, the interconnection via structure is located in the middle of the active structure.

In some possible implementations, before flipping the wafer and removing the semiconductor substrate, the method further includes: forming a first transistor based on the first interlayer dielectric layer; and bonding the first transistor to the carrier wafer.

In some possible embodiments, after forming a second source-drain structure, a second interlayer dielectric layer, and a second source-drain contact structure in sequence based on the second active structure, the method further includes: forming a second transistor based on the second interlayer dielectric layer, and the second transistor is self-aligned with the first transistor in a vertical direction of the semiconductor substrate.

In the second aspect, an embodiment of the present application provides a self-aligned transistor, including: a first transistor; a second transistor, the second transistor being arranged back to back with the first transistor; wherein the first source and drain metal of the first transistor is connected to the second source and drain metal of the second transistor through an interconnection through-hole structure, and the interconnection through-hole structure passes through the first interlayer dielectric layer of the first transistor and the second interlayer dielectric layer of the second transistor.

In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a self-aligned transistor as described in the above embodiment.

In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

In the present application, the interconnection via structure in the self-aligned transistor is connected to the first source-drain metal and the second source-drain metal respectively, so that the interconnection between the first source-drain structure and the second source-drain structure can be realized;

Furthermore, since the interconnection via structure penetrates the first interlayer dielectric layer and the second interlayer dielectric layer, the etching can be stopped at the source-drain metal by selective etching, thereby reducing the difficulty of controlling the etching time in the source-drain interconnection scheme.

It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

FIG1 is a schematic diagram of a first implementation flow of a method for interconnecting source and drain of a self-aligned transistor in an embodiment of the present application;

FIG2 is a schematic diagram of a first structure of a self-aligned transistor in an embodiment of the present application;

FIG3 is a schematic diagram of a first structure of an interconnected through-hole structure in an embodiment of the present application;

4A to 4E are schematic diagrams of a first preparation process of a self-aligned transistor in an embodiment of the present application;

FIG5 is a schematic diagram of a second structure of a self-aligned transistor in an embodiment of the present application;

FIG6 is a schematic diagram of a second structure of an interconnected through-hole structure in an embodiment of the present application;

FIG7 is a schematic diagram of a third structure of a self-aligned transistor in an embodiment of the present application;

FIG8 is a schematic diagram of a fourth structure of a self-aligned transistor according to an embodiment of the present application;

FIG9 is a schematic diagram of a fifth structure of a self-aligned transistor in an embodiment of the present application;

FIG10 is a sixth structural schematic diagram of a self-aligned transistor in an embodiment of the present application;

The above pictures:

10. self-aligned transistor; 11. first transistor; 111. first active structure; 112. first source-drain structure; 113. first source-drain metal; 114. first interlayer dielectric layer; 115. first gate structure; 116. first spacer; 117. first metal interconnection layer; 12. second transistor; 121. second active structure; 122. second source-drain structure; 123. second source-drain metal; 124. second interlayer dielectric layer; 125. second gate structure; 126. second spacer; 127. second metal interconnection layer; 13. interconnection via structure; 131. first interconnection via structure; 132. second interconnection via structure; 14. shallow trench isolation layer; 15. first insulating layer; 16. carrier wafer; 21. semiconductor substrate; 22. fin structure; 23. shallow trench isolation structure; 241. first dummy gate structure; 242. second dummy gate structure.

Detailed ways

Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

As Moore's Law continues to deepen, after the technology node of gate-all-around FET (GAA), continuing to promote transistor size miniaturization is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve transistor integration density and circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

In one embodiment, there are two schemes for manufacturing processes of stacked transistors, the first is a monolithic scheme, and the second is a sequential scheme.

The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding a wafer on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, in the thermal process of processing the upper transistor, the temperature needs to be strictly controlled to avoid affecting the lower transistor and the interconnection line. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonded wafer; (3) There is an alignment error between the upper and lower transistors, and the photolithography accuracy is extremely high; (4) When solving the problem of source-drain interconnection between the upper and lower transistors, the etching time needs to be accurately controlled to ensure the depth of the source-drain contact metal of the lower transistor; (5) In the layout design, the position of the active structure (such as the fin structure) in the transistor is fixed, which will limit the width of the source-drain metal, resulting in a large resistance of the source-drain metal, which is not conducive to the performance of the circuit.

In order to solve the above technical problems, an embodiment of the present application provides a source-drain interconnection method of a self-aligned transistor to reduce the difficulty of controlling the etching time for manufacturing an interconnection through-hole structure.

In the embodiments of the present application, the self-aligned transistor can be applied to semiconductor devices such as memory and processor.

In one embodiment, the self-aligned transistor may include at least two transistors, for example, a first transistor and a second transistor. The first transistor and the second transistor are arranged opposite to each other. The first active structure in the first transistor and the second active structure in the second transistor are formed by the same process. In this case, it can be understood that the first transistor and the second transistor share the same active structure, and the first active structure and the second active structure are self-aligned.

In the embodiment of the present application, the first transistor and the second transistor in the self-aligned transistor may be transistors of the same type, such as any one of the following: a fin field effect transistor, a full-surround gate transistor, and a planar transistor.

FIG. 2 is a self-aligned transistor composed of fin field effect transistors. The preparation method provided in the embodiment of the present application will be described below in conjunction with the structure of the self-aligned transistor shown in FIG. 2 .

FIG. 1 is a schematic diagram of a first implementation flow of a method for interconnecting the source and drain of a self-aligned transistor in an embodiment of the present application. Referring to FIG. 1 , the method for interconnecting the source and drain of a self-aligned transistor may include:

S101, forming an active structure on a semiconductor substrate, wherein the active structure includes a first active structure and a second active structure.

Among them, the semiconductor substrate in the embodiment of the present application can be a silicon (Si) substrate, or a silicon-on-insulator (SOI) substrate. Of course, it can also be a substrate made of other semiconductor materials, and the embodiment of the present application does not make specific limitations on this.

It is understandable that when the type of the self-aligned transistor is different, the arrangement of the substrate is also different accordingly. For example, when the self-aligned transistor is a fin field effect transistor or a planar transistor, the semiconductor substrate can be a single-layer structure, that is, a substrate made of one semiconductor material; when the self-aligned transistor is a full-surround gate transistor, the semiconductor substrate can be a stacked structure, that is, a stacked layer obtained by stacking Si material and silicon germanium (SiGe) material.

In some embodiments, when the self-aligned transistor is a fin field effect transistor, the above S101 may include: etching the semiconductor substrate to form a plurality of fin structures; the upper half of the fin structure is a first active structure, and the lower half of the fin structure is a second active structure.

In other embodiments, when the self-aligned transistor is a full-surround gate transistor, the above S101 may include: etching the semiconductor substrate to form a columnar structure, wherein the semiconductor substrate is formed by alternately deposited silicon layers and silicon germanium layers; the upper half of the columnar structure is the first active structure, and the lower half of the columnar structure is the second active structure.

In some other embodiments, when the self-aligned transistor is a planar transistor, the above S101 may include: etching the semiconductor substrate to form a block structure; the upper half of the block structure is the first active structure, and the lower half of the block structure is the second active structure.

In the embodiment of the present application, since the self-aligned transistor includes two transistors (i.e., the first transistor and the second transistor), and the first active structure of the first transistor and the second active structure of the second transistor are formed by the same etching process, a larger etching depth can be used when etching the semiconductor substrate. For example, the height of the fin-shaped structure (which may also be a columnar structure or a block structure) obtained by etching can be greater than 100nm. It should be noted that the height of the fin-shaped structure can be set according to actual conditions, and the embodiment of the present application does not specifically limit this.

In some embodiments, after the active structure, the method may further include: filling oxide above the active structure to form a shallow trench isolation (STI) structure. The height of the shallow trench isolation structure is greater than the height of the active structure.

In the embodiment of the present application, the oxide forming the shallow trench isolation structure may be any one of the following: silicon nitride (SiN, Si ₃ N ₄ ), silicon dioxide (SiO ₂ ) or silicon oxycarbide (SiCO), etc.

In some embodiments, after forming the shallow trench isolation structure, the method may further include: performing a chemical-mechanical planarization (CMP) process on the shallow trench isolation structure.

In an embodiment of the present application, chemical mechanical planarization is performed on the shallow trench isolation structure, so that when the shallow trench isolation structure is subsequently etched, the corresponding corrosion depths of the shallow trench isolation structure in different areas are the same, thereby making the top heights of the exposed active structures the same.

In some embodiments, after forming the shallow trench isolation structure, the method may further include: removing a portion of the shallow trench isolation structure by etching to expose the first active structure.

It is understandable that in order to perform subsequent preparation of the first transistor on the first active structure, such as preparing the first source-drain structure, the upper half of the shallow trench isolation structure can be etched first to expose the first active structure for subsequent preparation processes.

It should be noted that the etching process mentioned in the embodiments of the present application may include any one of the following: dry etching, wet etching, reactive ion etching and chemical oxide removal process, which is not limited in the embodiments of the present application.

In the embodiment of the present application, the solvent used for etching the shallow trench isolation structure may be: DHF solution or BOE solution. The solvent used in the etching process in the embodiment of the present application may be selected according to actual conditions and is not limited to the above DHF solution or BOE solution.

In some embodiments, after the first active structure is exposed, ion implantation may be performed at the connection between the first active structure and the second active structure to form an electrical isolation layer, wherein the electrical isolation layer is used to electrically isolate the first active structure from the second active structure.

The ions implanted include P-type ions, N-type ions or oxygen ions. The P-type ions may be one of the following: boron (B), gallium (Ga), aluminum (Al). The N-type ions may be one of the following: phosphorus (P), arsenic (As), antimony (Sb).

S102 , based on the first active structure, sequentially forming a first source-drain structure, a first interlayer dielectric layer and a first source-drain metal, wherein the first interlayer dielectric layer wraps the first active structure, the first source-drain structure and the first source-drain metal.

It can be understood that the removal of the shallow trench isolation structure and the exposure of the first active structure can provide a gate region and a source-drain groove of the first transistor. A semiconductor material is deposited in the gate region of the first transistor to obtain a first pseudo-gate structure of the first transistor. A source-drain epitaxial growth is performed in the source-drain groove of the first transistor to obtain a first source-drain structure. A semiconductor material is deposited above the first active structure to obtain a first interlayer dielectric layer. A metal material is deposited above the first source-drain structure to obtain a first source-drain metal.

In some embodiments, the method of forming the first dummy gate structure may include: photolithographically opening a gate region of the first transistor, and depositing a semiconductor material (such as polysilicon) in the gate region to form the first dummy gate structure of the first transistor.

In some embodiments, after forming the first dummy gate structure, spacers may be formed on both sides of the first dummy gate structure.

In some possible embodiments, the above S102 may include: etching a portion of the first active structure to form a first source-drain structure; depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; etching a first portion of the first interlayer dielectric layer to form a first source-drain metal; etching a second portion of the first interlayer dielectric layer to form a first interconnection through-hole structure, and the first interconnection through-hole structure is connected to the first source-drain metal.

In some embodiments, etching a portion of the first active structure to form a first source-drain structure may include: removing a portion of the first active structure by etching to provide a source-drain groove of the first transistor. Using the spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the source-drain groove by selective epitaxial growth to fill the source-drain groove of the first transistor, and then forming the first source-drain structure on the strained material by a heavy doping process.

It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and/or the first drain electrode structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, the source-drain groove, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source electrode and/or drain electrode".

In some embodiments, depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer may include: depositing an insulating material (such as silicon dioxide (SiO ₂ )) above the first active structure and the first source-drain structure to form a first interlayer dielectric layer; the first interlayer dielectric layer may cover the first active structure and the first source-drain structure.

In some embodiments, etching a first portion of the first interlayer dielectric layer to form a first source-drain metal; etching a second portion of the first interlayer dielectric layer to form a first interconnection through-hole structure, wherein the first interconnection through-hole structure is connected to the first source-drain metal, may include: etching a portion of the first interlayer dielectric layer located above the first source-drain structure (i.e., the first portion of the first interlayer dielectric layer) until the upper surface of the first source-drain structure is exposed to form a first source-drain metal groove. A metal material is deposited in the first source-drain metal groove to obtain the first source-drain metal. Next, etching a portion of the first interlayer dielectric layer located on the side of the first source-drain groove (i.e., the second portion of the first interlayer dielectric layer), the etching depth may be lower than the epitaxy of the first source-drain structure, to form a slot-shaped hole, and depositing a metal material identical to the first source-drain metal in the slot-shaped hole to obtain the first interconnection through-hole structure.

It should be noted that the preparation order of first preparing the first source-drain metal and then preparing the first interconnection through-hole structure in the above embodiment is only an example, and the first interconnection through-hole structure can also be prepared first and then the first source-drain metal, or the first source-drain metal and the first interconnection through-hole structure can be prepared at the same time, and the embodiment of the present application does not specifically limit this. The prepared first source-drain metal and the first interconnection through-hole structure are connected to each other, and it can be understood that the first source-drain metal and the first interconnection through-hole structure are an integral structure.

In some other possible embodiments, during the process of preparing the first transistor, the first interconnection through-hole structure in the first transistor may not be prepared. Without preparing the first interconnection through-hole structure, the above S102 may include: etching a portion of the first active structure to form a first source-drain structure; depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; and etching a third portion of the first interlayer dielectric layer to form a first source-drain metal.

It should be noted that the process of forming the first source-drain structure, the first interlayer dielectric layer and the first source-drain metal is the same as that in the above embodiment, and will not be elaborated in the embodiment of the present application.

S103, flipping the wafer and removing the semiconductor substrate.

It is understandable that after forming the first source-drain structure, the first interlayer dielectric layer and the first source-drain metal, other structures in the first transistor can be prepared according to standard steps. After the first transistor is prepared, the first transistor is flipped and the semiconductor substrate is removed so that the second active structure is placed upward, which is convenient for the subsequent preparation of the second transistor.

In some embodiments, before S103, the method may further include: forming a first transistor based on the first interlayer dielectric layer; and bonding the first transistor to the carrier wafer.

It can be understood that a back-end process (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.) is performed on the first interlayer dielectric layer to form a first metal interconnect layer of the first transistor. An insulating material (such as silicon oxide) is deposited on the first metal interconnect layer to form a first insulating layer, and the first insulating layer is bonded to the carrier wafer.

In the embodiment of the present application, the bonded carrier wafer can provide physical support for the flipped first transistor after inversion, thereby effectively preventing the first transistor from being broken by external force during the preparation of the second transistor.

In some embodiments, before forming the first metal interconnect layer, the method may further include: removing the first dummy gate structure by etching to expose the gate region of the first transistor, and depositing metal material in the gate region of the first transistor to form a first gate structure of the first transistor.

In some embodiments, after removing the semiconductor substrate, the method may further include: removing a portion of the shallow trench isolation structure by etching to expose the second active structure.

It is understandable that in order to perform subsequent preparation of the second transistor on the second active structure, such as preparing a second source-drain structure, the lower half of the shallow trench isolation structure can be etched first to expose the second active structure for subsequent preparation processes.

It should be noted that when etching the lower half of the shallow trench isolation structure, a shallow trench isolation structure of a certain thickness may be retained, and the retained shallow trench isolation structure may be used to isolate the first transistor from the second transistor.

S104, based on the second active structure, a second source-drain structure, a second interlayer dielectric layer and a second source-drain metal are sequentially formed, and the second interlayer dielectric layer wraps the second active structure, the second source-drain structure and the second source-drain metal.

The first source-drain metal and the second source-drain metal are connected through an interconnection through-hole structure, and the interconnection through-hole structure penetrates the first interlayer dielectric layer and the second interlayer dielectric layer.

It can be understood that the removal of the shallow trench isolation structure and the exposure of the second active structure can provide a gate region and a source-drain groove of the second transistor. Semiconductor material is deposited in the gate region of the second transistor to obtain a second pseudo-gate structure of the second transistor. Source-drain epitaxial growth is performed in the source-drain groove of the second transistor to obtain a second source-drain structure. Semiconductor material is deposited above the second active structure to obtain a second interlayer dielectric layer. Metal material is deposited above the second source-drain structure to obtain a second source-drain metal.

In some embodiments, the method of forming the second dummy gate structure may include: photolithography to open the gate region of the second transistor, and depositing a semiconductor material (such as polysilicon) in the gate region to form a first dummy gate structure of the second transistor.

In some embodiments, after the second dummy gate structure is formed, spacers may be formed on both sides of the second dummy gate structure.

In some possible embodiments, the above S104 may include: etching a portion of the second active structure to form a second source-drain structure; depositing a semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; etching a first portion of the second interlayer dielectric layer to form a second source-drain metal; etching a second portion of the second interlayer dielectric layer until it is connected to the first interconnection through-hole structure to form a second interconnection through-hole structure, and the second interconnection through-hole structure and the first interconnection through-hole structure constitute an interconnection through-hole structure.

In some embodiments, etching a portion of the second active structure to form a second source-drain structure may include: removing a portion of the second active structure by etching to provide a source-drain groove of the second transistor. Using the spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the source-drain groove by selective epitaxial growth to fill the source-drain groove of the second transistor, and then forming the second source-drain structure on the strained material by a heavy doping process.

In some embodiments, depositing a semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer may include: depositing an insulating material (such as silicon dioxide) above the second active structure and the second source-drain structure to form a second interlayer dielectric layer; the second interlayer dielectric layer may cover the second active structure and the second source-drain structure.

It should be noted that the first interlayer dielectric layer and the second interlayer dielectric layer in the embodiment of the present application may be formed of the same material or different materials.

In some embodiments, etching the first portion of the second interlayer dielectric layer to form a second source-drain metal; etching the second portion of the second interlayer dielectric layer until it is connected to the first interconnection through-hole structure to form a second interconnection through-hole structure, wherein the second interconnection through-hole structure and the first interconnection through-hole structure form an interconnection through-hole structure, which may include: etching the portion of the second interlayer dielectric layer located above the second source-drain structure (i.e., the first portion of the second interlayer dielectric layer) until the upper surface of the second source-drain structure is exposed to form a second source-drain metal groove. A metal material is deposited in the second source-drain metal groove to obtain a second source-drain metal. Next, etching the portion of the second interlayer dielectric layer located on the side of the second source-drain groove (i.e., the second portion of the second interlayer dielectric layer), the second portion of the second interlayer dielectric layer is aligned with the second portion of the first interlayer dielectric layer, and etching is stopped when etching reaches a position connected to the first interconnection through-hole structure to form a slot-shaped hole, and a metal material identical to the second source-drain metal is deposited in the slot-shaped hole to obtain a second interconnection through-hole structure.

In the embodiment of the present application, since the first interconnected via structure is connected to the first source-drain metal, the second interconnected via structure is connected to the second source-drain metal, and the second interconnected via structure is connected to the first interconnected via structure, the first source-drain metal and the second source-drain metal are also interconnected.

It should be noted that the above-mentioned scheme for preparing the second interconnection through-hole structure corresponds to the above-mentioned scheme for preparing the first interconnection through-hole structure. The first interconnection through-hole structure and the second interconnection through-hole structure together constitute the interconnection through-hole structure in the self-aligned transistor, realizing the interconnection between the first source-drain metal and the second source-drain metal.

It should be noted that the preparation order of first preparing the second source-drain metal and then preparing the second interconnection through-hole structure in the above embodiment is only an example, and the second interconnection through-hole structure can also be prepared first and then the second source-drain metal, or the second source-drain metal and the second interconnection through-hole structure can be prepared at the same time, and the embodiment of the present application does not specifically limit this. The prepared second source-drain metal and the second interconnection through-hole structure are connected to each other, and it can be understood that the second source-drain metal and the second interconnection through-hole structure are an integral structure.

In some other possible embodiments, during the process of preparing the first transistor, the first interconnection through-hole structure in the first transistor may not be prepared. When the first interconnection through-hole structure is not prepared, the above S104 may include: etching a portion of the second active structure to form a second source-drain structure; depositing semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; etching a third portion of the second interlayer dielectric layer to form a second source-drain metal; and etching a fourth portion of the second interlayer dielectric layer until it penetrates the first interlayer dielectric layer to form an interconnection through-hole structure.

It should be noted that the process of forming the second source-drain structure, the second interlayer dielectric layer and the second source-drain metal is the same as that in the above embodiment, and will not be described in detail in the embodiment of the present application.

In some embodiments, etching the fourth portion of the second interlayer dielectric layer until penetrating the first interlayer dielectric layer to form an interconnection through-hole structure may include: etching the portion of the second interlayer dielectric layer located on the side of the second source-drain metal groove (i.e., the fourth portion of the second interlayer dielectric layer) until etching reaches the side of the first source-drain metal, stopping etching to form a slot-shaped hole, depositing the same metal material as the second source-drain metal in the slot-shaped hole to obtain an interconnection through-hole structure. The interconnection through-hole structure penetrates the first interlayer dielectric layer and the second interlayer dielectric layer.

In some possible implementations, the interconnection via structure is located at one side of the active structure; or, the interconnection via structure is located at both sides of the active structure; or, the interconnection via structure is located in the middle of the active structure.

It can be understood that for fin field effect transistors, the active structure is a plurality of fin structures, and the interconnection through-hole structure can be located on one side of the plurality of fin structures; it can also be located on both sides of the plurality of fin structures; when the intervals between the plurality of fin structures are large and the source and drain epitaxy are not fused together, the interconnection through-hole structure can be located between adjacent source and drain (it can also be understood that the interconnection through-hole structure can be located between the left fin structure and the right fin structure). For all-around gate transistors, the active structure is an interval-arranged nanosheet structure, and the interconnection through-hole structure can be located on one side of the nanosheet structure; it can also be located on both sides of the nanosheet structure. For planar transistors, the active structure is a block structure, and the interconnection through-hole structure can be located on one side of the block structure; it can also be located on both sides of the block structure.

In some other possible implementations, during layout design, the position of the active structure can be biased toward the left or right side of the self-aligned transistor so that the active structure is not located in the middle of the semiconductor substrate; on the other side (i.e., the right or left side), a wider interconnection via structure is formed.

In the embodiment of the present application, the position of the active structure is moved to one side, which can leave more space for the interconnection through-hole structure, increase the width of the interconnection through-hole structure, and thus reduce the resistance when the first source-drain metal and the second source-drain metal are interconnected.

In some possible implementations, after S104, the method may further include: forming a second transistor based on the second interlayer dielectric layer.

The second transistor is self-aligned with the first transistor in a vertical direction of the semiconductor substrate.

It can be understood that the post-process (such as interconnect line dielectric deposition, metal line formation, lead pad formation, etc.) is performed on the second interlayer dielectric layer to form the second metal interconnect layer of the second transistor. At this point, the second transistor in the self-aligned transistor is completed.

In some embodiments, before forming the second metal interconnect layer, the method may further include: removing the second dummy gate structure by etching to expose the gate region of the second transistor, and depositing metal material in the gate region of the second transistor to form a second gate structure of the second transistor.

In the embodiment of the present application, the metal material of the first gate structure and the second gate structure can be any one of the following: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN). The materials of the first gate structure and the second gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

In the embodiment of the present application, the materials of the first gate structure and the second gate structure can be made of the same or different metal materials according to actual conditions, and the embodiment of the present application does not specifically limit this.

In some embodiments, before preparing the first gate structure, the method may further include: depositing a semiconductor material on the surface of the first active structure to form a first gate dielectric layer of the first transistor, wherein the first gate dielectric layer is used to isolate the first active structure from the first gate structure.

In the embodiment of the present application, the method for preparing the second gate dielectric layer of the second transistor is the same as the method for preparing the first gate dielectric layer, which is not described in detail in the embodiment of the present application.

It should be noted that the materials used to prepare the first gate dielectric layer and the second gate dielectric layer may be the same or different, and this embodiment of the present application does not specifically limit this.

Below, taking the first transistor and the second transistor as fin field effect transistors as an example, the self-aligned transistor provided in the embodiment of the present application is described. Figure 2 is a schematic diagram of the first structure of the self-aligned transistor in the embodiment of the present application. Among them, (a) in Figure 2 is a top view of the self-aligned transistor. It should be noted that, for ease of understanding, only the fin structure, gate structure, and source-drain structure are shown in the top view; (b) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the source-drain structure (i.e., the A-A' direction); (c) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the gate structure (i.e., the B-B' direction).

As shown in FIG. 2 , the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of fin structures. The fin structure is divided into two parts, namely, the first part and the second part, the first part is used as the first active structure 111 in the first transistor 11, and the second part is used as the second active structure 121 in the second transistor 12. The first source-drain metal 113 in the first transistor 11 and the second source-drain metal 123 in the second transistor 12 are interconnected through an interconnection via structure 13. A shallow trench isolation layer 14 is provided between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used to isolate the first transistor 11 from the second transistor 12.

FIG3 is a schematic diagram of the first structure of the interconnection through-hole structure in the embodiment of the present application. FIG3 shows a disassembled schematic diagram of the interconnection through-hole structure 13, the first source-drain metal 113 and the second source-drain metal 123. Referring to FIG3, the interconnection through-hole structure 13 may include two parts, one part is the first interconnection through-hole structure 131, the first interconnection through-hole structure 131 is connected to the first source-drain metal 113; the other part is the second interconnection through-hole structure 132, the second interconnection through-hole structure 132 is connected to the second source-drain metal 123; the first interconnection through-hole structure 131 and the second interconnection through-hole structure 132 are connected.

It should be noted that the interconnection via structure 13 in FIG. 3 corresponds to the interconnection via structure 13 in the self-aligned transistor shown in FIG. 2 , and the interconnection via structure 13 in the embodiment of the present application may also be other structures.

In the embodiment of the present application, the first active structure 111 of the first transistor 11 and the second active structure 121 of the second transistor 12 are formed by the same etching process, so that the first transistor 11 and the second transistor 12 can be self-aligned.

The following describes the preparation process of the self-aligned transistor shown in Figure 2 in combination with the above preparation method. The self-aligned transistor shown in Figure 2 can be prepared by the process shown in Figures 4A to 4E, which are schematic diagrams of the first preparation process of the self-aligned transistor in the embodiment of the present application.

In one example, taking the first transistor 11 and the second transistor 12 as fin field effect transistors as an example, a first preparation process of the source-drain interconnected self-aligned transistor 10 may include the following steps:

The first step is to provide a semiconductor substrate 21 (eg, a Si substrate) (see (a) in FIG. 4A ).

Step 2: etching the semiconductor substrate 21 to form a plurality of fin structures 22 (see (b) in FIG. 4A ).

Step 3: Fill the fin-like structure 22 with oxide to form a shallow trench isolation structure 23 (see (c) in FIG. 4A ). The height of the shallow trench isolation structure 23 is greater than the height of the fin-like structure 22 and can cover multiple fin-like structures 22. Then, the shallow trench isolation structure 23 is subjected to chemical mechanical planarization.

Step 4: Using standard steps, a portion of the shallow trench isolation structure 23 is etched to expose the first portion of the fin structure 22 (ie, the first active structure 111 ) (see (a) in FIG. 4B ).

Step 5: Etch the first portion of the fin structure 22 to form source and drain grooves of the first transistor 11. Then, photolithography is performed to open the gate region of the first transistor 11, and polysilicon is deposited at the gate region to form a first dummy gate structure 241. First spacers 116 are formed on both sides of the first dummy gate structure 241 (see (b) in FIG. 4B ).

Step 6: epitaxially grow source and drain at the source and drain grooves of the first transistor 11 to form a first source and drain structure 112. Then, a semiconductor material is deposited on the first active structure 111 to form a first interlayer dielectric layer 114 (see (c) in FIG. 4B ).

Step 7: A portion of the first interlayer dielectric layer 114 is removed by etching to form a first source-drain metal groove, and a metal material is deposited in the first source-drain metal groove to form a first source-drain metal 113. Next, a first slot-shaped hole is formed on the side of the first source-drain metal 113 (i.e., the side of the source-drain epitaxy) by etching, and a metal material is deposited in the first slot-shaped hole to form a first interconnection through-hole structure 131, and the first interconnection through-hole structure 131 is connected to the first source-drain metal 113 (see (a) in FIG. 4C ).

Step 8: Remove the first dummy gate structure 241 and deposit metal in the gate region to form a first gate structure 115. Then, a back-end process is performed on the first interlayer dielectric layer 114 to form a first metal interconnect layer 117 (see FIG. 4C (b)).

Step 9: Deposit oxide on the first metal interconnect layer 117 to form a first insulating layer 15, and the first insulating layer 15 is bonded to the carrier wafer 16. Next, the first transistor 11 bonded to the carrier wafer 16 is flipped over so that the semiconductor substrate 21 is placed upward (see (c) in FIG. 4C ).

Step 10: The semiconductor substrate 21 is removed by etching, and the shallow trench isolation structure 23 is etched to expose the second portion of the fin structure 22 (see (a) in FIG. 4D ).

It should be noted that when etching the shallow trench isolation structure 23 , the etching depth is controlled to retain a certain thickness of the shallow trench isolation structure 23 to serve as the shallow trench isolation layer 14 . The shallow trench isolation layer 14 is used to isolate the first transistor 11 from the second transistor 12 .

Step 11: Form a second source-drain structure 122, a second dummy gate structure 242, a second spacer 126 and a second interlayer dielectric layer 124 on the second portion of the fin structure 22 (see (b) in FIG. 4D ) (see steps 5 and 6 for the specific preparation process).

Step 12: Remove a portion of the second interlayer dielectric layer 124 by etching to form a second source-drain metal groove, and deposit metal material in the second source-drain metal groove to form a second source-drain metal 123. The first source-drain metal 113 and the second source-drain metal 123 have the same shape and are arranged opposite to each other. Then, by etching, a second slot-shaped hole is formed on the side of the second source-drain metal 123 (aligned with the position of the first interconnection through-hole structure 131). When etching the second slot-shaped hole, the etching is stopped until the second slot-shaped hole is connected to the first slot-shaped hole. Metal material is deposited in the second slot-shaped hole to form a second interconnection through-hole structure 132, and the second interconnection through-hole structure 132 is connected to the second source-drain metal 123 (see (c) in FIG. 4D).

Step 13: forming a second gate structure 125 and a second metal interconnection layer 127 (the specific preparation process can refer to step 8) (see FIG. 4E ).

At this point, the self-aligned transistor 10 is prepared in which the first transistor 11 and the second transistor 12 are fin field effect transistors, and the first source-drain metal 113 and the second source-drain metal 123 are interconnected through the first interconnection via structure 131 and the second interconnection via structure 132 .

The interconnection through-hole structure 13 in the self-aligned transistor 10 shown in FIG. 2 is composed of two parts (i.e., the first interconnection through-hole structure 131 and the second interconnection through-hole structure 132). It can be understood that the interconnection through-hole structure 13 in the self-aligned transistor 10 shown in FIG. 2 is formed by two processes. In another embodiment, the interconnection through-hole structure 13 in the self-aligned transistor 10 can be formed by one process. FIG. 5 is a schematic diagram of the second structure of the self-aligned transistor in the embodiment of the present application. Among them, (a) in FIG. 5 is a top view of the self-aligned transistor. It should be noted that, for ease of understanding, only the fin structure, the gate structure, and the source-drain structure are shown in the top view; (b) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the source-drain structure (i.e., the A-A' direction); (c) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the gate structure (i.e., the B-B' direction).

As shown in FIG5 , the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of fin structures. The fin structure is divided into two parts, upper and lower, respectively, and is recorded as a first part and a second part. The first part is used as a first active structure 111 in the first transistor 11, and the second part is used as a second active structure 121 in the second transistor 12. The first source-drain metal 113 in the first transistor 11 and the second source-drain metal 123 in the second transistor 12 are interconnected through an interconnection through-hole structure 13. The interconnection through-hole structure 13 is located on one side of the active structure. The two ends of the interconnection through-hole structure 13 are connected to the first source-drain metal 113 and the second source-drain metal 123, respectively. A shallow trench isolation layer 14 is provided between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used to isolate the first transistor 11 and the second transistor 12.

FIG6 is a schematic diagram of a second structure of the interconnection via structure in the embodiment of the present application. FIG6 shows a disassembled schematic diagram of the interconnection via structure 13, the first source-drain metal 113, and the second source-drain metal 123. Referring to FIG6, the interconnection via structure 13 is led out from the second source-drain metal 123 and extends to the first source-drain metal 113. Both ends of the interconnection via structure 13 are connected to the first source-drain metal 113 and the second source-drain metal 123, respectively.

In the following, the preparation process of the self-aligned transistor shown in FIG. 5 is described in combination with the above preparation method.

The first step: providing a silicon substrate.

Step 2: Etch the silicon substrate to form multiple fin structures.

Step 3: forming a shallow trench isolation structure (for details, please refer to the third step in the first preparation process of the self-aligned transistor).

Step 4: Expose the first portion of the fin structure (ie, the first active structure) (for details, please refer to the fourth step in the first preparation process of the self-aligned transistor).

Step 5: forming a first dummy gate structure and a spacer (for details, please refer to the fifth step in the first preparation process of the self-aligned transistor).

Step 6: forming a first source-drain structure and a first interlayer dielectric layer (for details, please refer to the sixth step in the first preparation process of the self-aligned transistor).

Step 7: remove a portion of the first interlayer dielectric layer by etching to form a first source-drain metal groove, and deposit a metal material in the first source-drain metal groove to form a first source-drain metal.

Step 8: forming a first gate structure and a first metal interconnection layer (for details, please refer to the eighth step in the first preparation process of the self-aligned transistor).

Step 9: Flip the wafer, remove the semiconductor substrate, and expose the second portion of the fin structure (for details, please refer to the ninth and tenth steps in the first preparation process of the self-aligned transistor).

Step 10: forming a second source-drain structure, a second dummy gate structure, and a second interlayer dielectric layer on the second portion of the fin structure (for the specific preparation process, please refer to the fifth and sixth steps in the first preparation process of the aligned transistor).

Step 11: Remove a portion of the second interlayer dielectric layer by etching to form a second source-drain metal groove, and deposit metal material in the second source-drain metal groove to form a second source-drain metal. The first source-drain metal and the second source-drain metal have the same shape and are arranged opposite to each other. Then, a third slot-shaped hole is formed on the side of the second source-drain metal by etching. When etching the third slot-shaped hole, etching is stopped until the third slot-shaped hole contacts the first source-drain metal and the third slot-shaped hole penetrates the first interlayer dielectric layer. Metal material is deposited in the third slot-shaped hole to form an interconnected through-hole structure, and the two ends of the interconnected through-hole structure are respectively connected to the first source-drain metal and the second source-drain metal.

Step 12: Form a second gate structure and a second metal interconnection layer (for details, please refer to step 8 in the first preparation process of the self-aligned transistor).

At this point, the self-aligned transistor 10 is prepared, in which the first transistor 11 and the second transistor 12 are fin field effect transistors, and the first source-drain metal 113 and the second source-drain metal 123 are interconnected through the interconnection via structure 13 .

In some embodiments, FIG7 is a schematic diagram of the third structure of the self-aligned transistor in the embodiments of the present application. Among them, (a) in FIG7 is a top view of the self-aligned transistor. It should be noted that, for ease of understanding, the top view only shows the fin structure, the gate structure, and the source-drain structure; (b) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the source-drain structure (i.e., the A-A' direction); (c) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the gate structure (i.e., the B-B' direction).

As shown in FIG. 7 , the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of fin-shaped structures. In the A-A' direction, the positions of the plurality of fin-shaped structures are biased toward one side (such as the A side) of the semiconductor substrate. The fin-shaped structure is divided into two parts, which are respectively recorded as the first part and the second part. The first part is used as the first active structure 111 in the first transistor 11, and the second part is used as the second active structure 121 in the second transistor 12. The first source-drain metal 113 in the first transistor 11 and the second source-drain metal 123 in the second transistor 12 are interconnected through an interconnection through-hole structure 13. The two ends of the interconnection through-hole structure 13 are connected to the first source-drain metal 113 and the second source-drain metal 123, respectively. A shallow trench isolation layer 14 is provided between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used to isolate the first transistor 11 and the second transistor 12.

Referring to FIG. 7 and FIG. 2 , the interconnection via structure 13 in FIG. 7 is wider than the interconnection via structure 13 in FIG. 2 . This is because the active structure of the self-aligned transistor 10 shown in FIG. 7 is not arranged in the middle of the semiconductor substrate, but is biased to one side of the semiconductor substrate, and a larger space is reserved for the interconnection via structure 13. The increase in the width of the interconnection via structure 13 can reduce the resistance when the first source-drain structure 112 and the second source-drain structure 122 are interconnected.

In some embodiments, during the process of preparing the self-aligned transistor 10 shown in FIG. 7 , when etching the semiconductor substrate to form a fin-shaped structure, the etching position is controlled so that the position of the formed fin-shaped structure is biased toward one side of the semiconductor substrate, and a larger space is reserved on the other side of the semiconductor substrate for the subsequent preparation of the interconnection through-hole structure 13. When forming the interconnection through-hole structure 13, a slot-shaped hole with a larger diameter is etched, and then a metal material is deposited in the slot-shaped hole to form the interconnection through-hole structure 13. The preparation method of other structures in the self-aligned transistor 10 shown in FIG. 7 is the same as the preparation method of the self-aligned transistor 10 shown in FIG. 2 , and reference can be made to the first preparation process of the self-aligned transistor 10, which will not be described in detail in the present embodiment of the application.

In some embodiments, FIG8 is a schematic diagram of the fourth structure of the self-aligned transistor in the embodiments of the present application. Among them, (a) in FIG6 is a top view of the self-aligned transistor. It should be noted that, for ease of understanding, the top view only shows the fin structure, the gate structure, and the source-drain structure; (b) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the source-drain structure (i.e., the A-A' direction); (c) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the gate structure (i.e., the B-B' direction).

As shown in FIG8 , the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of fin structures. The fin structure is divided into two parts, which are respectively referred to as the first part and the second part. The first part is used as the first active structure 111 in the first transistor 11, and the second part is used as the second active structure 121 in the second transistor 12. The first source-drain metal 113 in the first transistor 11 and the second source-drain metal 123 in the second transistor 12 are interconnected through an interconnection through-hole structure 13. The interconnection through-hole structure 13 is located on both sides of the active structure, and the two ends of the interconnection through-hole structure 13 are respectively connected to the first source-drain metal 113 and the second source-drain metal 123. A shallow trench isolation layer 14 is provided between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used to isolate the first transistor 11 and the second transistor 12.

In some embodiments, during the process of preparing the self-aligned transistor shown in FIG8, when forming the interconnection through hole structure 13, slot-shaped holes are simultaneously etched on both sides of the active structure to form the interconnection through hole structures 13 located on both sides of the active structure. The preparation method of other structures in the self-aligned transistor 10 shown in FIG8 is the same as the preparation method of the self-aligned transistor 10 shown in FIG2, and reference may be made to the first preparation process of the self-aligned transistor 10, which will not be described in detail in the present embodiment of the application.

In some embodiments, FIG9 is a fifth structural schematic diagram of a self-aligned transistor in an embodiment of the present application. Among them, (a) in FIG9 is a top view of the self-aligned transistor. It should be noted that, for ease of understanding, the top view only shows the fin structure, the gate structure, and the source-drain structure; (b) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the source-drain structure (i.e., the A-A' direction); (c) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the gate structure (i.e., the B-B' direction).

As shown in FIG. 9 , the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of fin-shaped structures. The fin-shaped structure is divided into two parts, which are respectively referred to as the first part and the second part. The first part is used as the first active structure 111 in the first transistor 11, and the second part is used as the second active structure 121 in the second transistor 12. The first source-drain metal 113 in the first transistor 11 and the second source-drain metal 123 in the second transistor 12 are interconnected through an interconnection via structure 13. The interconnection via structure 13 is located in the middle of adjacent source-drain epitaxy (which can be understood as being located in the middle of a plurality of fin-shaped structures), and the two ends of the interconnection via structure 13 are respectively connected to the first source-drain metal 113 and the second source-drain metal 123. A shallow trench isolation layer 14 is provided between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used to isolate the first transistor 11 and the second transistor 12.

In some embodiments, during the process of preparing the self-aligned transistor 10 shown in FIG. 9 , when etching multiple fin structures on a semiconductor substrate, the spacing between the fin structures is increased, and when growing source and drain epitaxy, the source and drain epitaxy is not fused together, and a position for an interconnection via structure 13 is reserved in the middle of the multiple fin structures and the source and drain epitaxy. When forming the interconnection via structure 13, a slot-shaped hole is etched in the middle of the active structure to form an interconnection via structure 13 located in the middle of the active structure. The preparation method of other structures in the self-aligned transistor 10 shown in FIG. 9 is the same as the preparation method of the self-aligned transistor shown in FIG. 2 , and reference can be made to the first preparation process of the self-aligned transistor, which will not be described in detail in the present embodiment of the application.

In some embodiments, FIG10 is a sixth structural schematic diagram of a self-aligned transistor in an embodiment of the present application. Among them, (a) in FIG10 is a top view of the self-aligned transistor. It should be noted that, for ease of understanding, the top view only shows the nanosheet structure, the gate structure, and the source-drain structure; (b) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the source-drain structure (i.e., the A-A' direction); (c) is a cross-sectional view of the self-aligned transistor taken along the cross-sectional direction of the gate structure (i.e., the B-B' direction).

As shown in FIG. 10 , the self-aligned transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the self-aligned transistor 10 is a plurality of nanosheet structures. The nanosheet structure is divided into two parts, which are respectively referred to as the first part and the second part. The first part is used as the first active structure 111 in the first transistor 11, and the second part is used as the second active structure 121 in the second transistor 12. The first source-drain metal 113 in the first transistor 11 and the second source-drain metal 123 in the second transistor 12 are interconnected through an interconnection through-hole structure 13. The interconnection through-hole structure 13 is located on one side of the active structure, and the two ends of the interconnection through-hole structure 13 are respectively connected to the first source-drain metal 113 and the second source-drain metal 123. A shallow trench isolation layer 14 is provided between the first transistor 11 and the second transistor 12, and the shallow trench isolation layer 14 is used to isolate the first transistor 11 and the second transistor 12.

In some embodiments, during the process of preparing the self-aligned transistor 10 shown in FIG. 10, when etching the semiconductor substrate to form the nanosheet structure, the etching position is controlled so that the position of the formed nanosheet structure is biased toward one side of the semiconductor substrate, and a larger space is reserved on the other side of the semiconductor substrate for the subsequent preparation of the interconnection through-hole structure 13. When forming the interconnection through-hole structure 13, a slot-shaped hole with a larger diameter is etched, and then a metal material is deposited in the slot-shaped hole to form the interconnection through-hole structure 13. The preparation method of other structures in the self-aligned transistor 10 shown in FIG. 10 is the same as the preparation method of the self-aligned transistor 10 shown in FIG. 2, and reference can be made to the first preparation process of the self-aligned transistor 10, which will not be described in detail in the present embodiment of the application.

In the embodiment of the present application, the interconnection via structure 13 in the self-aligned transistor 10 penetrates the first interlayer dielectric layer 114 and the second interlayer dielectric layer 124 to realize the interconnection between the first source-drain structure 112 and the second source-drain structure 122;

Furthermore, since the interconnection through-hole structure 13 penetrates the first interlayer dielectric layer 114 and the second interlayer dielectric layer 124, the etching can be stopped at the source-drain metal by means of selective etching, thereby reducing the difficulty of controlling the etching time in the source-drain interconnection scheme;

Furthermore, the interconnection via structure 13 can be arranged at any of the following positions: one side of the active structure, both sides of the active structure, or the middle of the active structure, which makes the interconnection between the first source-drain structure 112 and the second source-drain structure 122 in the self-aligned transistor 10 more flexible.

Furthermore, the self-aligned transistor 10 provided in the embodiment of the present application can be inspected using an inspection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the self-aligned transistor 10 provided in the embodiment of the present application can be inspected by TEM slicing to inspect the interconnection between the first source-drain metal 113 and the second source-drain metal 123.

The present application provides a semiconductor device, including: a self-aligned transistor as described in the above embodiment. The specific definition of the self-aligned transistor can be found in the self-aligned transistors shown in Figures 2, 5, 7, 8, 9 and 10, which will not be described in detail here.

The embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as in the above embodiment, the semiconductor device being arranged on the circuit board. The semiconductor device includes the above self-aligned transistor. The specific definition of the self-aligned transistor can be referred to the self-aligned transistor shown in the above-mentioned Figures 2, 5, 7, 8, 9 and 10, which will not be described in detail here.

In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (11)

1. A method for interconnecting source and drain of a self-aligned transistor, characterized in that the method comprises: forming an active structure on a semiconductor substrate, the active structure comprising a first active structure and a second active structure; Based on the first active structure, a first source-drain structure, a first interlayer dielectric layer and a first source-drain metal are sequentially formed, wherein the first interlayer dielectric layer wraps the first active structure, the first source-drain structure and the first source-drain metal; Flipping and removing the semiconductor substrate; Based on the second active structure, a second source-drain structure, a second interlayer dielectric layer and a second source-drain metal are sequentially formed, wherein the second interlayer dielectric layer wraps the second active structure, the second source-drain structure and the second source-drain metal; The first source-drain metal and the second source-drain metal are connected via an interconnection through-hole structure, and the interconnection through-hole structure penetrates the first interlayer dielectric layer and the second interlayer dielectric layer. 2. The method according to claim 1, characterized in that the step of sequentially forming a first source-drain structure, a first interlayer dielectric layer and a first source-drain metal based on the first active structure comprises: Etching a portion of the first active structure to form the first source-drain structure; Depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; Etching a first portion of the first interlayer dielectric layer to form the first source and drain metal; A second portion of the first interlayer dielectric layer is etched to form a first interconnection via structure, wherein the first interconnection via structure is connected to the first source-drain metal. 3. The method according to claim 2, characterized in that the step of sequentially forming a second source-drain structure, a second interlayer dielectric layer, and a second source-drain metal based on the second active structure comprises: Etching a portion of the second active structure to form the second source-drain structure; Depositing a semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; Etching a first portion of the second interlayer dielectric layer to form a second source/drain metal; The second portion of the second interlayer dielectric layer is etched until it is connected with the first interconnection through-hole structure to form a second interconnection through-hole structure, wherein the second interconnection through-hole structure and the first interconnection through-hole structure constitute the interconnection through-hole structure. 4. The method according to claim 1, characterized in that the step of sequentially forming a first source-drain structure, a first interlayer dielectric layer and a first source-drain metal based on the first active structure comprises: Etching a portion of the first active structure to form the first source-drain structure; Depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; A third portion of the first interlayer dielectric layer is etched to form the first source/drain metal. 5. The method according to claim 4, characterized in that the step of sequentially forming a second source-drain structure, a second interlayer dielectric layer, and a second source-drain metal based on the second active structure comprises: Etching a portion of the second active structure to form the second source-drain structure; Depositing a semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; Etching a third portion of the second interlayer dielectric layer to form a second source and drain metal; The fourth portion of the second interlayer dielectric layer is etched until penetrating the first interlayer dielectric layer to form the interconnection through-hole structure. 6. The method according to claim 1, characterized in that The interconnection via structure is located on one side of the active structure; or, The interconnecting via structures are located on both sides of the active structure; or, The interconnect via structure is located in the middle of the active structure. 7. The method according to claim 1, characterized in that before flipping and removing the semiconductor substrate, the method further comprises: Based on the first interlayer dielectric layer, forming a first transistor; The first transistor is bonded to a carrier wafer. 8. The method according to claim 7, characterized in that after sequentially forming a second source-drain structure, a second interlayer dielectric layer, and a second source-drain contact structure based on the second active structure, the method further comprises: A second transistor is formed based on the second interlayer dielectric layer, and the second transistor is self-aligned with the first transistor in a vertical direction of the semiconductor substrate. 9. A self-aligned transistor, comprising: a first transistor; a second transistor, the second transistor being arranged opposite to the first transistor; The first source-drain metal of the first transistor is connected to the second source-drain metal of the second transistor through an interconnection via structure, and the interconnection via structure penetrates the first interlayer dielectric layer of the first transistor and the second interlayer dielectric layer of the second transistor. 10 . A semiconductor device, comprising: the self-aligned transistor according to claim 9 . 11 . An electronic device, comprising: a circuit board and the semiconductor device according to claim 10 , wherein the semiconductor device is arranged on the circuit board.