CN117878061A - Preparation method of stacked transistor, device and equipment - Google Patents

Preparation method of stacked transistor, device and equipment Download PDF

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Publication number
CN117878061A
CN117878061A CN202410177683.1A CN202410177683A CN117878061A CN 117878061 A CN117878061 A CN 117878061A CN 202410177683 A CN202410177683 A CN 202410177683A CN 117878061 A CN117878061 A CN 117878061A
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gate
transistor
source
drain
forming
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吴恒
彭莞越
卢浩然
黎明
黄如
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Peking University
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Peking University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application provides a preparation method of a stacked transistor, the stacked transistor, a device and equipment. The preparation method comprises the following steps: forming an active structure on the substrate structure, the active structure including a first portion and a second portion, the first portion being closer to the substrate structure than the second portion; forming a first transistor based on the first part of the active structure, wherein the first transistor comprises a first grid structure wrapping the first part and first source-drain structures positioned on two sides of the first grid structure; forming a gate isolation dielectric layer on the first gate structure; forming a second gate structure of the second transistor on the gate isolation dielectric layer based on the second portion of the active structure; the first grid structure is isolated from the second grid structure through a grid isolation medium layer.

Description

Preparation method of stacked transistor, device and equipment
Technical Field
The present disclosure relates to the field of integrated semiconductors, and more particularly, to a method for manufacturing a stacked transistor, a device, and an apparatus.
Background
While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. The stacked transistor (stacked transistors) achieves further enhancement of transistor integration density by integrating two or more layers of transistors in a vertical space, which is one of the important technologies for continuing the miniaturization of integrated circuit dimensions.
When the stacked transistors (including the first transistor and the second transistor) are manufactured by adopting the conventional scheme, the first gate structure in the first transistor and the second gate structure in the second transistor are formed at the same time, and the first gate structure and the second gate structure are directly contacted, so that the gate isolation between the upper layer transistor and the lower layer transistor is difficult to realize.
Disclosure of Invention
The application provides a preparation method of a stacked transistor, the stacked transistor, a device and equipment, and gate isolation between upper and lower layers of transistors is achieved.
In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, including: forming an active structure on the substrate structure, the active structure including a first portion and a second portion, the first portion being closer to the substrate structure than the second portion; forming a first transistor based on the first part of the active structure, wherein the first transistor comprises a first grid structure wrapping the first part and first source-drain structures positioned on two sides of the first grid structure; forming a gate isolation dielectric layer on the first gate structure; forming a second gate structure of the second transistor on the gate isolation dielectric layer based on the second portion of the active structure; the first grid structure is isolated from the second grid structure through a grid isolation medium layer.
In some possible embodiments, after forming the first transistor based on the first portion of the active structure, the method further comprises: gate cutting is conducted on the first gate structure to form a first gate cutting groove; filling a first insulating material in the first gate cutting groove to form a first gate cutting structure; forming a gate isolation dielectric layer on the first gate structure, comprising: and depositing a second insulating material on the first gate structure and the first gate cutting structure to form a gate isolation dielectric layer.
In some possible implementations, after forming the second gate structure of the second transistor on the gate isolation dielectric layer based on the second portion of the active structure, the method further includes: gate cutting is conducted on the second gate structure to form a second gate cutting groove; and filling a third insulating material in the second gate cutting groove to form a second gate cutting structure.
In some possible embodiments, the active structure further comprises: a sacrificial layer located between the first portion and the second portion; forming a first transistor based on a first portion of the active structure, comprising: removing the second portion of the active structure and the sacrificial layer in the source drain region of the stacked transistor; forming a first source drain structure based on the first portion of the active structure; forming a first source drain metal on the first source drain structure; the method further comprises the steps of: epitaxially growing a second source-drain structure on the first source-drain metal, the second portion being surrounded by the second gate structure; and forming a second source-drain metal on the second source-drain structure.
In some possible embodiments, after forming the first source-drain metal on the first source-drain structure, the method further comprises: and depositing a fourth insulating material on the first source-drain metal to form a source-drain isolation dielectric layer, wherein the first source-drain metal is isolated from the second source-drain structure through the source-drain isolation dielectric layer.
In some possible embodiments, the method further comprises: embedding a first power rail and a second power rail in the substrate structure, wherein the first power rail and the second power rail are respectively arranged at two sides of the active structure; after forming the first source-drain structure based on the first portion of the active structure, the method further comprises: forming a first power rail connection metal on the first power rail, the first power rail connection metal being connected with a first source metal of the first source drain metals; after epitaxially growing a second source-drain structure on the first source-drain metal, the second portion surrounded by the second gate structure, the method further comprises: and forming a second power rail connection metal on the second power rail, wherein the second power rail connection metal is connected with a second source electrode metal in the second source electrode and drain electrode metals.
In some possible embodiments, before forming the first source-drain structure based on the first portion of the active structure, the method further comprises: depositing a first semiconductor material at the intersection of the source-drain region and the gate region of the stacked transistor to form a protective layer covering the second portion of the active structure and the sacrificial layer; after forming the first source-drain structure based on the first portion of the active structure, the method further comprises: and removing the protective layer.
In some possible embodiments, forming an active structure on a substrate structure includes: providing a wafer, and sequentially depositing a first material layer and a second material layer on the wafer; etching the second material layer, the first material layer and the first part of the wafer, wherein the etched first material layer forms a sacrificial layer, and the etched second material layer forms a second part of the active structure; an oxide material is deposited on the second portion of the wafer to form a first shallow trench isolation structure, the first shallow trench isolation structure having a height that is less than a height of the first portion of the wafer, the first portion of the wafer not being surrounded by the first shallow trench isolation structure forming a first portion of the active structure.
In some possible embodiments, after forming the active structure on the substrate structure, the method further comprises: etching first shallow trench isolation structures and first areas of the wafer which are positioned on two sides of the active structure to form a first groove and a second groove; filling second metal materials in the first groove and the second groove to form a first power rail and a second power rail, wherein the heights of the first power rail and the second power rail are smaller than those of the first shallow trench isolation structure; oxide material is deposited on the first power rail and the second power rail to form a second shallow trench isolation structure, and the height of the second shallow trench isolation structure is the same as that of the first shallow trench isolation structure.
In a second aspect, embodiments of the present application provide a stacked transistor fabricated using a fabrication method as described in the first aspect and any of the embodiments thereof, including: a first transistor; a second transistor, the first transistor and the second transistor being stacked; and the grid isolation medium layer is used for isolating the first grid structure of the first transistor from the second grid structure of the second transistor through the grid isolation medium layer.
In a third aspect, embodiments of the present application provide a semiconductor device, including: a stacked transistor as described in the second aspect above.
In a fourth aspect, embodiments of the present application provide an electronic device, including: a circuit board and the semiconductor device according to the third aspect, the semiconductor device being provided to the circuit board.
The technical scheme that this application provided can include following beneficial effect:
in the embodiment of the application, by forming the active structure on the substrate structure, forming the first transistor based on the first part of the active structure, which is closer to the substrate structure, then forming the gate isolation dielectric layer on the first gate structure of the first transistor, and then forming the second gate structure of the second transistor based on the second part of the active structure on the gate isolation dielectric layer, the stacked transistor with gate isolation between the upper and lower transistors can be independently formed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing a stacked transistor according to an embodiment of the present application;
FIGS. 2A-2D are four design layouts of stacked transistors in an embodiment of the present application;
fig. 3 is a schematic diagram of a first structure of a stacked transistor according to an embodiment of the present application;
fig. 4 to 30 are schematic structural views of stacked transistors in the first manufacturing process according to the embodiment of the present application;
fig. 31 to 32 are schematic structural views of stacked transistors in a second manufacturing process according to embodiments of the present application;
fig. 33 is a schematic diagram of a second structure of a stacked transistor according to an embodiment of the present application;
fig. 34 is a schematic diagram of a third structure of a stacked transistor according to an embodiment of the present application;
fig. 35 is a schematic diagram of a fourth structure of a stacked transistor in an embodiment of the present application.
The figures above:
10. stacking transistors; 11. a first transistor (bottom transistor); 111. a first portion of the fin structure (active structure); 112. a first source drain structure; 113. a first source drain metal; 114. a first power rail; 115. the first power rail is connected with metal; 116. a first gate structure; 117. a first gate cut-off structure; 12. a gate isolation dielectric layer; 13. a second transistor (top-layer transistor); 131. a second portion of the fin structure; 132. a second source drain structure; 133. a second source drain metal; 134. a second power rail; 135. the second power rail is connected with the metal; 136. a second gate structure; 137. a second gate cut-off structure; 21. a substrate; 22. a first material layer; 23. a second material layer; 24. a sacrificial layer; 25. a first shallow trench isolation structure; 26. a first groove; 27. a second groove; 28. shallow trench isolation structures; 29. a dummy gate structure; 30. a first spacer; 31. a second spacer; 32. a protective layer; 33. a first interlayer dielectric layer; 34. a source-drain isolation dielectric layer; 35. a second interlayer dielectric layer; 36. a gate structure; 37. a gate cut-off structure; 38. and a metal interconnection layer.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application.
While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits.
In one embodiment, the fabrication process of the stacked transistor has two schemes, the first is a monolithic scheme and the second is a sequential scheme.
In the first approach, N-channel field effect transistors (N field effect transistors, NFET) and P-channel field effect transistors (P field effect transistors, PFET) are fabricated on the same substrate, and wafer bonding techniques are not employed. This determines that the same layer transistors must be of the same type, i.e., NFET or PFET. And the transistors on the upper layer and the lower layer are strictly in the same plane space, and no alignment deviation exists. The advantage of this solution is a better integration density. Drawbacks of this approach include the following two points: (1) The process is complex, and a large number of process technologies need to be developed and optimized; (2) Each layer of transistors has a fixed polarity, and two layers of transistors must be relied upon to form a basic Complementary Metal Oxide Semiconductor (CMOS) circuit, which has poor design flexibility.
The second scheme is based on wafer bonding and layer-by-layer processing. Specifically, the two transistors are stacked vertically by bonding a wafer on top of the fabricated lower transistor to prepare the upper transistor. However, this approach requires tight temperature control during the thermal process of processing the upper layer transistors, avoiding affecting the lower layer transistors and the interconnect lines. The scheme has the advantages that the device structure, the channel crystal orientation and even the channel material adopted by the upper layer transistor and the lower layer transistor can be correspondingly optimized to obtain better and more matched device performance due to wafer bonding. This solution currently presents the following technical challenges: (1) preparation of a high-quality upper transistor active layer; (2) thinning and defect control of the upper bonded wafer; (3) The upper and lower layer transistors have alignment errors and have extremely high requirements on photoetching precision.
At present, in the preparation process of the stacked transistor, the gate structures of the upper layer transistor and the lower layer transistor are formed simultaneously, and the gate structures of the upper layer transistor and the lower layer transistor are directly contacted, so that different gate structures are difficult to realize. Also, the gate structures between the plurality of stacked transistors are also isolated by providing a gate cut structure in the adjacent gate region between the two stacked transistors. In the current manufacturing scheme, the gate cut-off structure between the plurality of stacked transistors is also formed on the upper and lower transistors at the same time, which makes it impossible to realize different isolation modes in the stacked transistors, thereby affecting the flexibility of the stacked transistors in circuit design.
Based on the above-mentioned problems, the embodiments of the present application provide a method for manufacturing a stacked transistor, which can achieve flexibility in circuit design of the stacked transistor.
In the embodiment of the application, the stacked transistor can be applied to a semiconductor device such as a memory, a processor and the like.
In an embodiment, the stacked transistor may include at least two transistors, for example, a first transistor and a second transistor, the first transistor and the second transistor being stacked, the first transistor being formed based on a first portion of the active structure, the second transistor being formed based on a second portion of the active structure, and the first portion and the second portion of the active structure being formed through the same process, so it can be understood that the first transistor is self-aligned with the second transistor. Furthermore, the first gate structure in the first transistor is isolated from the second gate structure in the second transistor by a gate isolation dielectric layer, i.e., there is isolation between the gate structures of the upper and lower transistors in the stacked transistor.
In an embodiment of the present application, the first transistor and the second transistor in the stacked transistor may be transistors of the same type, and the types of the transistors may include, but are not limited to: fin field effect transistors, fully surrounding gate transistors and planar transistors, etc.
Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing a stacked transistor according to an embodiment of the present application, and as shown in fig. 1, the method for manufacturing a stacked transistor includes the following steps.
S110: an active structure is formed on a substrate structure.
Wherein the active structure includes a first portion and a second portion, the first portion being closer to the substrate structure than the second portion.
In some embodiments, the active structure may be formed by depositing a semiconductor material on the substrate structure and etching the semiconductor material.
Wherein the substrate structure may include, but is not limited to: silicon (Si) substrates, silicon-on-insulator (SOI) substrates, fully depleted silicon-on-insulator (FDSOI) substrates, stacked substrates formed by alternating deposition of silicon and silicon germanium (SiGe), and the like. The semiconductor material forming the active structure may be selected according to practical requirements, such as a silicon material, a silicon germanium material, etc., which is not particularly limited in the embodiments of the present application. The implementation process of forming the active structure on the substrate structure at S110 is described in detail later.
It will be appreciated that by forming the active structure on the substrate structure, it is possible to realize the formation of transistors stacked on top of each other based on the active structure in a subsequent step.
Illustratively, when the transistors in the stacked transistor are fin field effect transistors, the active structure is a fin structure; when the transistors in the stacked transistors are all-around gate transistors, the active structure is a nano-sheet structure; when the transistors in the stacked transistor are planar transistors, the active structure is a bulk structure.
When the types of stacked transistors are different, the arrangement of the active structures is correspondingly different. For example, when the stacked transistor is a fin field effect transistor or a planar transistor, the active structure may be a structure made using one semiconductor material; when the stacked transistor is a fully-around gate transistor, the active structure may be a stacked structure made of a plurality of semiconductor materials, for example, a stacked layer obtained by stacking a silicon material and a silicon germanium material.
In an embodiment of the present application, the active structure includes a first portion and a second portion, the first portion being closer to the substrate structure than the second portion, the first portion and the second portion being formed in a same process, such that a first transistor formed based on the first portion is self-aligned with a second transistor formed based on the second portion.
In forming the active structure, a larger etching depth may be used, i.e., the height of the active structure may be a larger value, e.g., the height of the etched fin structure is greater than 100 nanometers (nm). It should be noted that the height of the active structure may be set according to practical situations, which is not specifically limited in the embodiments of the present application.
In some embodiments, the implementation procedure of S110 may be: providing a wafer, and sequentially depositing a first material layer and a second material layer on the wafer; etching the second material layer, the first material layer and the first part of the wafer, wherein the etched first material layer forms a sacrificial layer, and the etched second material layer forms a second part of the active structure; an oxide material is deposited on the second portion of the wafer to form a first shallow trench isolation structure, the first shallow trench isolation structure having a height that is less than a height of the first portion of the wafer, the first portion of the wafer not being surrounded by the first shallow trench isolation structure forming a first portion of the active structure.
It will be appreciated that the first material layer and the second material layer may be formed by sequentially depositing the first material and the second material on the wafer, respectively. The second material layer, the first material layer and the first portion of the wafer are etched by an etching process, wherein the etched first material layer forms a sacrificial layer and the etched second material layer forms a second portion of the active structure. The first shallow trench isolation structure may then be formed by depositing an oxide material on the non-etched second portion of the wafer, and the first shallow trench isolation structure may have a height that is less than a height of the first portion of the wafer such that the first shallow trench isolation structure only partially encapsulates the first portion of the wafer, the portion of the first portion of the wafer that is not encapsulated by the first shallow trench structure forming a first portion of the active structure.
Wherein the first material is different from the material used for the wafer, and the second material is different from the first material.
In an example, the wafer may be a silicon wafer, the first material may be a silicon germanium material, and the second material may be a silicon material, i.e., the first and second portions of the active structure may be formed of a silicon material, and the sacrificial layer may be formed of a silicon germanium material.
Illustratively, the oxide material may include, but is not limited to: silicon dioxide (SiO 2) or silicon oxycarbide (SiCO).
It should be noted that, the etching process mentioned in the embodiments of the present application may include any of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal processes, to which embodiments of the present application are not limited.
In some embodiments, after etching the second material layer, the first material layer, and the first portion of the wafer, an oxide material is deposited on the remaining second portion of the wafer and the oxide material is thinned to form a first shallow trench isolation structure having a height that is less than a height of the first portion of the wafer. The process of the thinning treatment may be, for example, chemical-mechanical planarization (CMP), which is not limited in the embodiment of the present application.
In some embodiments, after the active structure is formed on the substrate structure, the first power rail and the second power rail may be buried in the substrate structure, and the first power rail and the second power rail are disposed on two sides of the active structure, respectively. In this way, the stacked transistor may be subsequently powered by connecting the power rail with the source structure of the stacked transistor.
In some embodiments, after forming the active structure on the substrate structure, the first shallow trench isolation structures and the first region of the wafer on both sides of the active structure may be etched to form a first recess and a second recess; filling second metal materials in the first groove and the second groove to form a first power rail and a second power rail, wherein the heights of the first power rail and the second power rail are smaller than those of the first shallow trench isolation structure; oxide material is deposited on the first power rail and the second power rail to form a second shallow trench isolation structure, and the height of the second shallow trench isolation structure is the same as that of the first shallow trench isolation structure.
The grooves used for filling the power supply rail can be etched on two sides of the first shallow trench isolation structure and the second part of the wafer through a photoetching process, and then the grooves are filled with a second metal material to form the power supply rail. An oxide material is then filled over the power rails until it is level with the previously formed first shallow trench isolation structures. The grooves include a first groove and a second groove, and the power rails include a first power rail and a second power rail, respectively.
Illustratively, the second metallic material may include, but is not limited to: titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta), or molybdenum (Mo), to which the present embodiments are not limited.
In some embodiments, after forming the power rail, a second semiconductor material may also be deposited within the gate region of the stacked transistor to form a dummy gate structure. Thus, a dummy gate structure common to the upper and lower transistors can be formed on the peripheral side of the active structure.
In one embodiment, the semiconductor material forming the dummy gate structure may be polysilicon, amorphous silicon, or the like.
In some embodiments, after forming the dummy gate structure, a first spacer (spacer) may be formed on both sides of the dummy gate structure, the first spacer being used to isolate the second gate structure from the second source drain structure.
Here, the structure of the first spacer may be set according to actual requirements, which is not specifically limited in the embodiment of the present application.
Illustratively, the first spacer may have a single layer structure, and be entirely made of the same material, such as porous carbon silicon oxide (SiCOH).
S120: a first transistor is formed based on the first portion of the active structure.
The first transistor comprises a first grid structure wrapping the first part and first source-drain structures positioned on two sides of the first grid structure.
In some embodiments, the implementation procedure of S120 may be: removing the second portion of the active structure and the sacrificial layer in the source drain region of the stacked transistor; forming a first source drain structure based on the first portion of the active structure; and forming a first source-drain metal on the first source-drain structure.
In S110, after etching the second material layer, the first material layer, and the first portion of the wafer, the etched first material layer forms a sacrificial layer, that is, the sacrificial layer is located between the first portion and the second portion of the active structure.
To facilitate the subsequent formation of the source and drain regions of the second transistor, the sacrificial layer of the source and drain regions and the second portion of the active structure are removed first, and the source and drain structure of the first transistor is formed over the first portion of the active structure. A first source-drain structure is then epitaxially grown over the first portion of the active structure and a first source-drain metal is formed over the first source-drain structure.
In some embodiments, after forming the first source-drain structure, an interlayer dielectric may be further deposited on the first source-drain structure, and the interlayer dielectric may be thinned to a top layer of the first source-drain structure, so as to form a first interlayer dielectric layer, and then a first source-drain metal may be formed in the first interlayer dielectric layer.
It should be noted that, the first source-drain structure, the first source-drain metal and the first interlayer dielectric layer may be formed by standard steps of the semiconductor manufacturing process, which is not specifically limited in this embodiment of the present application.
Illustratively, a source-drain recess may be formed in a first portion of the exposed active structure, and a source-drain epitaxial growth may be performed in the source-drain recess to obtain a first source-drain structure. And depositing a semiconductor material on the peripheral side of the first source-drain structure to obtain a first interlayer dielectric layer. And depositing a first metal material on the first source-drain structure to obtain a first source-drain metal.
Illustratively, a portion of the active structure is removed by etching, a source-drain recess of the first transistor may be provided, a strained material such as silicon germanium or silicon carbide is formed in the source-drain recess by selective epitaxial growth to fill the source-drain recess of the first transistor, and then the first source-drain structure is formed on the strained material by a heavy doping process.
It should be noted that, for convenience of description, the first source-drain structure in the embodiments of the present application is referred to simply as a first source structure and/or a first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, the source-drain groove and the like are similar to those of the first source-drain structure, wherein 'source-drain' is abbreviated as 'source electrode and/or drain electrode'.
In addition, a first power rail and a second power rail are buried in the substrate structure in S110, and the first power rail and the second power rail are disposed at both sides of the active structure to supply power to the stacked transistors. Based on this, in some embodiments, after forming the first source-drain structure based on the first portion of the active structure, a first power rail connection metal may also be formed on the first power rail, the first power rail connection metal being connected with a first source metal of the first source-drain metal.
It is understood that one end of the first power rail connection metal is connected to the first source metal of the first source drain metals, and the other end is connected to the first power rail, so that the first power rail can supply power to the first transistor through the first power rail connection metal.
In an example, the forming of the first source drain metal on the first source drain structure and the forming of the first power rail connection metal on the first power rail may be performed simultaneously, and a metal material of the first source drain metal and a metal material of the first power rail connection metal may be the same.
In some embodiments, a first semiconductor material may also be deposited at the intersection of the source-drain region and the gate region of the stacked transistor prior to forming the first source-drain structure of the first transistor to form a protective layer covering the second portion of the active structure and the sacrificial layer.
It will be appreciated that only a second portion of the active structure of the source drain region is removed, while a second portion of the active structure of the gate region remains for later use in self-aligned formation of a second source drain structure in a fabrication step of the second transistor. At this time, the second portion of the active structure and the sacrificial layer may be covered by depositing a first semiconductor material at an intersection of the source drain region and the gate region, and the first semiconductor material may form a protective layer that interfaces with the second portion of the active structure of the gate region and the sacrificial layer of the gate region.
Here, the protective layer may form a protection for the second portion of the active structure and the sacrificial layer. The protective layer may prevent the second source drain structure from being epitaxially grown in advance on the second portion of the active structure of the gate region if a process for epitaxially growing the first source drain structure based on the first portion of the active structure is employed.
The first semiconductor material forming the protective layer may be, for example, silicon nitride (SiN, si3N 4) or the like, which is not limited in the embodiment of the present application.
Based on this, in an embodiment, the protection layer may also be removed after forming the first source drain structure based on the first portion of the active structure.
It will be appreciated that by removing the protective layer, the second portion of the active structure of the gate region and the sacrificial layer of the gate region may be re-exposed, thereby facilitating the formation of the second transistor based on the second portion of the active structure in a subsequent step.
In some embodiments, after forming the first source-drain metal on the first source-drain structure, a fourth insulating material may be further deposited on the first source-drain metal to form a source-drain isolation dielectric layer, where the first source-drain metal is isolated from the source-drain structure of the second transistor by the source-drain isolation dielectric layer.
It will be appreciated that the first transistor is to be isolated from the second transistor in the source drain region, and therefore, after the structure of the source drain region of the first transistor is completed, a fourth insulating material may be deposited on the first source drain metal and the first power rail connection metal of the first transistor to form a source drain isolation dielectric layer, and then the structure of the source drain region of the second transistor is prepared on the source drain isolation dielectric layer.
The fourth insulating material for forming the source-drain isolation dielectric layer may be any one of the following materials: silicon nitride (SiN, si) 3 N 4 ) Silicon dioxide (SiO) 2 ) Or silicon oxycarbide (SiCO), and the like.
In addition, since the sacrificial layer of the source drain region and the second portion of the active structure are removed in the above operation, the following operation can be performed on this basis; epitaxially growing a second source-drain structure on the second portion surrounded by the second gate structure on the source-drain isolation dielectric layer; and forming a second source-drain metal on the second source-drain structure.
In some embodiments, after forming the second source-drain structure, an interlayer dielectric may be further deposited on the second source-drain structure, and the interlayer dielectric may be thinned to a top layer of the second source-drain structure to form a second interlayer dielectric layer, and then a second source-drain metal may be formed in the second interlayer dielectric layer.
Also, in some embodiments, after forming the second source-drain structure, a second power rail connection metal may also be formed on the second power rail, the second power rail connection metal being connected to a second source metal of the second source-drain metals. Here, one end of the second power rail connection metal is connected to the second source metal of the second source drain metals, and the other end is connected to the second power rail, so that the second power rail can supply power to the second transistor through the second power rail connection metal.
The second source-drain structure, the second interlayer dielectric layer, the second source-drain metal and the second power rail connection metal of the second transistor are prepared in the same manner as the first source-drain structure, the first interlayer dielectric layer, the first source-drain metal and the first power rail connection metal of the first transistor, and are not described herein.
It should be noted that, since the second source-drain structure is epitaxially grown based on the second portion of the active structure, the first source-drain structure is formed based on the first portion of the active structure, and the first portion and the second portion of the active structure are self-aligned structures, the second source-drain structure and the first source-drain structure are self-aligned structures, so as to effectively improve the symmetry of the structure of the transistor.
After the structure of the source and drain regions of the first transistor is completed, the dummy gate structure formed previously and the sacrificial layer in the gate region where the first gate structure is formed based on the first portion of the active structure may be removed.
It will be appreciated that by removing the dummy gate structure and the sacrificial layer within the gate region, the active structure within the gate region may be exposed, followed by depositing an insulating material over a first portion of the active structure to form a first gate dielectric layer, and depositing a metal material over the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together form a first gate structure. Thus, the first transistor is completed.
It should be noted that the first gate structure may be formed by standard steps of the semiconductor manufacturing process, which is not described herein in detail.
In the embodiment of the present application, the metal material forming the first gate structure may be any one of the following: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), and the like, which are not particularly limited in the embodiments of the present application.
In addition, in some embodiments, a gate structure may also be formed on the first portion and the second portion of the active structure together, that is, an insulating material may be deposited on the first portion and the second portion of the first active structure to form a gate dielectric layer, and a metal material may be deposited on the gate dielectric layer to form a gate electrode layer, where the gate dielectric layer and the gate electrode layer together form the gate structure, and the gate structure encapsulates the first portion and the second portion of the active structure.
In this scenario, the gate structure wrapped over the second portion of the active structure may be subsequently removed, after which the second gate structure of the second transistor is again prepared.
It can be appreciated that when the gate structure wrapped on the second portion of the active structure is etched, the gate dielectric layer and the second interlayer dielectric layer in the gate structure are used as etching stop layers, and etching time is controlled to etch and remove the gate structure wrapped on the second portion of the active structure.
In addition, the embodiment of the application can also realize isolation between the stacked transistors through the gate cutting structure, namely, gate cutting (gate cut) processing of the stacked transistors is performed.
In some embodiments, after forming the first transistor, the first gate structure may be further subjected to gate cutting to form a first gate cutting groove; and filling a first insulating material in the first gate cutting groove to form a first gate cutting structure.
It will be appreciated that a photoresist may be applied over the first gate structure, and after exposure and development (i.e., to form a photoresist layer), a notch is formed at a predetermined location, wherein the notch corresponds to a gate cut-off region of the first transistor. Then, a portion of the first gate structure is etched using the photoresist layer as a mask to form a first gate cut groove.
It should be noted that, the thickness of the first gate cutting groove (i.e. the size of the notch of the photoresist layer) may be designed according to practical situations, but may not be etched on the active structure, which is not specifically limited in the embodiment of the present application.
After forming the first gate cutting groove, the first gate cutting groove may be filled with a first insulating material to form first gate cutting structures located at both sides of the first gate structure.
The first insulating material may be an insulating material such as nitride, for example.
In addition, a gate structure is formed on the first portion and the second portion of the active structure together, and in a scene that the gate structure wraps the first portion and the second portion, gate cutting can be performed on the gate structure to form a gate cutting groove, and a first insulating material is filled in the gate cutting groove to form the gate cutting structure.
The implementation manner of the gate cutting structure may refer to the implementation manner of the first gate cutting structure, which is not described herein again.
It will be appreciated that the gate cut structure herein is located on both sides of the gate structure surrounding the first and second portions.
In this scenario, the gate structure wrapped over the second portion of the active structure, and the gate cut structure corresponding to the second portion, may be subsequently removed, after which the second gate structure of the second transistor, and/or the second gate cut structure, may be re-fabricated.
It should be noted that, in the embodiment of the present application, the gate may be cut off for both the upper and lower layers of transistors (i.e., the first transistor and the second transistor), or only one layer of the transistors may be cut off, i.e., only the first transistor may be cut off, or only the second transistor may be cut off, or no gate cutting process may be performed for both the upper and lower layers of transistors. Wherein the operation of performing the gate cutting process on the first transistor is the same as the operation of performing the gate cutting process on the second transistor.
S130: a gate isolation dielectric layer is formed over the first gate structure.
After forming the first gate structure, an oxide material may be deposited over the first gate structure, and then anisotropically etched to the bottom of the second portion of the active structure, followed by isotropically etching the oxide material to form a gate isolation dielectric layer that serves as isolation of the upper and lower layer transistors over the gate region.
In the case of gate turn-off of the first transistor, the implementation procedure of S130 may further be: and depositing a second insulating material on the first gate structure and the first gate cutting structure to form a gate isolation dielectric layer. The second insulating material may be an insulating material such as oxide, for example.
S140: a second gate structure of the second transistor is formed on the gate isolation dielectric based on the second portion of the active structure.
The preparation process of the structure of the source-drain region of the second transistor is referred to as S120. Here, a second gate structure of the second transistor, and/or a second gate cut structure are prepared.
It will be appreciated that an insulating material may be deposited over the second portion of the active structure to form a second gate dielectric layer, and a metal material may be deposited over the second gate dielectric layer to form a second gate electrode layer, the second gate dielectric layer and the second gate electrode layer together forming a second gate structure.
It should be noted that the second gate structure may be formed by standard steps of the semiconductor manufacturing process, which is not described herein in detail.
The metal material for preparing the first gate structure may be different from or the same as the metal material for preparing the second gate structure.
In some embodiments, after forming the second gate structure, the second gate structure may be further subjected to gate cutting to form a second gate cutting groove; and filling a third insulating material in the second gate cutting groove to form a second gate cutting structure.
It can be understood that the gate isolating dielectric layer, the gate dielectric layer, and the second interlayer dielectric layer may be used as an etching stop layer to perform a gate cutting process of the second transistor, and the gate cutting process operation corresponds to the gate cutting process operation of the first transistor, so as to form a second gate cutting structure.
The third insulating material forming the second gate cutting structure and the first insulating material forming the first gate cutting structure may be the same or different, which is not limited in the embodiment of the present application.
In some embodiments, after the second gate structure and/or the second gate cut structure are completed, a subsequent process (such as dielectric deposition between interconnect lines, metal line formation, formation of an extraction pad, etc.) may be performed on the second gate structure and/or the second gate cut structure, and the second source drain structure, to form a metal interconnect layer of the stacked transistor.
In an embodiment of the present application, by forming an active structure on a substrate structure, a first transistor is formed based on a first portion of the active structure that is closer to the substrate structure, then a gate isolation dielectric layer is formed on a first gate structure of the first transistor, and then a second gate structure of a second transistor is formed on the gate isolation dielectric layer based on a second portion of the active structure. Thus, the manufacturing methods of the first gate structure of the first transistor and the second gate structure of the second transistor are independent. In addition, the grid electrode cutting-off process can be selectively carried out between the upper layer transistor and the lower layer transistor so as to realize different isolation modes between the stacked transistors, and further improve the flexibility and the degree of freedom of the stacked transistors in circuit design.
The following describes a method for manufacturing a stacked transistor according to the embodiment of the present application, taking an active structure in the stacked transistor as a fin structure as an example. Fig. 2A to 2D are four design layouts of stacked transistors in the embodiment of the present application. FIG. 2A is a layout of stacked transistors in which both bottom and top layer transistors are gate-turned off; FIG. 2B is a layout of the stacked transistors with the bottom layer transistors not gate-off and the top layer transistors gate-off; FIG. 2C is a layout of the bottom layer transistor in the stacked transistor with the gate cut off, and the top layer transistor without the gate cut off; fig. 2D is a layout in which neither the bottom nor top transistors of the stacked transistors have gate cuts. Wherein the A-A' direction in fig. 2A-2D is the tangential direction of the stacked transistor along the gate structure; the B-B' direction is the tangential direction of the stacked transistor along the source-drain structure; the C-C' direction is the tangential direction of the stacked transistor along the fin structure; the D-D' direction is the direction along which the fin extends in the stacked transistor but without cutting the tangent plane of the fin. Fig. 2A to 2D (a) are top views of the bottom layer transistor, and fig. 2A to 2D (b) are top views of the top layer transistor.
First, a first structure of the stacked transistor, that is, a structure of the stacked transistor under the layout of fig. 2A will be described. Fig. 3 is a schematic diagram of a first structure of a stacked transistor according to an embodiment of the present application. Fig. 3 (a) is a top view of the stacked transistor, and only fin structures, source-drain structures, and gate structures of the stacked transistor are shown in the top view for ease of understanding. Fig. 3 (B) is a cross-sectional view of the stacked transistor in the A-A ' direction, fig. 3 (c) is a cross-sectional view of the stacked transistor in the B-B ' direction, and fig. 3 (D) is a cross-sectional view of the stacked transistor in the D-D ' direction.
Referring to fig. 3, the stacked transistor 10 includes a first transistor 11 and a second transistor 13, and an active structure in the stacked transistor 10 is a plurality of fin structures. The fin structure is divided into an upper and a lower part, denoted as a first part 111 of the fin structure and a second part 131 of the fin structure, the first part 111 of the fin structure forming the active structure in the first transistor 11 and the second part 131 of the fin structure forming the active structure in the second transistor 13. The first transistor 11 and the second transistor 13 are stacked, and the first transistor 11 is isolated from the second transistor 13 by the gate isolation dielectric layer 12. The first transistor 11 includes a first source drain structure 112, a first source drain metal 113, a first power rail connection metal 115, a first gate structure 116, and a first gate cut-off structure 117, wherein the first power rail connection metal 115 is connected to the first power rail 114. The second transistor 13 includes a second source drain structure 132, a second source drain metal 133, a second power rail connection metal 135, a second gate structure 136, and a second gate cut-off structure 137, wherein the second power rail connection metal 135 is connected to the second power rail 134. The first power rail 114 and the second power rail 134 are located on either side of the fin structure.
In the first embodiment, a method for manufacturing the first structure of the stacked transistor shown in fig. 3 is described with reference to fig. 4 to 30. Where (a) in fig. 4 to (30) are sectional views of the stacked transistor in the A-A 'direction, (B) in fig. 4 to (30) are sectional views of the stacked transistor in the B-B' direction, (C) in fig. 3 to (23) are sectional views of the stacked transistor in the C-C 'direction, and (D) in fig. 22 to (30) are sectional views of the stacked transistor in the D-D' direction.
In one example, the first fabrication process of stacked transistor 10 may include the following steps.
The first step: a layer of silicon germanium material is epitaxially grown on a silicon substrate (wafer) 21 to form a first material layer 22, and then a layer of silicon material is epitaxially grown on the first material layer 22 to form a second material layer 23, resulting in the structure shown in fig. 4.
And a second step of: for the structure shown in fig. 4, the patterning and etching process is completed, forming a fin structure. Wherein the second material layer 23 is etched first, then the first material layer 22 in the middle is etched, then the first portion of the substrate 21 is etched, and the second portion of the substrate 21 is left, resulting in the structure shown in fig. 5.
It will be appreciated that the etched second material layer 23, the first material layer 22, and the first portion of the substrate 21 together form a fin structure, the etched second material layer 23 forms the second portion 131 of the fin structure, and the etched first material layer 22 forms the sacrificial layer 24.
And a third step of: oxide material is deposited on the substrate 21 until the fin structure in fig. 5 is covered, a first shallow trench isolation structure 25 is formed, and a chemical mechanical planarization process is performed on the surface of the first shallow trench isolation structure 25, so as to obtain the structure shown in fig. 6.
Fourth step: the first shallow trench isolation structure 25 shown in fig. 6 is etched using an etching process to expose the second portion 131 of the fin structure and the sacrificial layer 24, so that the first shallow trench isolation structure 25 can cover a lower portion of the first portion of the substrate 21, resulting in the structure shown in fig. 7.
Wherein an upper portion of the first portion of the substrate 21 not covered by the first shallow trench isolation structure 25 forms a first portion 111 of the fin structure.
Fifth step: grooves of the power supply rail are etched in the first shallow trench isolation structure 25 and the substrate 21 shown in fig. 7 by an etching process, so as to obtain a first groove 26 and a second groove 27, and a structure shown in fig. 8 is obtained.
Sixth step: the grooves of the power supply rail shown in fig. 8 are filled with a power supply rail Metal (BPR-Metal) to form the power supply rail, that is, the first grooves 26 and the second grooves 27 are filled with a power supply rail Metal to form the first power supply rail 114 and the second power supply rail 134, resulting in the structure shown in fig. 9.
Seventh step: oxide material is deposited on the power rail shown in fig. 9 to form a second shallow trench isolation structure, the height of the second shallow trench isolation structure is the same as that of the first shallow trench isolation structure 25, and the second shallow trench isolation structure and the first shallow trench isolation structure 25 together form a shallow trench isolation structure 28, so that the structure shown in fig. 10 is obtained.
That is, oxide material is deposited on the power rail to be level with the height of the previous first shallow trench isolation structure.
Eighth step: polysilicon material is deposited in the gate region of the structure shown in fig. 10 to form a dummy gate structure 29 common to the fin structures of the upper and lower layers, and first spacers 30 are formed on both sides of the dummy gate structure to obtain the structure shown in fig. 11.
Ninth step: the second portion 131 of the fin structure and the sacrificial layer 24 of the source drain region of the structure shown in fig. 11 are etched to obtain the structure shown in fig. 12.
Tenth step: the sacrificial layer 24 of the first spacer region is etched, and the etched region is filled with an insulating material to form a second spacer 31, resulting in the structure of fig. 13.
The insulating material may be, for example, a silicon nitride material.
Eleventh step: a silicon nitride coating (Coat-SiN) is deposited at the intersection of the source and drain regions and the gate region using an isotropic deposition process to form a protective layer 32, the protective layer 32 covering the second portion 131 of the fin structure of the gate region and the sacrificial layer 24, resulting in the structure shown in fig. 14.
It will be appreciated that the protective layer 32 may provide for the top fin structure to be unaffected while the bottom source drain structure (i.e., the first source drain structure) is subsequently epitaxially grown.
Twelfth step: a first source-drain structure 112 of the first transistor 11 is epitaxially grown on the first portion 111 of the fin structure of the source-drain region, resulting in the structure as in fig. 15.
Thirteenth step: the protective layer 32 is removed using an etching process to yield the structure of fig. 16.
Fourteenth step: an interlayer dielectric is deposited over the first source drain structure 112 and planarized over the first source drain structure 112 to form a first interlayer dielectric layer 33, resulting in the structure of fig. 17.
Fifteenth step: source-drain metal contacts of the underlying transistor and connections of the underlying transistor to the power supply rail are formed in the first interlayer dielectric layer 33, i.e. the first source-drain metal 113 and the first power supply rail connection metal 115 are formed, resulting in the structure as shown in fig. 18.
Sixteenth step: an interlayer dielectric is deposited over the first source drain metal 113 and the first power rail connection metal 115 to form a source drain isolation dielectric layer (NP isolation) 34, and the first transistor 11 and the second transistor 13 are isolated in the source drain region by the source drain isolation dielectric layer 34, resulting in the structure as shown in fig. 19.
Seventeenth step: a second source-drain structure 132 of the second transistor 13 is epitaxially grown on the source-drain isolation dielectric layer 34, resulting in the structure of fig. 20.
Eighteenth step: an interlayer dielectric is deposited over the second source drain structure 132 and planarized over the second source drain structure 132 to form a second interlayer dielectric layer 35, resulting in the structure of fig. 21.
Nineteenth step: a top transistor source drain metal contact and a top transistor to power rail connection are formed in the second interlayer dielectric layer 35, that is, a second source drain metal 133 and a second power rail connection metal 135 are formed, resulting in the structure as shown in fig. 22.
To facilitate the consistency of the subsequent structure, a cut-out view in the D-D' direction is added here.
Twenty-step: the dummy gate structure 29 and the sacrificial layer 24 at the gate region are removed and a gate structure 36 common to the top and bottom layer transistors is formed over the first and second portions of the fin structure resulting in the structure as in fig. 23.
Wherein the gate structure 36 includes a gate dielectric layer and a gate electrode layer coated over the first and second portions of the fin structure.
Twenty-first step: gate cutting is performed on the first transistor 11, that is, gate cutting is performed on the gate structure 36 to form a cut groove, and an insulating material is filled in the gate cut groove to form a gate cut structure 37, resulting in the structure as shown in fig. 24.
Wherein the gate cut-off structure 37 is on both sides of the gate structure 36 common to the top and bottom transistors.
The insulating material may be a nitride material, for example.
Twenty-second step: the gate dielectric layer and the second interlayer dielectric layer 35 in the gate structure are used as etching stop layers, etching time is controlled to etch and remove the gate structure and the gate cut-off structure wrapped by the second portion of the fin structure, the remaining gate structure wrapped by the first portion of the fin structure is used as the first gate structure 116 of the underlying transistor (the first transistor 11), and the gate cut-off structure corresponding to the first portion of the fin structure is used as the first gate cut-off structure 117 of the first transistor 11, so as to obtain the structure as shown in fig. 25.
Twenty-third step: oxide material is isotropically deposited over the first gate structure 116 and the first gate cut structure 117 and planarized to the gate dielectric layer, resulting in the structure of fig. 26.
Twenty-fourth step: for the structure of fig. 26, the oxide material deposited in the previous step is anisotropically etched to the bottom layer of the second portion of the fin structure, resulting in the structure of fig. 27.
Twenty-fifth step: for the structure of fig. 27, the oxide material etched in the previous step is then isotropically etched to form the gate isolation dielectric layer 12, which forms the isolation of the top layer transistor and the bottom layer transistor over the gate region, resulting in the structure of fig. 28.
Twenty-sixth step: on the gate isolation dielectric layer 12, a second gate structure 136 of the top-level transistor is formed, resulting in the structure of fig. 29.
The metal material of the gate electrode layer in the second gate structure 136 may be the same as or different from the metal material of the gate electrode layer in the first gate structure 116.
Twenty-seventh step: the self-aligned gate cutting of the top-level transistor is performed with the gate isolation dielectric layer 12, the gate electrode layer, and the second interlayer dielectric layer 35 as etch stop layers to form a second gate cut structure 137, resulting in the structure as shown in fig. 30.
The insulating material in the second gate cutting structure 137 may be the same as or different from the insulating material in the first gate cutting structure 117.
Twenty eighth step: the CMP reduces the height of the top layer and simultaneously removes the gate dielectric layer on top of the source and drain regions, completing the subsequent interconnect process for stacking transistor 10, forming metal interconnect layer 38, resulting in the structure of fig. 3.
Thus, a first structure of the completed stacked transistor is prepared.
Next, a second structure of the stacked transistor, that is, a structure of the stacked transistor under the layout of fig. 2B will be described.
Referring to the above-described method for manufacturing the first structure, unlike the method for manufacturing the first structure, since the underlying transistor is not subjected to gate cutting, after the structure as shown in fig. 23 is obtained in the twentieth step is performed, the operation of forming the gate cutting structure in the twentieth step is not performed, and accordingly, the operation of etching the gate cutting structure in the twenty-second step is not performed. The remaining steps are still performed through the twenty-sixth step, forming the second gate structure 136 of the top-level transistor, resulting in the structure of fig. 31. As shown in fig. 31, the first gate cut structure 117 is not present in the underlying transistor. A twenty-seventh step is performed to perform gate turn-off of the top-level transistor to form a second gate turn-off structure 137, resulting in the structure of fig. 32. Finally, a twenty eighth step is performed to interconnect the source drain metal of the transistor with the subsequent interconnect metal line to form the metal interconnect layer 38, resulting in the structure shown in fig. 33.
Next, a third structure of the stacked transistor, that is, a structure of the stacked transistor under the layout of fig. 2C will be described.
Referring to the above-described method for manufacturing the first structure, unlike the method for manufacturing the first structure, since the top-layer transistor is not subjected to gate cutting, after the structure as shown in fig. 29 is obtained in the twenty-sixth step, the operation of forming the second gate cutting structure 137 in the twenty-seventh step is not performed, and the twenty-eighth step is directly performed, so that the metal interconnection layer 38 is formed, thereby obtaining the structure as shown in fig. 34.
Finally, a fourth structure of the stacked transistor is described, namely, a structure of the stacked transistor under the layout of fig. 2D is described.
Referring to the above-described method for manufacturing the first structure, unlike the method for manufacturing the first structure, since the underlying transistor is not subjected to gate cutting, after the structure as shown in fig. 23 is obtained in the twentieth step is performed, the operation of forming the gate cutting structure in the twentieth step is not performed, and accordingly, the operation of etching the gate cutting structure in the twenty-second step is not performed. The remaining steps are still performed, and since the top-layer transistor is not gate-off, after the twenty-sixth step is performed, the twenty-eighth step is directly performed without performing the operation of forming the second gate-off structure 137 in the twenty-seventh step, forming the metal interconnection layer 38, resulting in the structure as in fig. 35. As shown in fig. 35, no gate cut structure is present in both the top layer transistor and the bottom layer transistor.
According to the embodiment of the application, the scheme of realizing the isolation of the gate structures and the gate cutting structures of the upper-layer transistor and the lower-layer transistor is adopted, so that the gate structures of the upper-layer transistor and the lower-layer transistor are different and isolated from each other, and meanwhile, the gate cutting structures of the upper-layer transistor and the lower-layer transistor are isolated from each other. In addition, the upper layer transistor and the lower layer transistor can independently select a grid structure and a grid cutting structure, so that the flexibility and the freedom degree of the stacked transistor in circuit design are improved.
Further, the stacked transistor provided in the embodiments of the present application may be detected using a detection analysis instrument, for example: scanning electron microscope (scanning electron microscope, SEM), transmission electron microscope (transmission electron microscope, TEM), scanning transmission electron microscope (scanning transmission electron microscopy, STEM), and the like. Taking TEM as an example, the stacked transistor provided in the embodiments of the present application may adopt a TEM slicing manner to detect the above-mentioned different types of gate cut structures.
The embodiment of the application provides a semiconductor device, which comprises: stacked transistors as in the above embodiments. For specific limitation of the stacked transistor, reference may be made to the above stacked transistor, and detailed description thereof is omitted herein.
An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device includes the above-described stacked transistor. For specific limitation of the stacked transistor, reference may be made to the above stacked transistor, and detailed description thereof is omitted herein.
In the description of the embodiments of the present application, a description referring to the terms "one embodiment," "an example," "a particular example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In this application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described herein, as well as the features of the various embodiments or examples, may be combined by those skilled in the art without contradiction.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations can be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (12)

1. A method of fabricating a stacked transistor, comprising:
forming an active structure on a substrate structure, the active structure comprising a first portion and a second portion, the first portion being closer to the substrate structure than the second portion;
forming a first transistor based on a first part of the active structure, wherein the first transistor comprises a first grid structure wrapping the first part and first source-drain structures positioned on two sides of the first grid structure;
forming a gate isolation dielectric layer on the first gate structure;
forming a second gate structure of a second transistor on the gate isolation dielectric layer based on a second portion of the active structure; the first grid structure is isolated from the second grid structure through the grid isolation dielectric layer.
2. The method of claim 1, wherein after forming the first transistor based on the first portion of the active structure, the method further comprises:
gate cutting is conducted on the first gate structure to form a first gate cutting groove;
filling a first insulating material in the first grid cutting groove to form a first grid cutting structure;
The forming a gate isolation dielectric layer on the first gate structure includes:
and depositing a second insulating material on the first gate structure and the first gate cutting structure to form the gate isolation medium layer.
3. The method of claim 1 or 2, wherein after forming a second gate structure of a second transistor on the gate isolation dielectric layer based on the second portion of the active structure, the method further comprises:
gate cutting is conducted on the second gate structure to form a second gate cutting groove;
and filling a third insulating material in the second gate cutting groove to form a second gate cutting structure.
4. The method of claim 1, wherein the active structure further comprises: a sacrificial layer located between the first portion and the second portion;
the forming a first transistor based on the first portion of the active structure includes:
removing the second portion of the active structure and the sacrificial layer in the source drain region of the stacked transistor;
forming the first source-drain structure based on the first part of the active structure;
forming a first source drain metal on the first source drain structure;
The method further comprises the steps of:
epitaxially growing a second source-drain structure on the first source-drain metal, the second portion being surrounded by the second gate structure;
and forming a second source-drain metal on the second source-drain structure.
5. The method of claim 4, wherein after forming a first source drain metal on the first source drain structure, the method further comprises:
and depositing a fourth insulating material on the first source-drain metal to form a source-drain isolation dielectric layer, wherein the first source-drain metal is isolated from the second source-drain structure through the source-drain isolation dielectric layer.
6. The method according to claim 4, wherein the method further comprises:
embedding a first power rail and a second power rail in the substrate structure, wherein the first power rail and the second power rail are respectively arranged at two sides of the active structure;
after the forming the first source-drain structure based on the first portion of the active structure, the method further includes:
forming a first power rail connection metal on the first power rail, wherein the first power rail connection metal is connected with a first source metal in the first source-drain metal;
After epitaxially growing the second source-drain structure on the first source-drain metal, a second portion surrounded by the second gate structure, the method further comprises:
and forming a second power rail connection metal on the second power rail, wherein the second power rail connection metal is connected with a second source electrode metal in the second source electrode and drain electrode metals.
7. The method of any of claims 4 to 6, wherein prior to the forming the first source drain structure based on the first portion of the active structure, the method further comprises:
depositing a first semiconductor material at the intersection of the source-drain region and the gate region of the stacked transistor to form a protective layer covering the second portion of the active structure and the sacrificial layer;
after the forming the first source-drain structure based on the first portion of the active structure, the method further includes:
and removing the protective layer.
8. The method of claim 1, wherein forming an active structure on a substrate structure comprises:
providing a wafer, and sequentially depositing a first material layer and a second material layer on the wafer;
etching the second material layer, the first material layer and the first part of the wafer, wherein the etched first material layer forms the sacrificial layer, and the etched second material layer forms the second part of the active structure;
Depositing an oxide material on a second portion of the wafer to form a first shallow trench isolation structure, the first shallow trench isolation structure having a height that is less than a height of a first portion of the wafer, the first portion of the wafer not being surrounded by the first shallow trench isolation structure forming a first portion of the active structure.
9. The method of claim 8, wherein after forming the active structure on the substrate structure, the method further comprises:
etching the first shallow trench isolation structures and the first area of the wafer which are positioned at two sides of the active structure to form a first groove and a second groove;
filling second metal materials in the first groove and the second groove to form a first power rail and a second power rail, wherein the heights of the first power rail and the second power rail are smaller than the height of the first shallow groove isolation structure;
depositing the oxide material on the first power rail and the second power rail to form a second shallow trench isolation structure, wherein the height of the second shallow trench isolation structure is the same as that of the first shallow trench isolation structure.
10. A stacked transistor manufactured using the manufacturing method according to any one of claims 1 to 9, comprising:
A first transistor;
a second transistor, the first transistor and the second transistor being stacked;
and the first grid structure of the first transistor is isolated from the second grid structure of the second transistor through the grid isolation dielectric layer.
11. A semiconductor device, comprising: the stacked transistor of claim 10.
12. An electronic device, comprising: a circuit board and the semiconductor device according to claim 11, the semiconductor device being provided to the circuit board.
CN202410177683.1A 2024-02-08 2024-02-08 Preparation method of stacked transistor, device and equipment Pending CN117878061A (en)

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CN202410177683.1A CN117878061A (en) 2024-02-08 2024-02-08 Preparation method of stacked transistor, device and equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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