CN117995753A - Preparation method of stacked transistor, device and equipment - Google Patents
Preparation method of stacked transistor, device and equipment Download PDFInfo
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- CN117995753A CN117995753A CN202410130550.9A CN202410130550A CN117995753A CN 117995753 A CN117995753 A CN 117995753A CN 202410130550 A CN202410130550 A CN 202410130550A CN 117995753 A CN117995753 A CN 117995753A
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 176
- 239000004065 semiconductor Substances 0.000 claims abstract description 150
- 238000000034 method Methods 0.000 claims abstract description 91
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000011810 insulating material Substances 0.000 claims abstract description 38
- 238000000151 deposition Methods 0.000 claims abstract description 23
- 230000001590 oxidative effect Effects 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 215
- 238000002955 isolation Methods 0.000 claims description 98
- 238000004519 manufacturing process Methods 0.000 claims description 29
- 239000011229 interlayer Substances 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 15
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 32
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 32
- 238000005530 etching Methods 0.000 description 23
- 230000005669 field effect Effects 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910003481 amorphous carbon Inorganic materials 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 238000013459 approach Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000012369 In process control Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010965 in-process control Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000001350 scanning transmission electron microscopy Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The application provides a preparation method of a stacked transistor, the stacked transistor, a device and equipment. The method comprises the following steps: sequentially stacking a first active structure, an isolated active structure and a second active structure on a substrate; forming a first transistor based on the first active structure; depositing a first insulating material on a first surface of the first transistor facing the second active structure to form a first semiconductor material layer; depositing a second insulating material over the second active structure and the first semiconductor material layer to form a second semiconductor material layer; removing a portion of the second layer of semiconductor material overlying the first layer of semiconductor material to expose the first layer of semiconductor material; removing the first semiconductor material layer to expose the isolated active structure; oxidizing the isolated active structure to form an isolated dielectric structure; removing a portion of the second semiconductor material layer covering the second active structure to expose the second active structure; a second transistor is formed based on the second active structure.
Description
Technical Field
The present application relates to the field of semiconductors, and in particular, to a method for manufacturing a stacked transistor, a device, and an apparatus.
Background
While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors further increase transistor integration density by integrating two or more layers of transistors in vertical space is one of the important technologies continuing the scaling of integrated circuits.
When a traditional monolithic scheme is adopted to prepare a stacked transistor (stacked transistor), the active regions of the upper layer transistor and the lower layer transistor need to be electrically isolated, and the current electrical isolation mode has the following technical difficulties: the ion implantation mode is difficult in process control, and the diffusion effect of implanted ions can have a great influence on the thermal budget of the subsequent process, and can damage the device structure.
Disclosure of Invention
The application provides a preparation method of a stacked transistor, the stacked transistor, a device and equipment, so that isolation between an active region of a first transistor and an active region of a second transistor is realized under the condition that a device structure is not damaged.
In a first aspect, an embodiment of the present application provides a method for manufacturing a stacked transistor, where the method includes: sequentially stacking a first active structure, an isolated active structure and a second active structure on a substrate; forming a first transistor based on the first active structure; depositing a first insulating material on a first surface of the first transistor facing the second active structure to form a first semiconductor material layer; a first layer of semiconductor material surrounding the isolated active structure; depositing a second insulating material over the second active structure and the first semiconductor material layer to form a second semiconductor material layer; the second semiconductor material layer wraps the second active structure; removing a portion of the second layer of semiconductor material overlying the first layer of semiconductor material to expose the first layer of semiconductor material; removing the first semiconductor material layer to expose the isolated active structure; oxidizing the isolated active structure to form an isolated dielectric structure; removing a portion of the second semiconductor material layer covering the second active structure to expose the second active structure; a second transistor is formed based on the second active structure.
In some possible embodiments, before forming the first transistor based on the first active structure, the method further comprises: depositing a dielectric material on the first active structure, the isolation active structure and the second active structure to form a shallow trench isolation structure; the shallow slot isolation structure wraps the first active structure, the isolation active structure and the second active structure; removing the first portion of the shallow trench isolation structure to expose the first active structure; before forming the second transistor based on the second active structure, the method further comprises: and rewinding and removing the substrate.
In some possible embodiments, after rewinding and removing the substrate, before forming the first semiconductor material layer, the method further includes: removing a portion of the second active structure away from the first active structure to form a first recess; depositing a second insulating material in the first recess to form a first filling structure; a second portion of the shallow trench isolation structure is removed to expose the second active structure and isolate the active structure.
In some possible embodiments, removing a portion of the second layer of semiconductor material that covers the first layer of semiconductor material to expose the first layer of semiconductor material includes: a portion of the second layer of semiconductor material overlying the first layer of semiconductor material is removed and a portion of the second layer of semiconductor material overlying the first fill structure is removed to expose the first layer of semiconductor material and the first fill structure.
In some possible embodiments, after oxidizing the isolated active structure to form an isolated dielectric structure, the method further comprises: removing the first filling structure and the second semiconductor material layer to expose the second active structure; a second transistor is formed based on the second active structure.
In some possible embodiments, removing a portion of the second layer of semiconductor material that covers the first layer of semiconductor material to expose the first layer of semiconductor material includes: removing a portion of the second layer of semiconductor material overlying the first layer of semiconductor material and a portion of the second layer of semiconductor material overlying the second surface of the second active structure to expose the first layer of semiconductor material and the second surface; the second surface is a surface of the second active structure away from the first active structure.
In some possible embodiments, after removing the first semiconductor material layer to expose the isolated active structure, the method further comprises: depositing a second insulating material over the second surface and the first region of the first surface to form a third layer of semiconductor material; the first region is not in contact with the second active structure.
In some possible embodiments, after oxidizing the isolated active structure to form an isolated dielectric structure, the method further comprises: removing the second semiconductor material layer and the third semiconductor material layer to expose the second active structure; a second transistor is formed based on the second active structure.
In some possible embodiments, forming a first transistor based on the first active structure includes: forming a first pseudo gate structure, a first gap wall, a first source drain structure and a first interlayer dielectric layer of a first transistor in sequence based on the first active structure; removing the first dummy gate structure and forming a first gate structure and a first gate dielectric layer; and performing subsequent process treatment on the first interlayer dielectric layer to form a first metal interconnection layer.
In some possible embodiments, forming a second transistor based on the second active structure includes: forming a second pseudo gate structure, a second gap wall, a second source drain structure and a second interlayer dielectric layer of the second transistor in sequence based on the second active structure; removing the second pseudo gate structure and forming a second gate structure and a second gate dielectric layer; and performing subsequent process treatment on the second interlayer dielectric layer to form a second metal interconnection layer.
In a second aspect, an embodiment of the present application provides a stacked transistor including: a first transistor; a second transistor; the first active structure of the first transistor and the second active structure of the second transistor are formed by the same process, and the first transistor and the second transistor are self-aligned; and the isolation medium structure is used for isolating the first active structure and the second active structure, and the isolation medium structure is positioned between the first active structure and the second active structure.
In a third aspect, an embodiment of the present application provides a semiconductor device including: stacked transistors as in the above embodiments.
In a fourth aspect, an embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board.
In the application, the isolation medium structure is formed by oxidizing the isolation active structure between the first active structure and the second active structure, so that the isolation between the active region of the first transistor and the active region of the second transistor can be realized under the condition of not damaging the device structure.
Further, compared with the traditional ion implantation and isolation method adopting Silicon On Insulator (SOI), the isolation medium structure is simpler in process, and meanwhile, the self-alignment problem of the first transistor and the second transistor is considered, so that the consistency of the active areas of the first transistor and the second transistor is ensured.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic flow chart of a first implementation of a method for manufacturing a stacked transistor according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a first structure of a stacked transistor according to an embodiment of the present application;
fig. 3A to 3F are schematic views illustrating a first process for manufacturing a stacked transistor according to an embodiment of the present application;
fig. 4A to 4D are schematic views illustrating a second process for manufacturing a stacked transistor according to an embodiment of the present application;
The figures above:
10. Stacking transistors; 11. a first transistor; 111. a first active structure; 112. a first spacer; 113. a first source drain structure; 114. a first interlayer dielectric layer; 115. a first gate dielectric layer; 116. a first gate structure; 117. a first metal interconnect layer; 12. a second transistor; 121. a second active structure; 122. a second spacer; 123. a second source drain structure; 124. a second interlayer dielectric layer; 125. a second gate dielectric layer; 126. a second gate structure; 127. a second metal interconnect layer; 128. a second dummy gate structure; 13. an isolation medium structure; 14. a first insulating layer; 15. a carrier wafer; 21. a substrate; 22. a fin structure; 221. a first fin structure; 222. a second fin structure; 223. isolating the active structure; 23. shallow trench isolation structure; 231. a first portion of the shallow trench isolation structure; 232. a second portion of the shallow trench isolation structure; 233. shallow groove isolation layer; 24. a first groove; 25. a first filling structure; 31. a first semiconductor material layer; 32. a second semiconductor material layer; 33. and a third semiconductor material layer.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.
While moore's law is continually deepening, continuing to advance transistor scaling after the technology node of the full-round gate transistor (GAA) is a hot spot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits.
In one embodiment, the fabrication process of the stacked transistor (stacked transistors) has two schemes, a single-chip scheme and a sequential scheme.
In the first approach, N-channel field effect transistors (N FIELD EFFECT transistors, NFETs) and P-channel field effect transistors (P FIELD EFFECT transistors, PFETs) are fabricated on the same substrate, and wafer bonding techniques are not used. This determines that the same layer transistors must be of the same type, i.e., NFET or PFET. And the transistors on the upper layer and the lower layer are strictly in the same plane space, and no alignment deviation exists. The advantage of this solution is a better integration density. Drawbacks of this approach include the following two points: (1) The process is complex, and a large number of process technologies need to be developed and optimized; (2) Each layer of transistors has a fixed polarity, and two layers of transistors must be relied upon to form a basic Complementary Metal Oxide Semiconductor (CMOS) circuit, which has poor design flexibility.
The second scheme is based on wafer bonding and layer-by-layer processing. Specifically, the two transistors are stacked vertically by bonding a wafer on top of the fabricated lower transistor to prepare the upper transistor. However, this approach requires tight temperature control during the thermal process of processing the upper layer transistors, avoiding affecting the lower layer transistors and the interconnect lines. The scheme has the advantages that the device structure, the channel crystal orientation and even the channel material adopted by the upper layer transistor and the lower layer transistor can be correspondingly optimized to obtain better and more matched device performance due to wafer bonding. This solution currently presents the following technical challenges: (1) preparation of a high-quality upper transistor active layer; (2) thinning and defect control of the upper bonded wafer; (3) The upper and lower layer transistors have alignment errors and have extremely high requirements on photoetching precision.
In the first scheme (i.e., the monolithic scheme), electrical isolation is required between the active regions of the upper transistor and the lower transistor, and the current isolation method includes: (1) Using the SOI substrate, forming a natural electrical isolation layer by using a buried oxide layer (BOX) in the SOI substrate; (2) The electrical isolation layer is formed by ion implantation of P-type ions, N-type ions or oxygen ions. However, the cost of the SOI substrate is high, and it is difficult to obtain an SOI substrate with a BOX layer and a device layer having a proper thickness; the ion implantation mode is difficult in process control, and the diffusion effect of implanted ions can have a great influence on the thermal budget of the subsequent process, and can damage the device structure.
In order to solve the technical problems described above, an embodiment of the present application provides a method for manufacturing a stacked transistor, so as to achieve isolation between an active region of a first transistor and an active region of a second transistor without damaging a device structure.
In the embodiment of the application, the stacked transistor can be applied to semiconductor devices such as memories, processors and the like.
In an embodiment, the stacked transistor may include at least two transistors, for example, a first transistor and a second transistor. The first transistor and the second transistor are arranged opposite to each other. Wherein the first active structure in the first transistor and the second active structure in the second transistor are formed by the same process, it is understood that the first active structure and the second active structure are self-aligned.
In the embodiment of the application, the first transistor and the second transistor in the stacked transistors may be transistors of the same type, such as any one of the following: fin field effect transistors, fully surrounding gate transistors, planar transistors, and vertical transistors.
Fig. 2 is a stacked transistor formed by a fin field effect transistor, and a method for manufacturing the stacked transistor according to an embodiment of the present application is described below with reference to the stacked transistor shown in fig. 2.
Fig. 1 is a schematic flow chart of a first implementation of a method for manufacturing a stacked transistor according to an embodiment of the present application, where the stacked transistor includes a first active structure for manufacturing a first transistor, a second active structure for manufacturing a second transistor, and an isolated active structure located between the first active structure and the second active structure. Referring to fig. 1, the method for manufacturing the stacked transistor may include:
s101, sequentially stacking a first active structure, an isolated active structure and a second active structure on a substrate.
It can be appreciated that in the process of preparing the stacked transistor, a substrate is provided first, and the active structure is etched based on the substrate; then, preparing a first transistor based on the first active structure; then, rewinding the first transistor to enable the second active structure to be placed upwards; next, preparing a second transistor based on the second active structure; a first transistor and a second transistor are formed in a back-to-back arrangement.
In some embodiments, when the stacked transistor is a fin field effect transistor, stacking the first active structure, the isolation active structure, and the second active structure on the substrate in order may include: etching the substrate to form a plurality of fin structures; the fin structure is divided into three parts from top to bottom, wherein the first part is a first active structure, the second part is an isolated active structure, and the third part is a second active structure.
In other embodiments, when the stacked transistor is a fully-around gate transistor, the stacking the first active structure, the isolation active structure, and the second active structure on the substrate in order may include: etching a substrate to form a columnar structure, wherein the substrate is formed of alternately deposited silicon (Si) layers and silicon germanium (SiGe) layers; the columnar structure is divided into three parts from top to bottom, wherein the first part is a first active structure, the second part is an isolated active structure, and the third part is a second active structure.
In still other embodiments, when the stacked transistor is a planar transistor, the stacking the first active structure, the isolation active structure, and the second active structure on the substrate in order may include: etching the substrate to form a block structure; the block structure is divided into three parts from top to bottom, wherein the first part is a first active structure, the second part is an isolated active structure, and the third part is a second active structure.
In the embodiment of the application, since the stacked transistor comprises two transistors (i.e., the first transistor and the second transistor), and the first active structure of the first transistor and the second active structure of the second transistor are formed by the same etching process, a larger etching depth can be used when etching the substrate. For example, the height of the etched fin structure (which may also be a columnar structure or a bulk structure) may be greater than 100nm. It should be noted that the height of the fin structure may be set according to practical situations, which is not particularly limited in the embodiment of the present application.
S102, forming a first transistor based on the first active structure.
In some possible embodiments, S102 may include: forming a first dummy gate structure, a first spacer (spacer), a first source drain structure and a first interlayer dielectric layer of a first transistor in sequence based on the first active structure; removing the first dummy gate structure and forming a first gate structure and a first gate dielectric layer; and performing subsequent process treatment on the first interlayer dielectric layer to form a first metal interconnection layer.
In some embodiments, the forming, based on the first active structure, the first dummy gate structure, the first spacer, the first source drain structure, and the first interlayer dielectric layer of the first transistor in order may include: photoetching a gate region of the first transistor, and depositing a semiconductor material (such as polysilicon) in the gate region to form a first pseudo gate structure of the first transistor; forming first gap walls on two sides of the first pseudo gate structure; removing a part of the first active structure by etching, providing a source-drain groove of the first transistor, forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the first transistor by selective epitaxial growth by taking the first spacer as a mask so as to fill the source-drain groove of the first transistor, and then forming the first source-drain structure on the strained material by a heavy doping process; depositing an insulating material (such as silicon dioxide (SiO 2)) above the first active structure and the first source drain structure to form a first interlayer dielectric layer; the first interlayer dielectric layer can cover the first active structure and the first source drain structure; then removing the first pseudo gate structure, and depositing an insulating material on the surface of the first active structure to form a first gate dielectric layer of the first transistor; depositing a metal material in the gate region to form a first gate structure; and finally, carrying out subsequent process treatment on the first interlayer dielectric layer to form a first metal interconnection layer.
It should be noted that, for convenience of description, the first source-drain structure in the embodiment of the present application is referred to as simply, and specifically refers to a first source structure and/or a first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, the source-drain groove and the like are similar to those of the first source-drain structure, wherein 'source-drain' is abbreviated as 'source electrode and/or drain electrode'.
In some possible embodiments, after forming the first transistor based on the first active structure and before rewinding and removing the substrate, the method may further include: an insulating material (e.g., silicon oxide) is deposited over the first metal interconnect layer to form a first insulating layer and the first insulating layer is bonded to the carrier wafer.
In the embodiment of the application, the bonded slide wafer can provide physical support for the turned first transistor after rewinding, so that the first transistor is effectively prevented from being broken due to external force in the process of preparing the second transistor.
And S103, depositing a first insulating material on a first surface of the first transistor facing the second active structure to form a first semiconductor material layer.
The first semiconductor material layer covers the first surface and surrounds the isolated active structure.
It will be appreciated that the first transistor and the second transistor are disposed opposite one another, during the fabrication process, the first transistor is first fabricated, after the fabrication of the first transistor is completed, the first transistor is reworked, and a first insulating material is deposited over the first transistor (i.e., the first transistor is adjacent to the first surface of the second transistor) to form a first layer of semiconductor material.
In an embodiment of the present application, the first insulating material may include, but is not limited to: amorphous carbon (amorphous carbon), amorphous silicon (amorphous silicon), and the like, but may be other insulating materials, and embodiments of the present application are not particularly limited thereto.
And S104, depositing a second insulating material on the second active structure and the first semiconductor material layer to form a second semiconductor material layer.
The second semiconductor material layer wraps the second active structure and covers the first semiconductor material layer.
It will be appreciated that the second semiconductor material layer may be formed overlying the first semiconductor material layer while surrounding the second active structure using an atomic layer deposition process to deposit a second insulating material over the second active structure and the first semiconductor material layer.
In the embodiment of the present application, the second insulating material is different from the first insulating material, and for convenience of description, the second insulating material is exemplified as silicon nitride (SiN). It should be noted that the second insulating material may be other insulating materials, which is not particularly limited in the embodiment of the present application.
And S105, removing a part of the second semiconductor material layer, which covers the first semiconductor material layer, so as to expose the first semiconductor material layer.
It will be appreciated that during subsequent fabrication, the isolated active structure is required to be exposed, so that in order of stacking the material layers, the portion of the second semiconductor material layer overlying the first semiconductor material layer (i.e., the portion of the second semiconductor material layer overlying the first semiconductor material layer) is removed first, exposing the first semiconductor layer to facilitate subsequent removal of the first semiconductor material layer.
And S106, removing the first semiconductor material layer to expose the isolated active structure.
It will be appreciated that after exposing the first semiconductor material, the first semiconductor material layer is removed, exposing the isolated active structure for a subsequent oxidation process.
And S107, performing oxidation treatment on the isolated active structure to form an isolated medium structure.
It will be appreciated that, by the oxidation process, the material of the isolated active structure is oxidized to another material different from the first active structure and the second active structure, and the isolated active structure is transformed to an isolated dielectric structure. Due to the difference in materials, the isolation dielectric structure may be used to isolate the first active structure from the second active structure.
In the embodiment of the application, the isolation medium structure is positioned between the first active structure and the second active structure, and the material of the isolation medium structure formed by oxidation treatment is different from that of the first active structure and the second active structure, so that the isolation medium structure can realize isolation between the active region of the first transistor and the active region of the second transistor.
In the embodiment of the application, the active region is a combination of a source region, a drain region and a channel region.
And S108, removing a part of the second semiconductor material layer which covers the second active structure to expose the second active structure.
It will be appreciated that in S105, the second semiconductor material layer is not removed completely, and a portion of the second semiconductor material layer surrounds the surface of the second active structure, and after the portion of the second semiconductor material layer is removed, the second active structure may be exposed, so as to facilitate the subsequent preparation of the second transistor.
S109, forming a second transistor based on the second active structure.
In some possible embodiments, S109 may include: forming a second pseudo gate structure, a second gap wall, a second source drain structure and a second interlayer dielectric layer of the second transistor in sequence based on the second active structure; removing the second pseudo gate structure and forming a second gate structure and a second gate dielectric layer; and performing subsequent process treatment on the second interlayer dielectric layer to form a second metal interconnection layer.
It should be noted that the process of preparing the second transistor is the same as the process of preparing the first transistor, and the embodiments of the present application are not described herein.
In some possible embodiments, before the step S102, the method may further include: depositing a dielectric material on the first active structure, the isolation active structure and the second active structure to form a shallow trench isolation structure; the shallow slot isolation structure wraps the first active structure, the isolation active structure and the second active structure; removing the first portion of the shallow trench isolation structure to expose the first active structure; the method may further include, prior to forming the second transistor based on the second active structure: and rewinding and removing the substrate.
In the embodiment of the present application, the dielectric material (i.e., insulating material) forming the shallow trench isolation structure may be any of the following: silicon nitride (SiN, si 3N4), silicon dioxide (SiO 2), silicon oxycarbide (SiCO), or the like, but may be other insulating materials, and embodiments of the present application are not limited thereto.
In some embodiments, after forming the shallow trench isolation structure, the method may further include: a chemical-mechanical planarization (CMP) process is performed on the shallow trench isolation structure.
In the embodiment of the application, the shallow trench isolation structure is subjected to chemical mechanical planarization, so that the corresponding corrosion depths of the shallow trench isolation structures in different areas are the same when the shallow trench isolation structure is etched later, and the heights of the tops of the exposed active structures are the same.
It should be noted that, the etching process mentioned in the embodiment of the present application may include any of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal processes, to which embodiments of the present application are not limited.
In the embodiment of the application, the solvent used for etching the shallow trench isolation structure can be: DHF solution or BOE solution. The solvent used in the etching process according to the embodiment of the present application may be selected according to the actual situation, and is not limited to the DHF solution or the BOE solution.
In some possible embodiments, after the rewinding and removing the substrate, and before forming the first semiconductor material layer, the method may further include: removing a portion of the second active structure away from the first active structure to form a first recess; depositing a second insulating material in the first recess to form a first filling structure; a second portion of the shallow trench isolation structure is removed to expose the second active structure and isolate the active structure.
It will be appreciated that after removal of the substrate, the shallow trench isolation structure is exposed, at which point the shallow trench isolation structure is level with the second active structure in a direction perpendicular to the substrate. Next, a portion of the second active structure may be etched by selective etching to form a first recess.
The etching height (i.e., the height of the first groove) may be set according to practical situations, which is not particularly limited in the embodiment of the present application.
In some embodiments, a second insulating material is co-deposited in the first groove and above the shallow trench isolation structure, and the deposited second insulating material fills the first groove and covers the surface of the shallow trench isolation structure; and then, carrying out CMP treatment on the deposited second insulating material, wherein the CMP is stopped on the surface of the shallow trench isolation structure, and the second insulating material in the first groove is not removed to form a first filling structure.
In some embodiments, the shallow trench isolation structure is comprised of a first portion surrounding the first active structure and a second portion surrounding the second active structure and isolating the active structure.
In some possible embodiments, in the case of forming the first filling structure, the step S105 may include: a portion of the second layer of semiconductor material overlying the first layer of semiconductor material is removed and a portion of the second layer of semiconductor material overlying the first fill structure is removed to expose the first layer of semiconductor material and the first fill structure.
It will be appreciated that the second semiconductor material layer covers the surfaces of the first fill structure, the first semiconductor material layer and the first active structure, and that the thickness of the SiN material on the second surface of the second active structure (i.e. the side of the second active structure remote from the first active structure) is greater than the thickness of the SiN material on the first semiconductor material layer, since both the second semiconductor material layer and the first fill structure are of a second insulating material (for example SiN). At this time, the SiN material covered on the first semiconductor material layer and a portion of the SiN material on the second surface of the second active structure may be removed by anisotropic etching, and the remaining SiN material wraps the surface of the second active structure.
In some possible embodiments, in the case of forming the first filling structure, after the step S107, the method may further include: removing the first filling structure and the second semiconductor material layer to expose the second active structure; a second transistor is formed based on the second active structure.
It will be appreciated that taking the second insulating material as an example of the SiN material, after the isolation dielectric structure is formed, the SiN material coated on the surface of the second active structure is removed, so as to expose the second active structure, so as to facilitate the subsequent preparation of the second transistor.
In some possible embodiments, the step S105 may include: a portion of the second layer of semiconductor material overlying the first layer of semiconductor material is removed, and a portion of the second layer of semiconductor material overlying the second surface of the second active structure is removed to expose the first layer of semiconductor material and the second surface. The second surface is a surface, far away from the first active structure, of the second active structure.
It will be appreciated that, taking the second insulating material as an example of the SiN material, after depositing (e.g., atomic layer deposition) a layer of SiN material on the surface of the second active structure and on the first semiconductor material layer, the deposited SiN material is a second semiconductor material layer, and the second semiconductor material layer wraps around the second active structure and covers the first semiconductor material layer. The SiN material on the second surface of the second active structure and on the first semiconductor material layer may then be removed by anisotropic etching, with the SiN material remaining on the sides of the second active structure after etching (i.e., the surfaces of the second active structure other than the second surface and the surfaces in contact with the isolated active structure).
In some possible embodiments, the method may include, after the step S106, without forming the first filling structure: a second insulating material is deposited over the second surface and the first region of the first surface to form a third layer of semiconductor material. Wherein the first region is not in contact with the second active structure.
It will be appreciated that taking the second insulating material as an example of the SiN material, after the first semiconductor material layer is removed, a layer of SiN material is deposited (e.g., physical vapor deposited) on the second surface of the second active structure and on the first surface in a region not contacting the isolated active structure (i.e., the first region), thereby forming a third semiconductor material layer. The third semiconductor material layer is not in contact with the isolated active structure, and the second active structure is wrapped by the third semiconductor material layer and the second semiconductor material layer together when the isolated active structure is exposed, so that the second active structure can be protected from being oxidized in the subsequent oxidation treatment process.
In some possible embodiments, after the step S107, the method may further include, without forming the first filling structure: removing the second semiconductor material layer and the third semiconductor material layer to expose the second active structure; a second transistor is formed based on the second active structure.
It can be appreciated that taking the second insulating material as an example of the SiN material, after the isolation dielectric structure is formed, the SiN material wrapped on the surface of the second active structure and the first surface of the first transistor is removed, so that the second active structure is exposed, and the subsequent preparation of the second transistor is facilitated.
In the following, a first transistor and a second transistor are taken as fin field effect transistors as examples, and a stacked transistor provided by an embodiment of the present application is described. Fig. 2 is a schematic diagram of a first structure of a stacked transistor according to an embodiment of the present application. In fig. 2, (a) is a design layout of the stacked transistor, and for convenience of understanding, only fin structures, gate structures, and source-drain structures are shown in the design layout; (b) A cut-away view of the stacked transistor along a cut-away direction (i.e., A-A') of the gate structure; (c) A cut-away view of the stacked transistor along a cut-away direction (i.e., the B-B' direction) of the source-drain structure; (d) A cut-away view of the stacked transistor is taken along the cut-away direction (i.e., the C-C' direction) of the fin structure.
Referring to fig. 2, the stacked transistor 10 includes a first transistor 11, a second transistor 12, and an isolation dielectric structure 13; wherein the first active structure 111 of the first transistor 11 and the second active structure 121 of the second transistor 12 are formed by the same process, the first transistor 11 and the second transistor 12 are self-aligned; the isolation dielectric structure 13 is used to isolate the first active structure 111 and the second active structure 121, and the isolation dielectric structure 13 is located between the first active structure 111 and the second active structure 121.
In the embodiment of the present application, since the first active structure 111 of the first transistor 11 and the second active structure 121 of the second transistor 12 are formed through the same etching process, self-alignment of the first transistor 11 and the second transistor 12 can be achieved.
The following describes the process of manufacturing the stacked transistor shown in fig. 2 in combination with the above manufacturing method. The stacked transistor shown in fig. 2 can be manufactured by the process shown in fig. 3A to 3F, and fig. 3A to 3F are schematic diagrams illustrating a first manufacturing process of the stacked transistor according to an embodiment of the present application.
In an example, taking the first transistor 11 and the second transistor 12 as fin field effect transistors as an example, the first manufacturing process of the stacked transistor 10 may include the following steps:
The first step: a substrate 21 such as a Si substrate is provided (see (a) in fig. 3A).
And a second step of: the substrate 21 is etched to form a plurality of fin structures 22, and a dielectric material is deposited on the plurality of fin structures 22 to form shallow trench isolation structures 23 (see (b) in fig. 3A).
Wherein, referring to (b) in fig. 3A, the fin structure 22 is composed of a first fin structure 221, a second fin structure 222, and an isolation active structure 223; the shallow trench isolation structure 23 is composed of a first portion 231 of the shallow trench isolation structure, a second portion 232 of the shallow trench isolation structure, and a shallow trench isolation layer 233.
And a third step of: removing the first portion 231 of the shallow trench isolation structure, exposing the first fin structure 221; then, a first dummy gate structure, a first spacer 112, a first source drain structure 113 and a first interlayer dielectric layer 114 in the first transistor 11 are sequentially formed according to standard steps; after the first dummy gate structure is removed, a first gate dielectric layer 115, a first gate structure 116, and a first metal interconnect layer 117 are formed (see (c) in fig. 3A).
Fourth step: an oxide is deposited over the first metal interconnect layer 117 forming a first insulating layer 14, the first insulating layer 14 being bonded to the carrier wafer 15. Next, the first transistor 11 after bonding the carrier wafer 15 is rewound so that the substrate 21 is placed upward (see (a) in fig. 3B).
Fifth step: the wafer thinning process is performed on the substrate 21 until the substrate 21 is removed, exposing the second fin structure 222 away from the surface of the first fin structure 221 (see (B) in fig. 3B).
Sixth step: a portion of the second fin structure 222 is removed by selective etching, forming a first groove 24 (see (c) in fig. 3B).
Seventh step: depositing SiN material (not shown) in the first recess 24 and on the second portion 232 of the shallow trench isolation structure, performing a CMP process on the deposited SiN material, and stopping the CMP process to the surface of the second portion 232 of the shallow trench isolation structure; after the CMP process, the first filling structure 25 is formed (see (a) in fig. 3C).
Eighth step: the second portion 232 of the shallow trench isolation structure is removed by etching, exposing the second fin structure 222 and the shallow trench isolation layer 233 (see (b) in fig. 3C).
In the embodiment of the present application, the shallow trench isolation layer 233 is used to isolate the first transistor 11 and the second transistor 12.
Ninth step: amorphous carbon is deposited on the shallow trench isolation layer 233 to form the first semiconductor material layer 31 (see (C) in fig. 3C).
Tenth step: an atomic layer deposition of a layer of SiN material is performed on the first semiconductor material layer 31 and the surface of the second fin structure 222 to form a second semiconductor material layer 32. Wherein, due to the first filling structure 25, the thickness of the SiN material on the surface of the second fin structure 222 away from the first fin structure 221 is larger than the thickness of the SiN material of the remaining surface (see (a) in fig. 3D).
Eleventh step: the SiN material on the surface of the second fin structure 222 remote from the first fin structure 221 and the first semiconductor material layer 31 is removed by anisotropic etching (see (b) in fig. 3D).
Twelfth step: the first semiconductor material layer 31 is removed by isotropic etching, exposing the isolation active structure 223 (see (c) in fig. 3D).
Thirteenth step: the isolation active structure 223 is oxidized to form an isolation dielectric structure 13 (see (a) in fig. 3E).
Fourteenth step: the SiN material on the surface of the second fin structure 222 is removed by isotropic etching (see (b) in fig. 3E).
Fifteenth step: a second dummy gate structure 128 of the second transistor 12 is formed using standard procedures (see (c) in fig. 3E).
Sixteenth step: the second spacer 122, the second source drain structure 123, and the second interlayer dielectric layer 124 in the second transistor 12 are sequentially prepared using standard steps (see (a) in fig. 3F).
Seventeenth step: removing the second dummy gate structure 128, exposing a gate region of the second transistor 12, depositing an insulating material at a junction of the gate region and the second fin structure 222 to form a second gate dielectric layer 125; a metal material is deposited in the gate region to form a second gate structure 126 (see (b) in fig. 3F).
Eighteenth step: a subsequent process treatment is performed on the second interlayer dielectric layer 124 to form a second metal interconnection layer 127 (see (c) in fig. 3F).
Thus far, the stacked transistor 10 in which the first transistor 11 and the second transistor 12 are fin field effect transistors and the first active structure 111 and the second active structure 121 are isolated by the isolation dielectric structure 13 is completed by the above-described first manufacturing method.
The manufacturing process shown in fig. 3A to 3F is only one example of the stacked transistors in the embodiment of the present application. The stacked transistor according to the embodiment of the present application may also be manufactured by the process shown in fig. 4A to 4D, and fig. 4A to 4D are schematic diagrams illustrating a second manufacturing process of the stacked transistor according to the embodiment of the present application.
In an example, taking the first transistor 11 and the second transistor 12 as fin field effect transistors as an example, the first manufacturing process of the stacked transistor 10 may include the following steps:
The first step: providing a substrate 21 (e.g., a Si substrate); forming a plurality of fin structures 22 and shallow trench isolation structures 23; forming a first transistor 11; the first transistor 11 after bonding the carrier wafer 15 is rewound so that the substrate 21 is placed upward; the substrate 21 is removed, exposing the second fin structure 222 away from the surface of the first fin structure 221 (see the first to fifth steps in the first fabrication process of the stacked transistor described above for a specific process) (see (a) in fig. 4A).
And a second step of: the second portion 232 of the shallow trench isolation structure is removed, exposing the second fin structure 222, isolating the shallow trench isolation layer 233 of the active structure 223 industry (see (b) in fig. 4A).
And a third step of: amorphous carbon is deposited on the shallow trench isolation layer 233 to form the first semiconductor material layer 31 (see (c) in fig. 4A).
Fourth step: an atomic layer deposition of a layer of SiN material is performed on the first semiconductor material layer 31 and the surface of the second fin structure 222 to form a second semiconductor material layer 32 (see (a) in fig. 4B).
Fifth step: the SiN material on the surface of the second fin structure 222 remote from the first fin structure 221 and the SiN material on the first semiconductor material layer 31 are removed by anisotropic etching (see (B) in fig. 4B).
Sixth step: the first semiconductor material layer 31 is removed by anisotropic etching (see (c) in fig. 4B).
Seventh step: a SiN material is deposited on the surface of the second fin structure 222 remote from the first fin structure 221 and on a portion of the area on the shallow trench isolation layer 233 (the area not in contact with the isolation active structure 223), forming a third semiconductor material layer 33 (see (a) in fig. 4C).
Eighth step: the exposed isolation active structure 223 is oxidized to form an isolation dielectric structure 13 (see (b) in fig. 4C).
Ninth step: the second semiconductor material layer 32 and the third semiconductor material layer 33 are removed to expose the second fin structure 222 (see (C) in fig. 4C).
Tenth step: formation of the second transistor 12 (see the fifteenth to seventeenth steps in the first fabrication of the stacked transistor described above for a specific process) (see FIG. 4D)
Thus, the stacked transistor 10 in which the first transistor 11 and the second transistor 12 are fin field effect transistors and the first active structure 111 and the second active structure 121 are isolated by the isolation dielectric structure 13 is completed by the second manufacturing method described above.
It should be noted that, when the stacked transistor is a fully-surrounding gate transistor, a planar transistor or a vertical transistor, the method for manufacturing the stacked transistor is the same as the method for manufacturing the stacked transistor as the fin field effect transistor in the above embodiment, and the embodiments of the present application will not be repeated.
In the embodiment of the application, the isolation medium structure is formed by oxidizing the isolation active structure between the first active structure and the second active structure, so that the isolation between the active region of the first transistor and the active region of the second transistor can be realized under the condition of not damaging the device structure.
Further, compared with the conventional ion implantation and isolation method using Silicon On Insulator (SOI), the method for preparing the isolation medium structure in the embodiment of the application is simpler in process, and meanwhile, the self-alignment problem of the first transistor and the second transistor is considered, so that the consistency of the active regions of the first transistor and the second transistor is ensured.
Further, the stacked transistor provided by the embodiment of the application can be detected by using a detection analysis instrument, for example: scanning electron microscope (scanning electron microscope, SEM), transmission electron microscope (transmission electron microscope, TEM), scanning transmission electron microscope (scanning transmission electron microscopy, STEM), and the like. Taking TEM as an example, the stacked transistor provided in the embodiment of the present application may detect an isolation medium structure located between the first active structure and the second active structure by using a TEM slicing manner.
In embodiments of the present application, the isolation medium structure may be not rectangular, but elliptical or other shapes, which are not particularly limited in embodiments of the present application. And the growth quality of the material of the isolation medium structure (i.e., siO x) may be observed to be non-uniform by TEM sectioning.
An embodiment of the present application provides a semiconductor device including: stacked transistors as in the above embodiments. For specific limitation of the stacked transistor, reference may be made to the stacked transistor shown in fig. 2 and will not be described herein.
An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device includes the above-described stacked transistor. For specific limitation of the stacked transistor, reference may be made to the stacked transistor shown in fig. 2 and will not be described herein.
In the description of the present application, a description of the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (13)
1. A method of fabricating a stacked transistor, the method comprising:
Sequentially stacking a first active structure, an isolated active structure and a second active structure on a substrate;
Forming a first transistor based on the first active structure;
Depositing a first insulating material on a first surface of the first transistor facing the second active structure to form a first semiconductor material layer; the first semiconductor material layer surrounds the isolated active structure;
depositing a second insulating material over the second active structure and the first layer of semiconductor material to form a second layer of semiconductor material; the second semiconductor material layer wraps the second active structure;
Removing a portion of the second layer of semiconductor material overlying the first layer of semiconductor material to expose the first layer of semiconductor material;
Removing the first semiconductor material layer to expose the isolated active structure;
oxidizing the isolated active structure to form an isolated medium structure;
removing a portion of the second semiconductor material layer overlying the second active structure to expose the second active structure;
A second transistor is formed based on the second active structure.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
Before the forming the first transistor based on the first active structure, the method further includes: depositing a dielectric material on the first active structure, the isolation active structure and the second active structure to form a shallow trench isolation structure; the shallow trench isolation structure wraps the first active structure, the isolation active structure and the second active structure; removing a first portion of the shallow trench isolation structure to expose the first active structure;
before the forming the second transistor based on the second active structure, the method further includes: and rewinding and removing the substrate.
3. The method of claim 2, wherein after the rewinding and removing the substrate, prior to forming the first layer of semiconductor material, the method further comprises:
Removing a portion of the second active structure away from the first active structure to form a first recess;
depositing the second insulating material in the first recess to form a first filling structure;
And removing a second portion of the shallow trench isolation structure to expose the second active structure and the isolated active structure.
4. The method of claim 3, wherein the removing a portion of the second layer of semiconductor material that covers the first layer of semiconductor material to expose the first layer of semiconductor material comprises:
A portion of the second layer of semiconductor material overlying the first layer of semiconductor material and a portion of the second layer of semiconductor material overlying the first fill structure are removed to expose the first layer of semiconductor material and the first fill structure.
5. The method of claim 4, wherein after said oxidizing said isolated active structure to form an isolated dielectric structure, said method further comprises:
Removing the first filling structure and the second semiconductor material layer to expose the second active structure;
the second transistor is formed based on the second active structure.
6. The method of claim 2, wherein the removing a portion of the second layer of semiconductor material that covers the first layer of semiconductor material to expose the first layer of semiconductor material comprises:
removing a portion of the second layer of semiconductor material overlying the first layer of semiconductor material and a portion of the second layer of semiconductor material overlying the second surface of the second active structure to expose the first layer of semiconductor material and the second surface; the second surface is a surface of the second active structure remote from the first active structure.
7. The method of claim 6, wherein after said removing said first layer of semiconductor material to expose said isolated active structure, said method further comprises:
depositing a second insulating material over the second surface and the first region of the first surface to form a third layer of semiconductor material; the first region is not in contact with the second active structure.
8. The method of claim 7, wherein after said oxidizing said isolated active structure to form an isolated dielectric structure, said method further comprises:
removing the second semiconductor material layer and the third semiconductor material layer to expose the second active structure;
the second transistor is formed based on the second active structure.
9. The method of claim 1, wherein forming the first transistor based on the first active structure comprises:
Forming a first pseudo gate structure, a first spacer, a first source drain structure and a first interlayer dielectric layer of a first transistor in sequence based on the first active structure;
Removing the first dummy gate structure and forming a first gate structure and a first gate dielectric layer;
and carrying out subsequent process treatment on the first interlayer dielectric layer to form a first metal interconnection layer.
10. The method of claim 1, wherein the forming the second transistor based on the second active structure comprises:
forming a second pseudo gate structure, a second spacer, a second source drain structure and a second interlayer dielectric layer of the second transistor in sequence based on the second active structure;
removing the second dummy gate structure and forming a second gate structure and a second gate dielectric layer;
And carrying out subsequent process treatment on the second interlayer dielectric layer to form a second metal interconnection layer.
11. A stacked transistor, the stacked transistor comprising:
A first transistor;
A second transistor; the first active structure of the first transistor and the second active structure of the second transistor are formed by the same process, the first transistor and the second transistor being self-aligned;
And the isolation medium structure is used for isolating the first active structure and the second active structure, and is positioned between the first active structure and the second active structure.
12. A semiconductor device, comprising: the stacked transistor of claim 11.
13. An electronic device, comprising: a circuit board and the semiconductor device according to claim 12, the semiconductor device being provided to the circuit board.
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