CN118352305A - Interconnection method of stacked transistor, stacked transistor and semiconductor device - Google Patents

Abstract

The application provides an interconnection method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the following steps: forming an active structure on a semiconductor substrate; removing the first portion of the active structure by a cutting process to expose the semiconductor substrate in the double diffusion isolation region; the double diffusion isolation region is positioned at one side of the second part of the active structure; forming a double diffusion isolation structure on the semiconductor substrate in the double diffusion isolation region; forming a first transistor and a second transistor self-aligned along a first direction based on the second portion of the active structure that is left, and a single diffusion isolation structure; the single diffusion isolation structure is positioned on the same side of the first transistor and the second transistor and is opposite to the double diffusion isolation structure; etching the double diffusion isolation structure to form a first groove, and filling metal materials in the first groove to form an interconnection through hole structure; the interconnection through hole structure is used for communicating the first metal interconnection layer of the first transistor with the second metal interconnection layer of the second transistor.

Description

Interconnection method of stacked transistor, stacked transistor and semiconductor device

Technical Field

The present application relates to the field of integrated circuits, and more particularly, to a stacked transistor interconnection method, a stacked transistor, and a semiconductor device.

Background

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors further increase transistor integration density by integrating two or more layers of transistors in vertical space is one of the important technologies continuing the scaling of integrated circuits.

In some schemes for fabricating stacked transistors (stacked transistor), in order to achieve inter-layer interconnection between upper and lower layers of transistors, it is necessary to provide field regions inside standard transistor cells to form a field region direct structure. However, this increases the area of standard transistor cells, which is detrimental to the miniaturization of integrated circuits.

Disclosure of Invention

The application provides an interconnection method of a stacked transistor, the stacked transistor and a semiconductor device, which are used for forming an interconnection through hole structure for connecting an upper layer transistor and a lower layer transistor by utilizing the position of a double diffusion isolation structure in a standard transistor unit, thereby solving the problem of area occupation caused by independently setting a field region and effectively improving the integration level of the stacked transistor.

In a first aspect, an embodiment of the present application provides a method for interconnecting stacked transistors, including: forming an active structure on a semiconductor substrate; removing the first portion of the active structure by a cutting process to expose the semiconductor substrate in the double diffusion isolation region; the double diffusion isolation region is positioned at one side of the second part of the active structure; forming a double diffusion isolation structure on the semiconductor substrate in the double diffusion isolation region; forming a first transistor and a second transistor self-aligned along a first direction based on the second portion of the active structure that is left, and a single diffusion isolation structure; the single diffusion isolation structure is positioned on the same side of the first transistor and the second transistor and is opposite to the double diffusion isolation structure; the first direction is perpendicular to the extending direction of the active structure; etching the double diffusion isolation structure to form a first groove, and filling metal materials in the first groove to form an interconnection through hole structure; the interconnection through hole structure is used for communicating the first metal interconnection layer of the first transistor with the second metal interconnection layer of the second transistor.

In some possible embodiments, forming a first transistor and a second transistor self-aligned along a first direction based on a second portion of the active structure that is left, and a single diffusion isolation structure comprising: forming a first transistor and a first single diffusion isolation structure based on a third portion of the second portion of the active structure; rewinding the first transistor and removing the semiconductor substrate to expose a fourth portion of the second portion of the active structure; the second transistor and the second single diffusion isolation structure are formed based on a fourth portion of the second portions of the active structure.

In some possible embodiments, after forming the first transistor and the first single diffusion isolation structure based on a third portion of the second portion of the active structure, the method further comprises: forming a first metal interconnection layer on the first transistor and the first single diffusion isolation structure; etching the double diffusion isolation structure to form a first groove, comprising: coating photoresist on the upper side of the second transistor to form a photoresist layer, wherein the photoresist layer covers the area except the double diffusion isolation area; and etching the first transistor and the second transistor by taking the photoresist layer as a mask until the first metal interconnection layer to form a first groove.

In some possible embodiments, after filling the first recess with the metal material to form the interconnect via structure, the method further comprises: a second metal interconnect layer is formed over the second transistor and the second single diffusion isolation structure.

In some possible embodiments, forming the first transistor and the first single diffusion isolation structure based on a third portion of the second portion of the active structure comprises: forming a first source-drain structure based on a third portion of the active structure, and a plurality of first gate structures alternately arranged with the first source-drain structure along a second direction; the second direction is parallel to the extending direction of the active structure; etching a third gate structure far away from the double-diffusion isolation region in the plurality of first gate structures and a third part of the active structure corresponding to the third gate structure to form a second groove; wherein, other structures except the third gate structure and the first source drain structure in the plurality of first gate structures form a first transistor; and filling insulating materials in the second grooves to form the first single-diffusion isolation structure.

In some possible embodiments, forming the second transistor and the second single diffusion isolation structure based on a fourth portion of the second portions of the active structure includes: forming a second source-drain structure based on the fourth portion of the active structure, and a plurality of second gate structures alternately arranged with the second source-drain structure along the second direction; etching a fourth grid structure far away from the double-diffusion isolation region in the plurality of second grid structures and an active structure corresponding to the fourth grid structure until the first single-diffusion isolation structure is exposed to form a third groove; wherein, other structures except the fourth gate structure and the second source drain structure in the plurality of second gate structures form a second transistor; and filling an insulating material in the third groove to form a second single diffusion isolation structure.

In some possible embodiments, filling a metal material in the first recess to form an interconnect via structure includes: depositing an insulating material on the inner wall of the first groove to form an isolation layer; and filling a metal material in the first groove to form an interconnection through hole structure, wherein the interconnection through hole structure is isolated from the active structure through an isolation layer.

In some possible embodiments, forming a double diffusion isolation structure on a semiconductor substrate within the double diffusion isolation region comprises: depositing an oxide material on the semiconductor substrate in the double-diffusion isolation region to form a shallow trench isolation structure, wherein the height of the shallow trench isolation structure is lower than that of the active structure; depositing an insulating material over the shallow trench isolation structure to form a first double diffusion isolation structure; rewinding the first double-diffusion isolation structure and removing the semiconductor substrate in the double-diffusion isolation region; thinning the shallow trench isolation structure to a preset height; and depositing an insulating material on the thinned shallow trench isolation structure to form a second double-diffusion isolation structure.

In a second aspect, an embodiment of the present application provides a stacked transistor including: a first transistor; a second transistor, the first transistor and the second transistor being stacked in a first direction; the first direction is perpendicular to the extending direction of the active structure; in the second direction, a double diffusion isolation structure is arranged on the first side of the first transistor and the second transistor, and a single diffusion isolation structure is arranged on the second side of the first transistor and the second transistor; the first direction is perpendicular to the second direction; an interconnection through hole structure is formed in the double diffusion isolation structure; the interconnection through hole structure is used for communicating the first metal interconnection layer of the first transistor with the second metal interconnection layer of the second transistor.

In a third aspect, an embodiment of the present application provides a semiconductor device including: stacked transistors as in the above embodiments.

In the embodiment of the application, the first part of the active structure is removed through a cutting process, so that a gap is formed between adjacent stacked transistor units, and a double-diffusion isolation structure is formed by the gap, so that the stacked transistor units are electrically isolated from the adjacent stacked transistor units on one side; by forming a single diffusion isolation structure opposite to the double diffusion isolation structure, the stacked transistor unit is electrically isolated from the adjacent stacked transistor unit on the other side, so that the stacked transistor has good electrical isolation performance. Further, by forming the interconnection through hole structure in the double-diffusion isolation structure, the characteristic that the area of the double-diffusion isolation structure is large is fully utilized, on one hand, the width of the interconnection through hole structure is increased, the resistance of the interconnection structure is reduced, and the conductivity of the stacked transistor is improved; on the other hand, the precision requirement when the interconnection through hole is formed by photoetching is reduced, and the preparation difficulty is greatly reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic diagram of a first structure of a stacked transistor in an embodiment of the application;

FIG. 2 is a schematic diagram of a second structure of a stacked transistor according to an embodiment of the present application;

FIG. 3 is a schematic flow chart of a method for manufacturing a stacked transistor according to an embodiment of the present application;

fig. 4 to 18 are schematic views showing a process of manufacturing a stacked transistor according to an embodiment of the present application;

fig. 19 is a schematic diagram of a third structure of a stacked transistor in an embodiment of the application.

The figures above: 10. stacking transistors; 101. a field region; 102. a field direct connection structure; 11. a first transistor; 12. two transistors; 13. a double diffusion isolation structure; 131. a first double diffusion isolation structure; 132. a second double diffusion isolation structure; 14. a single diffusion isolation structure; 141. a first single diffusion isolation structure; 142. a second single diffusion isolation structure; 15. an interconnect via structure; 16. standard cell boundaries; 17. a double diffusion isolation region; 18. a single diffusion isolation region; 111. a first metal interconnect layer; 112. a first source drain structure; 113. a first interlayer dielectric layer; 114. a first gate structure; 114a, a third gate structure; 115. a first source drain metal; 121. a second metal interconnect layer; 122. a second source drain structure; 123. a second interlayer dielectric layer; 124. a second gate structure; 124a, fourth gate structure; 125. a second source drain metal; 20. a semiconductor substrate; 21. a fin structure; 22. shallow trench isolation structures; 23. a first dummy gate structure; 24. a first side wall; 25. a first source drain groove; 26. an isolation layer; 27. a second groove; 28. a first insulating layer; 29. a carrier wafer.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits.

In one embodiment, the fabrication process of the stacked transistor (stacked transistors) has two schemes, a single-chip scheme and a sequential scheme.

In the first approach, N-channel field effect transistors (N FIELD EFFECT transistors, NFETs) and P-channel field effect transistors (P FIELD EFFECT transistors, PFETs) are fabricated on the same substrate, and wafer bonding techniques are not used. This determines that the same layer transistors must be of the same type, i.e., NFET or PFET. And the transistors on the upper layer and the lower layer are strictly in the same plane space, and no alignment deviation exists. The advantage of this solution is a better integration density. Drawbacks of this approach include the following two points: (1) The process is complex, and a large number of process technologies need to be developed and optimized; (2) Each layer of transistors has a fixed polarity, and two layers of transistors must be relied upon to form a basic Complementary Metal Oxide Semiconductor (CMOS) circuit, which has poor design flexibility.

The second scheme is based on wafer bonding and layer-by-layer processing. Specifically, the two transistors are stacked vertically by bonding a wafer on top of the fabricated lower transistor to prepare the upper transistor. However, this approach requires tight temperature control during the thermal process of processing the upper layer transistors, avoiding affecting the lower layer transistors and the interconnect lines. The scheme has the advantages that the device structure, the channel crystal orientation and even the channel material adopted by the upper layer transistor and the lower layer transistor can be correspondingly optimized to obtain better and more matched device performance due to wafer bonding.

In order to solve the technical problems of the two schemes, a self-aligned stacked transistor is provided, active regions of upper and lower homologous transistors are formed by etching, and the stacked transistor is manufactured on the front and back sides of a wafer by rewinding, so as to overcome the defects of the two schemes.

However, in some schemes for fabricating stacked transistors (stacked transistor), in order to implement interlayer interconnection between upper and lower layers of transistors, it is necessary to provide a field region inside a standard transistor cell to form a field region direct connection structure.

Fig. 1 is a schematic diagram illustrating a first structure of a stacked transistor according to an embodiment of the present application. In fig. 1, a top view of the stacked transistor is shown, and for ease of understanding, only fin structures, gate structures, source-drain structures, and field direct structures are shown in the top view; fig. 1 (b) is a cross-sectional view taken along the direction of a broken line A-A' in fig. 1 (a); fig. 1 (c) is a cross-sectional view taken along the direction of a broken line B-B' in fig. 1 (a).

Referring to fig. 1, the area within the dashed box is a field region 101 of the stacked transistor, and a field region direct connection structure 102 is formed in the field region 101. The cross-layer connection of the stacked transistors is achieved by field direct connection structure 102. However, when the field direct connection structure 102 is formed, a field region is formed in the standard transistor by a fin cutting process, and the new field region increases the area of the standard transistor unit, which is not beneficial to the size reduction of the integrated circuit. In addition, interlayer interconnection cannot be realized for an area outside the standard transistor cell, and thus the length of the subsequent metal line cannot be optimized according to the result of the layout wiring.

In order to solve the technical problems, the embodiment of the application provides an interconnection method of stacked transistors, so as to form an interconnection through hole structure for connecting an upper layer transistor and a lower layer transistor by utilizing the position of a double diffusion isolation structure in a standard transistor unit, thereby solving the problem of area occupation caused by independently setting a field region and effectively improving the integration level of the stacked transistors.

Fig. 2 is a schematic diagram of a second structure of a stacked transistor in an embodiment of the application. In fig. 2 (a) is a top view of the stacked transistor, it should be noted that, for ease of understanding, only fin structures, gate structures, source-drain structures, metal interconnection structures, interconnection via structures, double diffusion isolation structures, and single diffusion isolation structures are shown in the top view; fig. 2 (b) is a cross-sectional view taken along the direction of the broken line A-A' in fig. 2 (a); fig. 2 (c) is a cross-sectional view taken along the direction of a broken line B-B' in fig. 2 (a).

Referring to (b) and (c) in fig. 2, the stacked transistor 10 includes: the first transistor 11 and the second transistor 12 are stacked in the first direction, and the first transistor 11 and the second transistor 12 are disposed. Wherein the first direction is perpendicular to the extending direction of the active structure.

For example, when the active structure is a fin structure, the first direction is the same as the height direction from the bottom to the top of the fin structure.

It will be appreciated that the first transistor 11 and the second transistor 12 are self-aligned stacked transistors 10, i.e. the first active structure in the first transistor 11 and the second active structure in the second transistor 12 may be formed using the same active structure.

In the embodiment of the present application, in the second direction, the double diffusion isolation structure 13 may be disposed at the first sides of the first transistor 11 and the second transistor 12, and the single diffusion isolation structure 14 may be disposed at the second sides of the first transistor 11 and the second transistor 12.

Here, the first direction is perpendicular to the second direction, which may be the same as the extension (length) direction of the active structure.

It is understood that the first transistor 11 may be a lower transistor in the stacked transistor 10 and the second transistor 12 may be an upper transistor in the stacked transistor 10. On both sides of the first transistor 11 and the second transistor 12, a double diffusion isolation structure 13 and a single diffusion isolation structure 14 may be formed, respectively. Wherein both double diffusion isolation structures 13 and single diffusion isolation structures 14 may be used to isolate adjacent two stacked transistors 10.

It can be appreciated that the double diffusion isolation structure 13 and the single diffusion isolation structure 14 are respectively disposed at two sides of the standard stacked transistor unit formed by the first transistor 11 and the second transistor 12, so that a new isolation scheme of the stacked transistor unit can be provided, and flexibility of isolation between adjacent stacked transistor units is effectively improved.

It should be noted that the manufacturing process of the double diffusion isolation structure 13 and the single diffusion isolation structure 14 is different. The double diffusion isolation structure 13 may be formed by removing the active structure at the boundary of the standard stacked transistor cell; the single diffusion isolation structure 14 may be formed by removing the gate structure at the boundary of the standard stacked transistor cell, refilling with insulating material.

In some embodiments, an interconnect via structure 15 is formed in the double diffusion isolation structure 13. The interconnect via structure 15 is used to communicate the first metal interconnect layer 111 of the first transistor 11 with the second metal interconnect layer 121 of the second transistor 12.

It can be understood that the interconnect through hole structure is manufactured in the double diffusion isolation structure 13, so that the characteristic that the area occupied by the double diffusion isolation structure 13 is larger can be utilized, on one hand, the width of the interconnect through hole structure is increased, the resistance of the interconnect structure is reduced, and the conductivity of the stacked transistor is improved; on the other hand, the precision requirement when the interconnection through hole is formed by photoetching is reduced, and the preparation difficulty is greatly reduced.

The transistor cell in the embodiment of the present application may be referred to as a hybrid cell (hybrid cell), that is, the double diffusion isolation structure 13 is formed on one side, and the interconnection via structure is fabricated in the double diffusion isolation structure 13, and the single diffusion isolation structure 14 is formed on the other side. Referring to fig. 2 (a), standard cell boundaries 16 of hybrid standard cells can be seen. And, one side of the hybrid standard cell is a double diffusion isolation region 17 forming a double diffusion isolation structure 13, and the other side is a single diffusion isolation region 18 forming a single diffusion isolation structure 14. Wherein the double diffusion isolation region 17 is larger than the single diffusion isolation region 18, it occupies 1/2 the area of the contact gate pitch (contact poly pitch, CPP).

It can be appreciated that the hybrid standard cell scheme can save 1/2CPP area without sacrificing one CPP to form a field direct structure, compared to the scheme where single diffusion isolation structures 14 are prepared on both sides; similarly, compared with the scheme that double diffusion isolation structures 13 are prepared on two sides of the mixed standard unit scheme, the mixed standard unit scheme has certain advantages in the aspect of improving the integration level because the double diffusion isolation structure 13 on one side is changed into a single diffusion isolation structure 14, and the area of 1/2CPP can be saved.

Fig. 3 is a schematic flow chart of an implementation of a method for manufacturing a stacked transistor 10 according to an embodiment of the present application, and referring to fig. 3, the method for manufacturing a stacked transistor 10 may include:

S301: forming an active structure on a semiconductor substrate;

S302: removing the first portion of the active structure by a cutting process to expose the semiconductor substrate in the double diffusion isolation region; the double diffusion isolation region is positioned at one side of the second part of the active structure;

s303: forming a double diffusion isolation structure on the semiconductor substrate in the double diffusion isolation region;

S304: forming a first transistor and a second transistor self-aligned along a first direction based on the second portion of the active structure that is left, and a single diffusion isolation structure; the single diffusion isolation structure is positioned on the same side of the first transistor and the second transistor and is opposite to the double diffusion isolation structure; the first direction is perpendicular to the extending direction of the active structure;

s305: etching the double diffusion isolation structure to form a first groove, and filling metal materials in the first groove to form an interconnection through hole structure; the interconnection through hole structure is used for communicating the first metal interconnection layer of the first transistor with the second metal interconnection layer of the second transistor.

It should be noted that the steps shown in fig. 3 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations; the steps shown in fig. 3 can be sequentially adjusted according to actual requirements.

Fig. 4 to 18 are schematic views showing a manufacturing process of a stacked transistor 10 according to an embodiment of the present application, and for convenience of understanding, fig. 4 to 18 show a cross-sectional view along a dotted line A-A 'in fig. 2, and fig. 4 to 18 show a cross-sectional view along a dotted line B-B' in fig. 2; the method for manufacturing the stacked transistor 10 and the manufactured stacked transistor 10 according to the embodiments of the present application will be described in the following with reference to fig. 2 to 18.

In step S301, an active structure is formed on a semiconductor substrate 20.

Referring to fig. 4, a semiconductor substrate 20 is provided. The semiconductor substrate 20 may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, or the like. Next, a number of active structures upstanding from the semiconductor substrate may be formed on the semiconductor substrate 20.

Illustratively, the active structure shown in fig. 4 is a fin structure 21.

In some embodiments, when the stacked transistor 10 is a finfet, the S301 may include: fin structures 21 are formed on the semiconductor substrate 20.

In one embodiment, forming fin structure 21 on semiconductor substrate 20 includes: forming a semiconductor epitaxial layer on the surface of the semiconductor substrate 20 through an epitaxial growth process; the semiconductor epitaxial layer is etched to a depth into the semiconductor epitaxial layer or to the semiconductor substrate surface or to a depth into the substrate, thereby forming a plurality of fin structures 21.

In other embodiments, when the stacked transistor 10 is a fully-around gate transistor, the step S301 may include: the substrate is etched to form a columnar structure, wherein the substrate may be formed of alternately deposited silicon layers and silicon germanium layers.

In still other embodiments, when the stacked transistor 10 is a planar transistor, the S301 may include: and etching the substrate to form a block structure.

In the embodiment of the present application, since the stacked transistor 10 includes two transistors, and the first active structure of the first transistor 11 and the second active structure of the second transistor 12 are formed by the same etching process, a larger etching depth may be used in etching the semiconductor substrate 20. For example, the height of the etched fin structures 21 (which may also be columnar structures or bulk structures) may be greater than 100nm. It should be noted that the height of the fin structure 21 may be set according to practical situations, which is not particularly limited in the embodiment of the present application.

In step S302, a first portion of the active structure is removed using a cutting process to expose the semiconductor substrate 20 within the double diffusion isolation zone 17.

It will be appreciated that the active structure comprises: the first portion and the second portion may remain after the first portion of the active structure is cut away. The double diffusion isolation zone 17 is located on one side of the second portion of the active structure.

Referring to fig. 5, after forming fin structure 21 on semiconductor substrate 20, a fin cutting process may be used to remove a first portion of fin structure 21 located within double diffusion isolation region 17 to expose semiconductor substrate 20 within double diffusion isolation region 17.

Wherein, referring to the cross-sectional view in the A-A' direction, the fin structure 21 in the double diffusion isolation region 17 has been cut away. Referring to the cross-sectional view in the B-B' direction, the double diffusion isolation regions 17 are located partially on a first side of the standard cell boundary 16 and partially on a second side of the standard cell boundary 16 such that the double diffusion isolation structures 13 occupy a portion of the area inside the hybrid standard cell and also occupy a portion of the area outside the hybrid standard cell.

In some embodiments, referring to fig. 6, after the fin-cutting process is performed, the semiconductor substrate 20 within the double diffusion isolation regions 17 is exposed. Oxide material may be deposited on the semiconductor substrate 20 within the double diffusion isolation regions 17 to form shallow trench isolation structures 22 (shallow trench isolation, STI).

Wherein the shallow trench isolation structure 22 has a lower height than the fin structure 21.

Here, the oxide material forming the shallow trench isolation structure 22 may be any one of the following: silicon dioxide (SiO ₂) or silicon oxycarbide (SiCO), and the like.

It should be noted that, in the region other than the double diffusion isolation region 17, the shallow trench isolation structure 22 may be formed by deposition, so as to fill the shallow trench isolation structure 22 in the trench formed by the fin structure 21. Also, the shallow trench isolation structure 22 may wrap around a portion of the fin structure 21 proximate to the semiconductor substrate 20 to expose a portion of the fin structure 21 distal from the semiconductor substrate 20. The first transistor 11 and the first single diffusion isolation structure 141 may be formed in a subsequent step based on a portion of the fin structure 21 remote from the semiconductor substrate 20; after rewinding, the second transistor 12 and the second single diffusion isolation structure 142 are formed based on a portion of the fin structure 21 near the semiconductor substrate 20, so as to realize the preparation of the stacked transistor 10 in the embodiment of the present application.

In step S303, a double diffusion isolation structure 13 is formed on the semiconductor substrate 20 within the double diffusion isolation region 17.

It will be appreciated that double diffusion isolation structures 13 may be formed by depositing an insulating material over double diffusion isolation regions 17.

The insulating material may be silicon oxide, silicon nitride, aluminum oxide, or the like.

In some embodiments, the double diffusion isolation structure 13 comprises: a first double diffusion isolation structure 131 and a second double diffusion isolation structure 132. Wherein, the method of forming the first and second double diffusion isolation structures 131 and 132 may include: an insulating material is deposited over the shallow trench isolation structures 22 to form first double diffusion isolation structures 131. Rewinding the first double diffusion isolation structure 131 and removing the semiconductor substrate 20 in the double diffusion isolation region 17; thinning the shallow trench isolation structure 22 to a predetermined height; an insulating material is deposited over the thinned shallow trench isolation structures 22 to form second double diffusion isolation structures 132.

It is understood that the double diffusion isolation structure 13 may be formed by forming the first double diffusion isolation structure 131, forming the second double diffusion isolation structure 132 after rewinding. It will be appreciated that the above manner of forming the first double diffusion isolation structure 131 and the second double diffusion isolation structure 132 on the front and back sides of the wafer by the reverse implementation may be adapted to the scheme of forming the first transistor 11 and the second transistor 12 on the front and back sides of the wafer by the reverse implementation, so that the manufacturing process may be performed synchronously. That is, step S303 may be performed simultaneously with step S304, so that the first transistor 11 and the first double diffusion isolation structure 131 may be formed simultaneously, and the second transistor 12 and the second double diffusion isolation structure 132 may be formed simultaneously after rewinding.

Wherein the first double diffusion isolation structure 131 may isolate the first transistor 11 of the stacked transistor 10 from transistors in an adjacent stacked transistor; the second double diffusion isolation structure 132 may isolate the second transistor 12 of the stacked transistor 10 from transistors in an adjacent stacked transistor.

In step S304, the first transistor 11 and the second transistor 12, which are self-aligned in the first direction, and the single diffusion isolation structure 14 are formed based on the second portion of the active structure that is left.

Wherein the first direction is perpendicular to the extending direction of the active structure. The single diffusion isolation structure is located on the same side of the first transistor 11 and the second transistor 12 and is opposite to the double diffusion isolation structure 13.

It will be appreciated that the formation of the first transistor 11 and the second transistor 12 on the front and back sides of the wafer, respectively, may be achieved by a flip-chip technique based on the second portion of the active structure that is left. Meanwhile, the single diffusion isolation structure 14 distant from the double diffusion isolation structure 13 may also be formed based on the gate structure formed during the formation of the first transistor 11 and the second transistor 12, such that the first side of the first transistor 11 and the second transistor 12 is formed with the double diffusion isolation structure 13 and the second side is formed with the single diffusion isolation structure 14.

In some embodiments, the single diffusion barrier structure 14 may include: a first single diffusion isolation structure 141 and a second single diffusion isolation structure 142. Forming the first transistor 11 and the second transistor 12 self-aligned in the first direction based on the second portion of the active structure that is left, and the single diffusion isolation structure 14, comprising: forming a first transistor 11 and a first single diffusion isolation structure 141 based on a third portion of the second portion of the active structure; rewinding the first transistor and removing the semiconductor substrate 20 to expose a fourth portion of the second portion of the active structure; the second transistor 12 and the second single diffusion isolation structure 142 are formed based on a fourth portion of the second portion of the active structure.

It is understood that the first portion of the fin structure may be etched in step S302, thereby leaving the second portion of the fin structure. The second portion of the fin structure may be divided into a third portion and a fourth portion, wherein the fourth portion is closer to the semiconductor substrate 20 than the third portion. The first transistor 11 and the first single diffusion isolation structure 141 may be formed based on the third portion of the fin structure, and the second transistor 12 and the second single diffusion isolation structure 142 may be formed based on the fourth portion of the fin structure after rewinding.

In an embodiment, forming the first transistor 11 and the first single diffusion isolation structure 141 based on the third portion of the second portion of the active structure includes: forming a first source-drain structure 112 and a plurality of first gate structures 114 alternately arranged with the first source-drain structure 112 along the second direction based on the third portion of the active structure; etching a third gate structure 114a of the plurality of first gate structures 114 that is remote from the double diffusion isolation region 17 and a third portion of the active structure corresponding to the third gate structure 114a to form a second recess 27; wherein the first source-drain structure 112 and other structures except the third gate structure 114a in the plurality of first gate structures 114 constitute the first transistor 11; an insulating material is filled in the second recess 27 to form a first single diffusion isolation structure 141.

It is appreciated that after forming the first source drain structure 112 and the plurality of first gate structures 114, the first single diffusion isolation structure 141 may be formed using a third gate structure 114a of the plurality of first gate structures 114 that is remote from the double diffusion isolation region 17. The first single diffusion isolation structure 141 is formed by depositing an insulating material after removing the third gate structure 114a and the third portion (upper half) of the fin structure 21 at the bottom of the third gate structure 114 a.

Referring to fig. 7, after the shallow trench isolation structure 22 is formed, a plurality of spaced apart first dummy gate structures 23 may be deposited in a second direction using standard processes for semiconductor fabrication. And forming a first side wall 24 on the side wall of each first pseudo gate structure 23 through a side wall process, so as to prevent the side wall of the first pseudo gate structure 23 from being damaged in the subsequent preparation process. Subsequently, a first source-drain recess 25 may be formed based on the fin structure 21 between two adjacent dummy gate structures.

Here, the material forming the first dummy gate structure 23 may be polysilicon, amorphous silicon, germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), or the like. The material forming the first sidewall 24 may be a multi-layer material such as silicon oxide, silicon nitride or silicon oxide-silicon nitride-silicon oxide.

Here, the process of forming the first source-drain recess 25 may be selected according to practical requirements, which is not particularly limited in the embodiment of the present application.

Illustratively, the first source-drain recess 25 of the first transistor 11 may be formed on the fin structure 21 using a fin structure deep etch (FIN RECESS) process.

It should be noted that, for convenience of description, the first source-drain groove in the embodiment of the present application is referred to as simply, and specifically refers to the first source groove and/or the first drain groove. In addition, the first source-drain structure, the second source-drain structure, the first source-drain metal, the second source-drain metal, and the like are similar to the first source-drain groove, wherein "source-drain" is abbreviated as "source and/or drain".

Referring to fig. 8, a first source drain structure 112 may be formed based on the first source drain recess 25, and a dielectric layer material may be deposited over the first source drain structure 112 to form a first interlayer dielectric layer 113. The top of the first interlayer dielectric layer 113 is level with the top of the first dummy gate structure 23.

For example, a strained material such as sige or sic may be formed in the first source-drain recess 25 by selective epitaxial growth using the first sidewall 24 as a mask to fill the first source-drain recess 25, and then the first source-drain structure 112 may be formed on the strained material by a heavily doping process.

The dielectric layer material forming the first interlayer dielectric layer 113 has a high insulating property. A dielectric layer material is deposited within the double diffusion isolation regions 17 to form first double diffusion isolation structures 131.

The method of forming the first interlayer dielectric layer 113 is chemical vapor deposition or high aspect Ratio trench filling (HIGH ASPECT Ratio Process, HARP). The use of HARP may increase the isolation effect of the first interlayer dielectric layer 113.

Referring to fig. 9, a patterned mask layer (not shown) is formed on the first interlayer dielectric layer 113, and the first dummy gate structure 23 is etched using the patterned mask layer until an opening is formed. And an insulating material and a metal material are deposited in the openings to form first gate structures 114 on both sides of the first interlayer dielectric layer 113, respectively, in the second direction.

In one embodiment, the first gate structure 114 includes: a first gate dielectric layer and a first gate electrode layer. The materials of the first gate dielectric layer and the first gate electrode layer may be set according to actual requirements, which is not particularly limited in the embodiment of the present application.

By way of example, the first gate dielectric layer may be formed of a silicon oxide layer plus a K-value hafnium oxide layer, and the thickness of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

By way of example, the first gate electrode layer may be composed of multiple layers of electrode materials, each layer of electrode material including, but not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

In an example, the first gate dielectric layer may include: a 0.6nm silicon oxide layer and a 1.7nm hafnium oxide layer.

Referring to fig. 10, the first interlayer dielectric layer 113 in the first transistor 11 is etched to form a source drain metal recess, and a metal material is deposited in the source drain metal recess to form a first source drain metal 115. Here, the top surface of the first source drain metal 115 is flush with the top surface of the first interlayer dielectric layer 113.

Referring to fig. 11, a third gate structure 114a is defined in the plurality of first gate structures 114 away from the double diffusion isolation region 17, and then the third gate structure 114a and a third portion of the fin structure 21 at the bottom of the third gate structure 114a are etched so that the second recess 27 is formed.

Referring to fig. 12, an insulating material may be deposited in the second recess 27, and the deposited insulating material may be treated using a polishing process or a chemical mechanical planarization process such that a top surface of the first single diffusion barrier structure 141 formed of the insulating material is flush with a top surface of the first source drain metal 115.

Referring to fig. 13, after the first single diffusion isolation structure 141, the first source drain structure 112, the first gate structure 114, and the first double diffusion isolation structure 131 are completed, a subsequent interconnection process of the first transistor 11 may be completed, forming the first metal interconnection layer 111. The first metal interconnection layer 111 communicates with the first source drain metal 115.

Referring to fig. 14, an insulating oxide is deposited over the structure shown in fig. 13, forming a first insulating layer 28; above the first insulating layer 28, a carrier wafer 29 is bonded to the first insulating layer 28, followed by rewinding.

Referring to fig. 15, the semiconductor substrate 20 shown in fig. 14 is removed, exposing a fourth portion of the second portion of the fin structure 21 and the shallow trench isolation structure 22.

Referring to fig. 16, a second source drain structure 122 is formed based on the fourth portion of the active structure, and a plurality of second gate structures 124 are alternately arranged with the second source drain structure 122 in the second direction. Meanwhile, a second double diffusion isolation structure 132 is formed in the double diffusion isolation region 17.

Here, the second source drain structure 122, the second gate structure 124, and the second double diffusion isolation structure 132 may be formed in the same manner as the first source drain structure 112, the first gate structure 114, and the first double diffusion isolation structure 131 are formed. Specific steps may be described with reference to one or more embodiments corresponding to fig. 7 to 10, and are not repeated herein for brevity of description.

Referring to fig. 17, a fourth gate structure 124a of the plurality of second gate structures 124, which is remote from the double diffusion isolation region 17, and an active structure corresponding to the fourth gate structure 124a may be etched until the first single diffusion isolation structure 141 is exposed to form a third recess. Then, an insulating material is filled in the third recess to form a second single diffusion isolation structure 142.

Wherein the second source drain structure 122 and other structures of the plurality of second gate structures 124 except the fourth gate structure 124a constitute the second transistor 12.

Here, the second single diffusion isolation structure 142 may be formed in the same manner as the first single diffusion isolation structure 141. Specific steps may be described with reference to one or more embodiments corresponding to fig. 11 to 12, and are not repeated herein for brevity of description.

In step S305, referring to fig. 18, the double diffusion isolation structure 13 is etched to form a first recess, and a metal material is filled in the first recess to form an interconnection via structure 15.

It will be appreciated that by forming the interconnect via structure 15 in the double diffusion isolation structure 13, communication between the first metal interconnect layer 111 in the first transistor 11 and the second metal interconnect layer 121 in the second transistor 12 may be achieved.

In one embodiment, etching the double diffusion isolation structure 13 to form a first recess includes: coating a photoresist over the second transistor 12 to form a photoresist layer covering the region other than the double diffusion isolation region 17; the first transistor 11 and the second transistor 12 are etched up to the first metal interconnection layer 111 using the photoresist layer as a mask to form a first recess.

In one embodiment, filling a metal material in the first recess to form an interconnect via structure includes: depositing an insulating material on the inner walls of the first recess to form an isolation layer 26; the first recess is filled with a metal material to form an interconnect via structure 15, the interconnect via structure 15 being isolated from the active structure by an isolation layer 26.

In one embodiment, the second metal interconnect layer 121 is formed on the second transistor 12 and the second single diffusion isolation structure 142.

Referring to fig. 2, after forming the interconnection via structure 15, a subsequent interconnection process of the second transistor 12 may be completed, forming a second metal interconnection layer 121. The second metal interconnection layer 121 communicates with the second source drain metal 125. Meanwhile, the interconnect via structure 15 communicates the first metal interconnect layer 111 and the second metal interconnect layer 121.

In the embodiment of the application, the first part of the active structure is removed through a cutting process, so that a gap is formed between adjacent stacked transistor units, and a double-diffusion isolation structure is formed by the gap, thereby realizing that the stacked transistor units have electrical isolation between one side and the adjacent stacked transistor units; by forming a single diffusion isolation structure opposite to the double diffusion isolation structure, the stacked transistor unit is electrically isolated from the adjacent stacked transistor unit on the other side, so that the stacked transistor has good electrical isolation performance. Further, by forming the interconnection through hole structure in the double-diffusion isolation structure, the characteristic that the area of the double-diffusion isolation structure is large is fully utilized, on one hand, the width of the interconnection through hole structure is increased, the resistance of the interconnection structure is reduced, and the conductivity of the stacked transistor is improved; on the other hand, the precision requirement when the interconnection through hole is formed by photoetching is reduced, and the preparation difficulty is greatly reduced.

Fig. 19 is a schematic diagram of a third structure of a stacked transistor in an embodiment of the application. In fig. 19 (a) is a top view of the stacked transistor, it should be noted that, for ease of understanding, only fin structures, gate structures, source-drain structures, metal interconnection structures, interconnection via structures, double diffusion isolation structures, and single diffusion isolation structures are shown in the top view; fig. 19 (b) is a cross-sectional view taken along the direction of the broken line A-A' in fig. 19 (a); fig. 19 (c) is a cross-sectional view taken along the direction of a broken line B-B' in fig. 2 (a).

As shown in fig. 19, the stacked transistor 10 includes: the first transistor 11 and the second transistor 12 are self-aligned stacked in a first direction (perpendicular to the extension direction of the fin structure 21).

In the second direction (extending direction of the fin structure 21), a double diffusion isolation structure 13 is provided at a first side of the first transistor 11 and the second transistor 12, and a single diffusion isolation structure 14 is provided at a second side of the first transistor 11 and the second transistor 12. Also, an interconnect via structure 15 is formed in the double diffusion isolation structure 13.

Fig. 19 (c) is a cross-sectional view of the stacked transistor 10 along the metal interconnect structure (metal lines in the metal interconnect layer). In this cross-sectional view, shallow trench isolation structures 22 are used to electrically isolate between the first transistor 11 and the second transistor 12. The interconnect via structure 15 is for communicating the first metal interconnect layer 111 of the first transistor 11 with the second metal interconnect layer 121 of the second transistor 12, thereby realizing signal interconnection between the first transistor 11 and the second transistor 12.

In one or more embodiments for preparing the stacked transistor, the stacked transistor also has self-alignment property, so that on one hand, the problems of complex process, difficult alignment and the like existing in the existing mainstream technical scheme of the stacked transistor are solved, and the industrialization of transistor stacking technology is promoted. On the other hand, by the self-aligned back-to-back active structure and the grid structure, the upper transistor and the lower transistor can have independent signal and power supply networks and are connected through the interconnection of the stacked transistors, and under the condition of not changing the design of the 4T track unit which is in the very miniature, the metal wiring resource is greatly released.

Finally, the scheme of realizing the upper and lower transistors through the rewinding is compatible with the existing mainstream device architecture, and the front and back stacking comprising a planar transistor, a FinFET, GAA Nanosheet and even a vertical transistor (VTFET) can be realized without special process development aiming at a specific device architecture, so that the flexibility is high, and the extensibility is high from the iteration point of a semiconductor processing node. The flip-chip transistor is very advanced in concept, has important industrial value, and has strong practicability and wide expansion prospect.

An embodiment of the present application provides a semiconductor device including: stacked transistors as in the above embodiments. The specific limitation of the stacked transistor may be referred to the stacked transistor shown in fig. 2 and 19, and will not be described herein.

An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device includes the above-described stacked transistor. The specific limitation of the stacked transistor may be referred to the structures shown in fig. 2 and 19, and will not be described herein.

In the description of the present application, a description of the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method of interconnecting stacked transistors, comprising:

forming an active structure on a semiconductor substrate;

Removing the first part of the active structure by adopting a cutting process so as to expose the semiconductor substrate in the double-diffusion isolation region; the double diffusion isolation region is located at one side of the second part of the active structure;

forming a double diffusion isolation structure on the semiconductor substrate in the double diffusion isolation region;

Forming a first transistor and a second transistor self-aligned in a first direction based on the retained second portion of the active structure, and a single diffusion isolation structure; the single diffusion isolation structure is positioned on the same side of the first transistor and the second transistor and is opposite to the double diffusion isolation structure; the first direction is perpendicular to the extending direction of the active structure;

Etching the double diffusion isolation structure to form a first groove, and filling a metal material in the first groove to form an interconnection through hole structure; the interconnection through hole structure is used for communicating the first metal interconnection layer of the first transistor with the second metal interconnection layer of the second transistor.

2. The method of claim 1, wherein forming the first transistor and the second transistor self-aligned in the first direction based on the retained second portion of the active structure, and the single diffusion isolation structure comprises:

Forming a first transistor and a first single diffusion isolation structure based on a third portion of the second portion of the active structure;

rewinding the first transistor and removing the semiconductor substrate to expose a fourth portion of the second portion of the active structure;

a second transistor and a second single diffusion isolation structure are formed based on the fourth of the second portions of the active structure.

3. The method of claim 2, wherein after forming the first transistor and the first single diffusion isolation structure based on a third portion of the second portion of the active structure, the method further comprises:

Forming the first metal interconnection layer on the first transistor and the first single diffusion isolation structure;

the etching the double diffusion isolation structure to form a first groove comprises the following steps:

Coating photoresist above the second transistor to form a photoresist layer, wherein the photoresist layer covers the area except the double diffusion isolation area;

and etching the first transistor and the second transistor by taking the photoresist layer as a mask until the first metal interconnection layer so as to form the first groove.

4. The method of claim 2, wherein after filling the first recess with a metal material to form an interconnect via structure, the method further comprises:

the second metal interconnect layer is formed over the second transistor and the second single diffusion isolation structure.

5. The method of claim 2, wherein forming the first transistor and the first single diffusion isolation structure based on a third portion of the second portion of the active structure comprises:

Forming a first source-drain structure based on a third portion of the active structure, and a plurality of first gate structures alternately arranged with the first source-drain structure along a second direction; the second direction is parallel to the extending direction of the active structure;

Etching a third gate structure of the plurality of first gate structures, which is far away from the double-diffusion isolation region, and the third part of the active structure corresponding to the third gate structure to form a second groove; wherein other structures than the third gate structure in the plurality of first gate structures and the first source-drain structure constitute the first transistor;

and filling an insulating material in the second groove to form the first single diffusion isolation structure.

6. The method of claim 5, wherein forming a second transistor and a second single diffusion isolation structure based on the fourth of the second portions of the active structure comprises:

Forming a second source-drain structure based on the fourth portion of the active structure, and a plurality of second gate structures alternately arranged with the second source-drain structure along a second direction;

Etching a fourth gate structure of the second gate structures, which is far away from the double-diffusion isolation region, and the active structure corresponding to the fourth gate structure until the first single-diffusion isolation structure is exposed, so as to form a third groove; wherein the second transistor is formed by other structures except the fourth gate structure and the second source-drain structure in the plurality of second gate structures;

and filling an insulating material in the third groove to form the second single diffusion isolation structure.

7. The method of claim 1, wherein filling the first recess with a metal material to form an interconnect via structure comprises:

depositing an insulating material on the inner wall of the first groove to form an isolation layer;

and filling a metal material in the first groove to form the interconnection through hole structure, wherein the interconnection through hole structure is isolated from the active structure through the isolation layer.

8. The method of claim 1, wherein the forming a double diffusion isolation structure on the semiconductor substrate within the double diffusion isolation region comprises:

depositing an oxide material on the semiconductor substrate in the double-diffusion isolation region to form a shallow trench isolation structure, wherein the height of the shallow trench isolation structure is lower than that of the active structure;

depositing an insulating material over the shallow trench isolation structure to form a first double diffusion isolation structure;

Rewinding the first double-diffusion isolation structure and removing the semiconductor substrate in the double-diffusion isolation region;

thinning the shallow trench isolation structure to a preset height;

and depositing an insulating material on the thinned shallow trench isolation structure to form a second double-diffusion isolation structure.

9. A stacked transistor prepared using the method of any one of claims 1 to 8, comprising:

A first transistor;

A second transistor, the first transistor and the second transistor being stacked in a first direction; the first direction is perpendicular to the extending direction of the active structure;

A double diffusion isolation structure is arranged on a first side of the first transistor and a second side of the second transistor along a second direction, and a single diffusion isolation structure is arranged on a second side of the first transistor and the second transistor; the first direction is perpendicular to the second direction;

An interconnection through hole structure is formed in the double diffusion isolation structure; the interconnection through hole structure is used for communicating the first metal interconnection layer of the first transistor with the second metal interconnection layer of the second transistor.

10. A semiconductor device, comprising: the stacked transistor of claim 9.