CN118352310A

CN118352310A - Preparation method of stacked fork plate transistor, stacked fork plate transistor and electronic equipment

Info

Publication number: CN118352310A
Application number: CN202410178652.8A
Authority: CN
Inventors: 吴恒; 刘煜; 卢浩然; 葛延栋; 黎明; 王润声; 黄如
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2024-02-09
Filing date: 2024-02-09
Publication date: 2024-07-16

Abstract

The application provides a method for connecting a power rail of a stacked fork plate transistor, the stacked fork plate transistor, a device and equipment, and provides the method for manufacturing the stacked fork plate transistor, the stacked fork plate transistor and the electronic equipment, wherein the method comprises the following steps: forming a first semiconductor structure on a substrate; forming a first power rail on the first semiconductor structure; forming a first dielectric wall structure on a first power rail; removing the second sacrificial layer and forming a first metal communication structure connected with the first power rail in the first source electrode structure; forming a first metal interconnection layer on the second semiconductor structure and the third semiconductor structure; rewinding the second semiconductor structure and the third semiconductor structure; removing a portion of the substrate and the shallow trench sacrificial layer until a second portion of the pair of active structures is exposed; forming a second dielectric wall structure between a second portion of the pair of active structures; a second metal interconnect layer is formed over the fourth semiconductor structure and the fifth semiconductor structure. By the application, the integration density of the transistor can be improved.

Description

Preparation method of stacked fork plate transistor, stacked fork plate transistor and electronic equipment

Technical Field

The present application relates to the field of semiconductors, and in particular, to a method for manufacturing a stacked fork transistor, and an electronic device.

Background

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors further increase transistor integration density by integrating two or more layers of transistors in vertical space is one of the important technologies continuing the scaling of integrated circuits.

When the stacked fork-plate transistor (stacked transistor) is fabricated using a conventional monolithic scheme, there is a problem in that it is difficult to increase the integration density of the transistor.

Disclosure of Invention

The application provides a preparation method of a stacked fork plate transistor, the stacked fork plate transistor and electronic equipment, so as to improve the integration density of the transistor.

In a first aspect, an embodiment of the present application provides a method for manufacturing a stacked fork plate transistor, where the method includes: forming a first semiconductor structure on a substrate, the first semiconductor structure comprising: the active structure comprises a first part and a second part, wherein the first part is farther from the substrate than the second part, and at least a first sacrificial layer and an isolation layer which are sequentially stacked are arranged between the first part and the second part along the direction vertical to the substrate; the shallow groove isolation layer wraps the first part and is flush with the first sacrificial layer; forming a first power rail on the first semiconductor structure, the first power rail being located between first portions of a pair of active structures; forming a first dielectric wall structure on a first power rail; forming a second semiconductor structure and a third semiconductor structure based on a first portion of the pair of active structures, the second semiconductor structure including a first gate structure, a first source structure, and a first drain structure, the third semiconductor structure including a second gate structure, a second source structure, and a second drain structure; the first gate structure is isolated from the second gate structure by a first dielectric wall fork plate on the first dielectric wall structure; removing the isolation layer and forming a first metal communication structure connected with the first power rail in the first source electrode structure; forming a first metal interconnection layer on the second semiconductor structure and the third semiconductor structure; rewinding the second semiconductor structure and the third semiconductor structure; removing a portion of the substrate and the shallow trench isolation layer until a second portion of the pair of active structures is exposed; forming a second dielectric wall structure between a second portion of the pair of active structures; forming a fourth semiconductor structure and a fifth semiconductor structure based on the second portion of the pair of active structures, the fourth semiconductor structure including a third gate structure, a third source structure, and a third drain structure, the fifth semiconductor structure including a fourth gate structure, a third source structure, and a fourth drain structure; the third gate structure is isolated from the fourth gate structure by a second dielectric wall fork plate on the second dielectric wall structure; a second metal interconnect layer is formed over the fourth semiconductor structure and the fifth semiconductor structure.

In some possible embodiments, after removing the isolation layer, the method further comprises: a second metal communication structure is formed in the second source structure that is connected to the first power rail.

In some possible embodiments, a second sacrificial layer is further disposed between the first portion and the second portion in a direction perpendicular to the substrate, the second sacrificial layer being closer to the second portion than the first sacrificial layer; after removing a portion of the substrate and the shallow trench isolation layer until a second portion of the pair of active structures is exposed, the method further comprises: forming a second power rail on another portion of the shallow trench isolation layer, the second power rail being located between a second portion of the pair of active structures; after forming the fourth semiconductor structure and the fifth semiconductor structure based on the second portion of the pair of active structures, the method further comprises: and removing the second sacrificial layer and forming a third metal communication structure connected with the second power rail in the third source electrode structure.

In some possible embodiments, after removing the second sacrificial layer, the method further includes: a fourth metal communication structure is formed in the fourth source structure that is connected to the second power rail.

In some possible embodiments, forming a first power rail on the first semiconductor structure includes: depositing an oxide material on the first semiconductor structure to form a first insulating layer; depositing a metal material on the first insulating layer to form a first metal structure; etching the first metal structure to a preset height to form a second metal structure; etching a region of the second metal structure outside the first portions of the pair of active structures to obtain a third metal structure between the second portions of the pair of active structures; an oxide is deposited over the third metal structure to form a first power rail.

In some possible embodiments, forming a first metal communication structure in the first source structure connected to the first power rail, includes: depositing a semiconductor material on the first source electrode structure to form an interlayer dielectric layer; etching the interlayer dielectric layer until the first power rail is exposed to form a first groove; and filling a metal material in the first groove to form a first metal communication structure.

In some possible embodiments, after forming the first dielectric wall structure on the first power rail, the method further comprises: a first dielectric wall fork plate is formed over the first dielectric wall structure based on the isolation material.

In a second aspect, an embodiment of the present application provides a stacked fork plate transistor, including: the semiconductor device comprises a second semiconductor structure, a third semiconductor structure, a fourth semiconductor structure, a fifth semiconductor structure, a first power rail, a first dielectric wall structure, a first dielectric wall fork plate, a second dielectric wall structure and a second dielectric wall fork plate, wherein the first dielectric wall fork plate is positioned on the first dielectric wall structure, and the second dielectric wall fork plate is positioned on the second dielectric wall structure; the first power rail is located between the second semiconductor structure and the third semiconductor structure. The second semiconductor structure comprises a first grid structure, a first source electrode structure and a first drain electrode structure, and the third semiconductor structure comprises a second grid structure, a second source electrode structure and a second drain electrode structure; the first gate structure is isolated from the second gate structure by a first dielectric wall fork plate; the fourth semiconductor structure comprises a third gate structure, a third source structure and a third drain structure, and the fifth semiconductor structure comprises a fourth gate structure, a fourth source structure and a fourth drain structure; the third gate structure is isolated from the fourth gate structure by a second dielectric wall fork plate. The stacked fork plate transistor further comprises at least one of the following: the second semiconductor structure further comprises a first metal communication structure, and the first metal communication structure is connected with the first source electrode structure and the first power rail; the third semiconductor structure further includes a second metal communication structure connected to the second source structure and the first power rail.

In some possible implementations, the stacked fork plate transistor further includes a second power rail located between the fourth semiconductor structure and the fifth semiconductor structure; the stacked fork plate transistor further comprises at least one of the following: the fourth semiconductor structure further comprises a third metal communication structure, and the third metal communication structure is connected with the third source electrode structure and the second power rail; the fifth semiconductor structure further includes a fourth metal communication structure connected to the fourth source structure and the second power rail.

In a third aspect, an embodiment of the present application provides an electronic device, including: the stacked fork board transistor is arranged on the circuit board.

In the application, the first power rail is formed on the first semiconductor structure, the first dielectric wall structure is formed on the first power rail, the first dielectric wall fork plate is formed on the first dielectric wall structure to isolate the second semiconductor from the third semiconductor, the second semiconductor and the third semiconductor are symmetrically arranged on two sides of the first dielectric wall fork plate, the isolation layer arranged between the first part and the second part of the active structure along the vertical direction is removed, the first metal communication structure connected with the first power rail is formed in the first source structure of the second semiconductor, and the first dielectric wall fork plate can realize the reduction of the space between devices symmetrically arranged on two sides of the first dielectric wall fork plate through isolating the second semiconductor and the third semiconductor, thereby improving the integration density. In addition, the first power rail is arranged at the first dielectric wall fork plate and is connected from the bottom of the first source electrode structure in a wrapping mode, so that the resistance can be reduced.

Further, stacking the fork plate transistor enables a combination of the stacked transistor and the fork plate transistor, and further improves integration density while enabling self-alignment of the second semiconductor and the fourth semiconductor and self-alignment of the third semiconductor and the fourth semiconductor.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic flow chart of a method for manufacturing a stacked fork-plate transistor according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a stacked fork plate transistor according to an embodiment of the present application;

FIGS. 3-29 are schematic diagrams of a fabrication process for stacking fork-plate transistors in accordance with embodiments of the present application;

the figures above:

10. Stacking fork plate transistors; 20. an active structure; 201. a first portion of the active structure; 202. a second portion of the active structure; 21. a first initial stack structure; 21A, a first isolation layer; 21B, a first semiconductor layer; 22. a second initial stacked structure; 22A, a second isolation layer; 22B, a second semiconductor layer; 23. an intermediate layer; 231. a first sacrificial layer; 231a, a new first sacrificial layer; 232. a third isolation layer; 233. a second sacrificial layer; 24. a substrate; 251. a first insulating layer; 252. a second insulating layer; 253. a third insulating layer; 261. a first metal structure; 262. a second metal structure; 271. a first power rail; 272. a second power rail; 280. a dielectric layer; 281. a first dielectric wall structure; 282. a second dielectric wall structure; 291. a first dielectric wall yoke plate; 292. a second dielectric wall yoke plate; 30. shallow trench isolation layers; 31. a second semiconductor; 311. a first gate structure; 312. a first source electrode structure; 313. a first drain structure; 41. a third semiconductor; 411. a second gate structure; 412. a second source electrode structure; 413. a second drain structure; 51. a fourth semiconductor; 511. a third gate structure; 512. a third source structure; 513. a third drain structure; 61. a fifth semiconductor; 611. a fourth gate structure; 612. a fourth source structure; 613. a fourth drain structure; 71. an interlayer dielectric layer; 711. a first groove; 712. a first metal communication structure; 713. a second metal communication structure; 715. a first metal interconnect layer; 714. a second metal interconnect layer; 716. a third metal communication structure; 717. a fourth metal communication structure; 81. a patterned mask layer; 821. a first dielectric layer; 822. a second dielectric layer; 83. a dummy gate structure; a. a spacer layer.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.

While moore's law is continually deepening, continuing to advance transistor scaling after the technology node of the full-round gate transistor (GAA) is a hot spot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits.

In one embodiment, the fabrication process of the stacked transistor (stacked transistors) has two schemes, the first is a monolithic stacking scheme and the second is a sequential scheme.

In the first approach, N-channel field effect transistors (N FIELD EFFECT transistors, NFETs) and P-channel field effect transistors (P FIELD EFFECT transistors, PFETs) are fabricated on the same substrate, and wafer bonding techniques are not used. This determines that the same layer transistors must be of the same type, i.e., NFET or PFET. And the transistors on the upper layer and the lower layer are strictly in the same plane space, and no alignment deviation exists. The advantage of this solution is a better integration density. Drawbacks of this approach include the following two points: (1) The process is complex, and a large number of process technologies need to be developed and optimized; (2) Each layer of transistors has a fixed polarity, and two layers of transistors must be relied upon to form a basic Complementary Metal Oxide Semiconductor (CMOS) circuit, which has poor design flexibility.

The second scheme is based on wafer bonding and layer-by-layer processing. Specifically, the two transistors are stacked vertically by bonding a wafer on top of the fabricated lower transistor to prepare the upper transistor. However, this approach requires tight temperature control during the thermal process of processing the upper layer transistors, avoiding affecting the lower layer transistors and the interconnect lines. The scheme has the advantages that the device structure, the channel crystal orientation and even the channel material adopted by the upper layer transistor and the lower layer transistor can be correspondingly optimized to obtain better and more matched device performance due to wafer bonding. This solution currently presents the following technical challenges: (1) preparation of a high-quality upper transistor active layer; (2) thinning and defect control of the upper bonded wafer; (3) The upper and lower layer transistors have alignment errors and have extremely high requirements on photoetching precision.

The common technical difficulties faced by the two schemes include: 1) When the upper device is manufactured, the thermal stability of the lower device is improved; 2) Performance of upper devices at low thermal budget; (3) layer-to-layer transistor metal interconnect.

In order to solve the technical problems of the two schemes, a self-aligned stacked transistor is provided, active regions of upper and lower homologous transistors are formed by etching, and the stacked transistor is manufactured on the front and back sides of a wafer by rewinding, so as to overcome the defects of the two schemes. The stacked transistor includes a stacked first transistor and a stacked second transistor. Respective terminals (such as a source, a drain, and a gate) of the stacked transistor are connected to a plurality of Power rails (Power rails) and a plurality of signal lines, respectively. The conventional interconnection scheme is to arrange a plurality of power supply rails and a plurality of signal lines on the same layer of interconnection layer (for example, M0 layer) based on planar interconnection. Further miniaturization of the size of the semiconductor device 100 is limited by the large area of the power supply rails, which results in a large planar area occupied by the formed plurality of power supply rails.

Between two types of transistors, an N-type metal oxide semiconductor (NMOS) and a P-type metal oxide semiconductor (PMOS), which form Complementary Metal Oxide Semiconductor (CMOS) logic, a certain separation distance must be maintained to limit capacitance that impairs device performance and affects power consumption, reducing interference between adjacent transistors. This spacing limits the scaling of nanoplatelet-based logic. Fork plate transistors (forksheet) are one way to break this limitation, and forksheet is constructed by placing transistors in pairs on either side of a dielectric wall (DIELECTRIC WALL). The dielectric walls allow the device to be placed closely without capacitance problems, and designers can use the newly added space to shrink the logic cells, and can also use the existing space to manufacture wider transistors to achieve better performance.

However, forksheet is currently fabricated based on a monolithic approach, except that similar problems exist as described above for monolithically stacked transistors, and the integration density of the transistors is also limited. In addition, the wiring interconnection of the transistor needs to be provided with a power rail and signal lines on the M0 interconnection layer, the area of the power rail is large, the number of the signal lines is large, and the large area is occupied on the M0 layer, so that the further miniaturization of the size of the semiconductor device is limited.

In order to solve the above technical problems, an embodiment of the present application provides a method for manufacturing a stacked fork plate transistor, so as to improve the integration density of the transistor.

In the embodiment of the application, the stacked fork plate transistor can be applied to semiconductor devices such as memories, processors and the like.

In some embodiments, a stacked fork plate transistor may include a second semiconductor structure, a third semiconductor structure, a fourth semiconductor structure, a fifth semiconductor structure, a first power rail, a first dielectric wall structure, a first dielectric wall fork plate, a second dielectric wall structure, and a second dielectric wall fork plate, wherein the first dielectric wall fork plate is located on the first dielectric wall structure and the second dielectric wall fork plate is located on the second dielectric wall structure; the first power rail is positioned between the second semiconductor structure and the third semiconductor structure, the second semiconductor structure comprises a first grid structure, a first source electrode structure and a first drain electrode structure, and the third semiconductor structure comprises a second grid structure, a second source electrode structure and a second drain electrode structure; the first gate structure is isolated from the second gate structure by a first dielectric wall fork plate; the fourth semiconductor structure comprises a third gate structure, a third source structure and a third drain structure, and the fifth semiconductor structure comprises a fourth gate structure, a fourth source structure and a fourth drain structure; the third gate structure is isolated from the fourth gate structure by a second dielectric wall fork plate.

In the embodiment of the present application, the second semiconductor, the third semiconductor, the fourth semiconductor, and the fifth semiconductor in the stacked fork plate transistor may be transistors of the same type, such as any one of the following: nanoflake field effect transistors, fin field effect transistors, planar transistors, and the like. Wherein, as fork plate transistors, the second semiconductor and the third semiconductor are located in the front region, the fourth semiconductor and the fifth semiconductor are located in the back region, and the second semiconductor and the third semiconductor can be the same type of transistor (such as NFET or PFET) or different types of transistor (such as NFET and PFET); accordingly, the fourth semiconductor and the fifth semiconductor may be the same type of transistor, or may be different types of transistors; the embodiment of the application does not particularly limit the types of the plurality of transistors in the fork plate transistor in the front surface area or the back surface area.

Fig. 2 is a schematic diagram of a stacked fork transistor formed by a nano-chip field effect transistor, and a method for manufacturing the stacked fork transistor according to an embodiment of the present application is described below with reference to the structure of the stacked fork transistor shown in fig. 2.

Fig. 1 is a schematic flow chart of an implementation of a power rail connection method of a stacked fork transistor according to an embodiment of the present application, and referring to fig. 1, the power rail connection method of a stacked fork transistor may include:

s101, forming a first semiconductor structure on a substrate.

Wherein the first semiconductor structure comprises: a pair of active structures and a shallow trench isolation layer.

It can be appreciated that the active structure includes a first portion and a second portion, where the first portion is farther from the substrate than the second portion, and at least a first isolation layer and a second isolation layer are disposed between the first portion and the second portion, and are stacked in sequence; the shallow trench isolation layer wraps the first portion and is flush with the first isolation layer.

In some embodiments, the first portion and the second portion may be composed of sacrificial layers and semiconductor layers that are alternately stacked. The first portion may also be referred to as a first stack and the second portion may also be referred to as a second stack.

In some embodiments, a third isolation layer is further disposed between the first portion and the second portion in a direction perpendicular to the substrate, the third isolation layer being closer to the two portions than the first isolation layer.

In some embodiments, the shallow trench isolation material may be a nitride, an oxide (such as tetraethyl orthosilicate (TEOS)), or other semiconductor materials.

In some embodiments, when the stacked fork plate transistor is a nano-plate field effect transistor, the thickness of the silicon layer located on the substrate may be greater than the thickness of the other silicon layers in the stack of active structures, the substrate being formed by sequentially depositing material layers of different materials based on the lowermost silicon layer of a pair of active structures.

S102, forming a first power rail on the first semiconductor structure.

Wherein the first power rail is located between the first portions of the pair of active structures.

In some embodiments, after forming a first semiconductor structure on a substrate, depositing an oxide material on the first semiconductor structure to form a first insulating layer; depositing a metal material on the first insulating layer to form a first metal structure; etching the first metal structure to a preset height to form a second metal structure; etching a region of the second metal structure outside the first portions of the pair of active structures to obtain a third metal structure between the second portions of the pair of active structures; an oxide is deposited over the third metal structure to form a first power rail, the first power rail being located between the first portions of the pair of active structures.

In some embodiments, the predetermined height is a height below the first portion of the active structure, which is not limited herein.

It will be appreciated that the power supply rail is provided for powering the transistors, the purpose of the power supply rail being to power the stacked fork-plate transistors for subsequent connection with the first source metal. In one example, the power rail may be VSS of the stacked fork-gate transistor or VDD of the stacked fork-gate transistor.

S103, forming a first dielectric wall structure on the first power rail.

In some embodiments, after forming a first power rail on a first semiconductor structure, a dielectric material is deposited on the first power rail to form an initial dielectric wall structure, the initial dielectric wall structure overlying the first power rail is etched until the lower surfaces of the second semiconductor and the third semiconductor, the dielectric material deposited between the second semiconductor and the third semiconductor being unremoved, forming the first dielectric wall structure.

It should be noted that, when the dielectric material is filled, the initial dielectric wall structure between the pair of active structures may be made to have a greater height than the initial dielectric wall structure outside the pair of active structures by controlling the rate and/or time of film deposition, so that the initial dielectric wall structure outside the pair of active structures is completely removed while the initial dielectric wall structure between the pair of active structures remains when the initial dielectric wall structure is etched back. Of course, in other embodiments, the first dielectric wall structure may also be formed by etching the initial dielectric wall structure multiple times.

S104, forming a second semiconductor structure and a third semiconductor structure based on the first part of the pair of active structures.

In some embodiments, after forming the first dielectric wall structure on the first power rail, forming a second semiconductor structure and a third semiconductor structure based on a first portion of the pair of active structures, the second semiconductor structure including a first gate structure, a first source structure, and a first drain structure, the third semiconductor structure including a second gate structure, a second source structure, and a second drain structure; the first gate structure is isolated from the second gate structure by a first dielectric wall fork plate on the first dielectric wall structure.

In some embodiments, after forming the first source/drain structure, an interlayer dielectric may be further deposited on the first source/drain structure, thinned to a top layer of the first source/drain structure to form a first interlayer dielectric layer, and then a first source/drain metal is formed in the first interlayer dielectric layer.

It should be noted that, the first source/drain structure, the first source/drain metal and the first interlayer dielectric layer may be formed by standard steps of a semiconductor manufacturing process, which is not particularly limited in the embodiment of the present application.

In practical applications, the source/drain structure may be doped according to circuit design requirements to change the polarity of the semiconductor layer, thereby forming a P-type or N-type transistor.

S105, removing the second isolation layer, and forming a first metal communication structure connected with the first power rail in the first source electrode structure.

In some embodiments, after forming the second semiconductor structure and the third semiconductor structure based on the first portion of the pair of active structures, depositing a semiconductor material on the first source structure to form an interlayer dielectric layer; etching the interlayer dielectric layer until the first power rail is exposed to form a first groove; and filling a metal material in the first groove to form a first metal communication structure.

In some embodiments, the step S105 may include forming a second metal communication structure connected to the first power rail in the second source structure.

It is understood that one end of the first power rail connection metal is connected to the first source metal of the first source drain metals, and the other end is connected to the first power rail, so that the first power rail can supply power to the first transistor through the first power rail connection metal.

In an example, the forming of the first source drain metal on the first source drain structure and the forming of the first power rail connection metal on the first power rail may be performed simultaneously, and a metal material of the first source drain metal and a metal material of the first power rail connection metal may be the same.

And S106, forming a first metal interconnection layer on the second semiconductor structure and the third semiconductor structure.

It will be appreciated that after the second isolation layer is removed and the first metal communication structure connected to the first power rail is formed in the first source structure, standard processes are used to form a first metal interconnect layer over the second and third semiconductor structures based on circuit design requirements.

And S107, rewinding the second semiconductor structure and the third semiconductor structure.

It will be appreciated that the second semiconductor structure and the third semiconductor structure are reworked after the formation of the first metal interconnect layer.

And S108, removing a part of the substrate and the shallow trench isolation layer until a second part of the pair of active structures is exposed.

It will be appreciated that after the second and third semiconductor structures are reworked, a portion of the substrate and shallow trench isolation layer is removed until a second portion of the pair of active structures is exposed.

In some possible embodiments, after S108, the method further includes: a second power rail is formed on another portion of the shallow trench isolation layer, the second power rail being located between a second portion of the pair of active structures.

S109, forming a second dielectric wall structure between the second portions of the pair of active structures.

It will be appreciated that after forming the second power rail over the first semiconductor structure, a dielectric material is deposited over the second power rail and the dielectric material overlying the second power rail is etched to form a second dielectric wall structure.

And S110, forming a fourth semiconductor structure and a fifth semiconductor structure based on the second parts of the pair of active structures.

It will be appreciated that after forming the second dielectric wall structure between the second portions of the pair of active structures, forming a fourth semiconductor structure including a third gate structure, a third source structure, and a third drain structure and a fifth semiconductor structure including a fourth gate structure, a third source structure, and a fourth drain structure based on the second portions of the pair of active structures; the third gate structure is isolated from the fourth gate structure by a second dielectric wall fork plate on the second dielectric wall structure.

In some embodiments, after forming the second power rail on the first semiconductor structure, a dielectric material is deposited on the second power rail, the dielectric material overlying the second power rail is etched until the lower surfaces of the fourth semiconductor and the fifth semiconductor, the dielectric material deposited between the fourth semiconductor and the fifth semiconductor, which is not removed, forms a second dielectric wall structure.

In some possible embodiments, after S110, the method further includes: and removing the third isolation layer and forming a third metal communication structure connected with the second power rail in the third source electrode structure.

In some possible embodiments, after S110, the method further includes: and removing the third isolation layer, and forming a fourth metal communication structure connected with the second power rail in the fourth source electrode structure.

And S111, forming a second metal interconnection layer on the fourth semiconductor structure and the fifth semiconductor structure.

It will be appreciated that standard processes are used to form the second metal interconnect layer over the fourth semiconductor structure and the fifth semiconductor structure based on circuit design requirements.

The first stacked transistor and the second stacked transistor are symmetrically arranged on two sides of the dielectric wall fork plate along a first direction, the first stacked transistor comprises a second semiconductor and a fourth semiconductor which are self-aligned along the first direction, and the second stacked transistor comprises a third semiconductor and a fifth semiconductor which are self-aligned along the first direction.

It will be appreciated that after forming a pair of active structures, the front-side transistors may be fabricated in accordance with standard procedures followed by the back-side transistors. Wherein the front side transistor includes a second semiconductor and a third semiconductor, and the back side transistor includes a fourth semiconductor and a fifth semiconductor.

In some embodiments, when the stacked fork plate transistor is a nano-plate field effect transistor, the first portion of the active structure and the second portion of the active structure are columnar structures; the columnar structure is a lamination formed by alternately depositing a silicon layer and a silicon germanium layer; in the process of preparing the active structure, the nano-sheet structure can be formed by selectively etching the silicon germanium layer in the laminated layer.

In other embodiments, when the stacked fork plate transistor is a fin field effect transistor, the first portion of the active structure and the second portion of the active structure are fin structures. The number of fin structures is not particularly limited in the embodiment of the present application.

In still other embodiments, when the stacked fork plate transistor is a planar transistor, the first portion of the active structure and the second portion of the active structure are block structures.

In the embodiment of the present application, the insulating material forming the shallow trench isolation structure may be any one of the following: silicon nitride (e.g., siN, si ₃N₄), silicon dioxide (SiO ₂), or silicon oxycarbide (SiCO), among others.

In some possible embodiments, the step S107 may include: forming a second semiconductor and a third semiconductor based on the first portion of the active structure; bonding a carrier wafer to a first surface of the second semiconductor and a second portion of the third semiconductor remote from the active structure; rewinding and removing a portion of the substrate until a second surface of the shallow trench isolation structure is exposed away from the first portion of the active structure; removing a portion of the shallow trench isolation structure surrounding the back active structure to expose the back active structure; the fourth semiconductor and the fifth semiconductor are formed based on the second portion of the active structure.

In some embodiments, an insulating material may be deposited on the surfaces of the second semiconductor and the third semiconductor to form an insulating layer prior to bonding the carrier wafer. The insulating layer is used for electrically isolating the second semiconductor, the third semiconductor and the carrier wafer.

In some embodiments, in the process of removing the shallow trench isolation structure wrapping the back active structure, the remaining shallow trench isolation structure is not removed completely, but a shallow trench isolation structure with a certain thickness is reserved, and is used as a shallow trench isolation layer for isolating the front-side transistor and the back-side transistor.

In some possible embodiments, forming the second semiconductor and the third semiconductor based on the first portion of the active structure may include: forming a front gap wall, a front source drain structure and a front interlayer dielectric layer of the second semiconductor and the third semiconductor in sequence based on the first part of the active structure; removing the front side dummy gate structure to expose front side gate regions of the second semiconductor and the third semiconductor; depositing an isolation material in a first portion of the front gate region to form a first dielectric wall fork plate; the first portion corresponds to a first dielectric wall structure; depositing a metal material in other areas except the first part in the front grid area to form front grid structures of the second semiconductor and the third semiconductor, wherein the front grid structures are symmetrically arranged on two sides of the first dielectric wall fork plate; and performing a subsequent process on the front-side interlayer dielectric layer to form a first metal interconnection layer.

In some embodiments, the step of forming the front side spacer may include: and depositing an insulating material on the side wall of the front dummy gate structure to form a front spacer.

In some embodiments, the step of forming the front-side source-drain structure and the front-side interlayer dielectric layer may include: the source drain recesses of the second semiconductor and the third semiconductor may be provided by etching away the first portion of the active structure. Forming strained materials such as silicon germanium or silicon carbide in the source-drain grooves of the second semiconductor and the third semiconductor by using the front side gap wall as a mask through selective epitaxial growth so as to fill the source-drain grooves of the second semiconductor and the third semiconductor, and then forming a front side source-drain structure on the strained materials through a heavy doping process; next, an insulating material, such as silicon dioxide (SiO ₂), is deposited over the first portion of the active structure and the first source structure, the first drain structure, the second source structure, the second drain structure, forming a front-side interlayer dielectric layer, which may cover the first portion of the active structure and the first source structure, the first drain structure, the second source structure, the second drain structure.

It should be noted that, since the first semiconductor is a fork plate transistor, when the front-side source-drain structure is formed, the strained material can be controlled to grow on both sides of the first dielectric wall structure, and the front-side source-drain structure formed finally is two parts symmetrically arranged on both sides of the first dielectric wall structure, one part is used as the source-drain structure in the second semiconductor, and the other part is used as the source-drain structure in the third semiconductor.

In some embodiments, the step of forming the front-side gate structure may include: removing the front dummy gate structure, providing a front gate region for the subsequent formation of the front gate structure, coating photoresist on the first dielectric wall structure and in the front gate region, developing the photoresist to form a photoetching pattern aligned to the first dielectric wall structure, and depositing an isolation material on the dielectric fork plate structure by taking the photoresist as a mask to form a first isolation layer; then, the photoresist is removed and a metal material is deposited in the front gate region to form a front gate structure. The front grid structure is symmetrically arranged on two sides of the first dielectric wall fork plate.

In the embodiment of the application, the metal materials of the front grid structure and the back grid structure can be the same or different; the metal materials used for the front gate structure and the back gate structure may include, but are not limited to: the materials of the front gate structure and the back gate structure may be selected according to actual conditions, and are not limited to the metal materials listed above.

In some embodiments, a first metal interconnect layer is formed on the second semiconductor structure and the third semiconductor structure based on the first drain structure and the second drain structure.

In some embodiments, a first metal interconnect layer is formed on the second semiconductor structure and the third semiconductor structure based on the first drain structure, the second drain structure, and the second source structure.

In one possible embodiment, forming the fourth semiconductor and the fifth semiconductor of the first back side transistor based on the second portion of the active structure may include: depositing a third semiconductor material on the second portion of the active structure to form a back side dummy gate structure of the fourth semiconductor and the fifth semiconductor; forming a back spacer, a back source drain structure and a back interlayer dielectric layer of the fourth semiconductor and the fifth semiconductor in sequence based on the second part of the active structure; removing the back dummy gate structure to expose back gate regions of the fourth semiconductor and the fifth semiconductor; depositing an isolation material in a second portion of the back gate region to form a second isolation structure; the second portion corresponds to a second dielectric wall structure; depositing a metal material in other areas except the second part in the back gate area to form back gate structures of the fourth semiconductor and the fifth semiconductor, wherein the back gate structures are symmetrically arranged on two sides of the second isolation structure; and performing a subsequent process on the back interlayer dielectric layer to form a second metal interconnection layer.

It should be noted that the second isolation structure is located on the second dielectric wall structure, and the height of the second isolation structure in the horizontal direction is consistent with the height of the back gate structure. The gate structures of the fourth semiconductor and the fifth semiconductor form the back gate structure, and the second isolation structure is used for isolating the gate structure of the fourth semiconductor and the gate structure of the fifth semiconductor.

In an embodiment of the present application, the third semiconductor material for preparing the front side dummy gate structure and the back side dummy gate structure may include, but is not limited to: polysilicon (poly Si), amorphous silicon, or the like, and the above-described third semiconductor material may be selected according to practical situations, and is not limited to the above-listed materials.

In some embodiments, the step of forming the back spacer may include: and depositing an insulating material on the side wall of the back dummy gate structure to form a back spacer.

In the embodiment of the present application, the insulating materials used for the back spacer and the front spacer are the same material, or may be different materials, which is not particularly limited in the embodiment of the present application.

In some embodiments, the step of forming the back source drain structure and the back interlayer dielectric layer may include: the source drain recesses of the fourth semiconductor and the fifth semiconductor may be provided by etching away the second portion of the active structure. Forming strained materials such as silicon germanium or silicon carbide in the source-drain grooves of the fourth semiconductor and the fifth semiconductor by using the back spacer as a mask through selective epitaxial growth so as to fill the source-drain grooves of the fourth semiconductor and the fifth semiconductor, and then forming a back source-drain structure on the strained materials through a heavy doping process; next, an insulating material, such as silicon dioxide (SiO ₂), is deposited over the second portion of the active structure and the third source structure, the third drain structure, the fourth source structure, the fourth drain structure, forming a back-side interlayer dielectric layer, which may cover the second portion of the back active structure and the third source structure, the third drain structure, the fourth source structure, the fourth drain structure.

It should be noted that, since the first semiconductor is a fork plate transistor, when the back surface source-drain structure is formed, the strained material can be controlled to grow on both sides of the second dielectric wall structure, and the finally formed back surface source-drain structure is two parts symmetrically disposed on both sides of the second dielectric wall structure, one part is used as the source-drain structure in the fourth semiconductor, and the other part is used as the source-drain structure in the fifth semiconductor.

In some embodiments, the step of forming the back gate structure may include: removing the back dummy gate structure, providing a back gate region for the subsequent formation of the back gate structure, coating photoresist on the second dielectric wall structure and in the back gate region, developing the photoresist to form a photoetching pattern aligned to the second dielectric wall structure, and depositing an isolation material on the dielectric fork plate structure by taking the photoresist as a mask to form a second isolation layer; then, the photoresist is removed and a metal material is deposited in the back gate region to form a back gate structure. The back grid electrode structures are symmetrically arranged on two sides of the second isolation structure.

In some embodiments, a second metal interconnect layer is formed on the fourth semiconductor structure and the fifth semiconductor structure based on the third drain structure and the fourth drain structure.

In some embodiments, a second metal interconnect layer is formed on the fourth semiconductor structure and the fifth semiconductor structure based on the third drain structure, the fourth drain structure, and the fourth source structure.

In the following, a first semiconductor is taken as an example of a nano-chip field effect transistor, and a stacked fork plate transistor provided by an embodiment of the present application is described. Fig. 2 is a schematic structural diagram of a stacked fork-plate transistor according to an embodiment of the present application. In fig. 2, (a) is a design layout of the stacked fork plate transistor, and for convenience of understanding, only a nano-sheet structure, a gate structure and a source-drain structure are shown in the design layout; (b) Cut-away views of stacked fork-plate transistors taken along the cut-away direction (i.e., the A-A' direction) of the gate structure; (c) A cross-sectional view of the stacked fork plate transistor along a cross-sectional direction (i.e., the B-B' direction) of the source-drain structure; (d) Cut-away views of stacked fork-plate transistors are made along the cut-away direction (i.e., the C-C' direction) of the nanoplate structure.

Referring to fig. 2, the stacked fork plate transistor 10 includes a second semiconductor structure 31, a third semiconductor structure 41, a fourth semiconductor structure 51, a fifth semiconductor structure 61, a first power rail 271, a first dielectric wall structure 281, a first dielectric wall fork plate 291, a second dielectric wall structure 282, and a second dielectric wall fork plate 292.

Referring to fig. 2, in the A-A 'direction and the B-B' direction, the first dielectric wall structure 281 is located in the middle of the front-side nano-sheet structure of the front-side transistor, i.e., the front-side nano-sheet structure is symmetrically disposed at both sides of the first dielectric wall structure 281; likewise, the second dielectric wall structure 282 is located in the middle of the back-side nano-sheet structure of the back-side transistor, i.e., the back-side nano-sheet structure is symmetrically disposed on both sides of the second dielectric wall structure 282.

Wherein the second semiconductor structure 31 includes a first gate structure 311, a first source structure 312, and a first drain structure 313, and the third semiconductor structure 41 includes a second gate structure 411, a second source structure 412, and a second drain structure 413; the first gate structure 311 is isolated from the second gate structure 411 by a first dielectric wall fork 291; the fourth semiconductor structure 51 includes a third gate structure 511, a third source structure 512, and a third drain structure 513, and the fifth semiconductor structure 61 includes a fourth gate structure 611, a fourth source structure 612, and a fourth drain structure 613; the third gate structure 511 is isolated from the fourth gate structure 611 by a second dielectric wall fork plate 292; the first dielectric wall fork plate 291 is positioned on the first dielectric wall structure 281 and the second dielectric wall fork plate 292 is positioned on the second dielectric wall structure 282; the first power rail 271 is located between the second semiconductor structure 31 and the third semiconductor structure 41.

In some possible embodiments, the stacked fork plate transistor may further comprise at least one of: the second semiconductor structure 31 further includes a first metal communication structure 712, the first metal communication structure 712 being connected to the first source structure 312 and the first power rail 271; the third semiconductor structure 41 further comprises a second metal communication structure 713, said second metal communication structure 713 being connected to the second source structure 412 and the first power rail 271.

In some possible embodiments, the stacked fork plate transistor may further include: an intermediate isolation layer. Wherein, the intermediate isolation layer includes a first sacrificial layer 231, a third isolation layer 232, and may further include a second sacrificial layer 233, and the intermediate isolation layer is located between the front nano-sheet structure and the back nano-sheet structure, and the intermediate isolation layer is used for isolating the front nano-sheet structure and the back nano-sheet structure.

In some possible embodiments, the stacked fork plate transistor may further include: a first dielectric wall yoke 291; the first dielectric wall fork plate 291 is disposed on the first dielectric wall structure 281, and the first gate structure 311 and the second gate structure 411 of the front transistor are symmetrically disposed on two sides of the first dielectric wall fork plate 291; a second dielectric wall yoke plate 292; the second dielectric wall fork plate 292 is disposed on the first dielectric wall structure 281, and the third gate structure 511 and the fourth gate structure 611 of the back side transistor are symmetrically disposed at both sides of the second dielectric wall fork plate 292.

The process of manufacturing the stacked fork-plate transistor 10 shown in fig. 2 will be described below in connection with the above manufacturing method. The stacked fork-plate transistor 10 shown in fig. 2 can be prepared by the process shown in fig. 3 to 29, and fig. 3 to 29 are schematic views of a preparation process of the stacked fork-plate transistor according to an embodiment of the present application.

In an example, taking stacked fork-plate transistor 10 as a nano-sheet field effect transistor, the fabrication process of stacked fork-plate transistor 10 may include the steps of:

It should be noted that the different steps (i.e., different processes) in the following examples may show the manufacturing process of the stacked fork plate transistor 10 with A-A ' direction, B-B ' direction, C-C ' direction, or different combinations of the above directions, respectively, according to the structural changes.

The first step: semiconductor material is blanket deposited over substrate 24 to form an initial stacked structure.

In some embodiments, the material of the substrate 24 includes a semiconductor material, such as an elemental semiconductor material (e.g., silicon (Si) or germanium (Ge), etc.), a group III-V compound semiconductor material (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), a group II-VI compound semiconductor material (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), an organic semiconductor material, or other semiconductor materials known in the art. The present embodiment will be described taking the substrate 24 as a silicon substrate as an example.

As shown in fig. 3, the above initial stacked structure includes a second initial stacked structure 22, an intermediate sacrificial layer 23, and a first initial stacked structure 21 stacked in this order in a first direction. Wherein the first initial stack structure 21 includes first isolation layers 21A and first semiconductor layers 21B alternately arranged. The second initial stack structure 22 includes second isolation layers 22A and second semiconductor layers 22B alternately disposed. The intermediate layer 23 includes a second sacrificial layer 233, a third isolation layer 232, and a second sacrificial layer 233, which are sequentially disposed. The first direction is the epitaxial growth direction, perpendicular to the substrate 24.

Note that the material of the third isolation layer 232 includes a sacrificial layer material such as silicon oxide, polysilicon, photoresist, highly doped silicon germanium, and the like.

And a second step of: a patterned masking layer 81 is formed over the initial stack.

Referring to fig. 4, a patterned mask layer 81 is formed by depositing a dielectric material and performing photolithography or etching on the deposited dielectric material on the basis of the structure shown in fig. 3.

And a third step of: the initial stack is etched to the substrate 24 using the patterned mask layer 81 as an etch mask to form a pair of active structures 20.

Referring to fig. 5, on the basis of the structure shown in fig. 4, the initial stacked structure is etched using the patterned mask layer 81 as an etching mask until the substrate 24 is exposed to form a first trench. Here, the number of the first trenches may be one or more, and the first trenches may divide the initial stacked structure into at least one pair of active structures 20. The active structure 20 includes a first portion 201 and a second portion 202, and a portion of the intermediate sacrificial layer 23 that is not etched is included between the first portion 201 and the second portion 202.

In some embodiments, the etching process for the initial stacked structure includes at least one of a dry etch, a wet etch.

Fourth step: sacrificial material is deposited over substrate 24 and chemical-mechanical planarization (CMP) is performed until patterned masking layer 81 is exposed to form an initial Shallow Trench Isolation (STI) 30A.

Referring to fig. 6, on the basis of the structure shown in fig. 5, a sacrificial material is filled into the first trench, and a planarization process is performed until the patterned mask layer 81 is exposed, thereby forming an initial STI 30A.

Fifth step: the original STI 30A is etched back to remove the patterned mask layer 81 (see fig. 7).

Sixth step: the initial STI 30A is etched until at the third isolation layer 232 to expose the first portion 201 of the active structure 20.

Referring to fig. 8, the initial STI 30A is etched back on the basis of the structure shown in fig. 7 until the sidewalls of the remaining third isolation layer 232 are exposed to form the STI 30. In some embodiments, the etch-back initial STI 30A may stop at the bottom surface of the first sacrificial layer 231 or between the bottom surface and the top surface of the third isolation layer 232. When stopped between the bottom surface and the top surface of the third isolation layer 232, a portion of the sidewall of the third isolation layer 232 is also exposed.

Seventh step: an oxide is deposited over the STI 30 and the first portion 211, forming a first insulating layer 251.

Referring to fig. 9, an oxide is deposited on the basis of the structure shown in fig. 8 to form a first insulating layer 251 covering the STI 30 and the first portion 201.

Eighth step: a metal material is deposited on the first insulating layer 251 and CMP is performed to the first insulating layer 251 to form a first metal structure 261.

Referring to fig. 10, a metal material is deposited on the basis of the structure shown in fig. 9, and CMP is performed to the first insulating layer 25, thus forming a first metal structure 261. Here, the first metal structure 261 provides a basis for fabricating the first power rail 271.

Ninth step: the first metal structure 261 is etched to a predetermined height to form a second metal structure 262.

Referring to fig. 11, on the basis of the structure shown in fig. 10, when the first metal structure 261 is etched, the remaining first metal structure 261 may be stopped at a certain height, i.e., the height of the first power rail 271, by controlling the etching rate and/or time. For example, the remaining first metal structure 261 stops between the top and bottom surfaces of the first sacrificial layer 231, i.e., the surface of the first power rail 271 relatively far from the STI 30 is located between the third isolation layer 232 and the lowermost first semiconductor layer 21B, such that the subsequent first power rail is located between the new first sacrificial layer 231a and the first portion 201.

Tenth step: a layer of silicon oxide is deposited over the second metal structure 262 by an atomic layer deposition process to form the second insulating layer 252.

Referring to fig. 12, a layer of silicon oxide is deposited by an atomic layer deposition process on the basis of the structure shown in fig. 11, forming a second insulating layer 252 covering the first power rail 271 and the first portion 2012.

Eleventh step: a dielectric layer 280 is formed over the second insulating layer 252.

Referring to fig. 13, on the basis of the structure shown in fig. 12, a dielectric wall material is filled to form a dielectric layer 280, and the surface of the dielectric layer 280 is higher than the surface of the first portion 201. Here, the dielectric layer 280 provides a basis for a later fabrication of the first dielectric wall structure 281.

Twelfth step: the dielectric layer 280 is etched and portions between the pair of active structures 20 remain to form a first dielectric wall 281.

Referring to fig. 14, dielectric layer 280 is etched back to form first dielectric wall 281 by tightly controlling the rate and time of the isotropic etch based on the structure shown in fig. 13. In some embodiments, the surface of the first dielectric wall 281 is located between the bottom surface and the top surface of the uppermost second isolation layer 22A.

Thirteenth step: the second insulating layer 252 is etched exposing the first portion 201 and portions of the second metal structure 262 outside the pair of active structures 20.

Referring to fig. 15, on the basis of the structure shown in fig. 14, the second insulating layer 252 covering the side walls of the first portion 201 and the top surface is etched until it is substantially flush with the surface of the first dielectric wall 281. At this time, the second insulating layer 252 remains between the first dielectric wall 281 and the first portions 201 of the pair of active structures 20. The second insulating layer 252 covering the sidewalls of the first portion 201 and the top surface may also be etched at the same time as the second insulating layer 252 covering the portions of the second metal structure 262 outside the pair of active structures 20.

Fourteenth step: the second metal structure 262, which is located outside the pair of active structures 20, is etched to form a first power rail 271. Here, a first power rail 271 is located between the first portions 201 of a pair of active structures 20, above the first power rail 271 is a first dielectric wall structure 281 (see fig. 16).

Fifteenth step: an interlayer dielectric (INTER LAYER DIELECTRIC, ILD) layer 82 is formed where the second metal structure 262 is etched so that the ILD layer 82 replaces the portion of the second metal structure 262 that was etched away in the thirteenth step.

Referring to fig. 17, on the basis of the structure shown in fig. 16, ILD material is deposited over the first insulating layer 251, the active structure 20, and the first dielectric wall 281, which are located outside the pair of active structures 20, and CMP is performed such that the portions of the ILD layer 82 outside the active structures 20 replace the etched-away portions of the second metal structure 262.

Sixteenth step: a layer of oxide is deposited to form a third insulating layer 253.

Referring to fig. 18, an oxide layer is deposited by an ALD process to form a third insulating layer 253 overlying ILD layer 82, first portion 201, and first dielectric wall 281, based on the structure shown in fig. 17.

Seventeenth step: a polysilicon material is deposited over the third insulating layer 253 to form a dummy gate structure 83 (see fig. 19).

It should be noted that, in fig. 19, the cross-sectional view along the direction of the dashed line C-C ' is taken along the preset forming position of the channel, and the direction of the dashed line C-C ' is perpendicular to the direction of the dashed line A-A '; the cross-sectional view in the direction of the broken line B-B 'in fig. 20 is taken along the predetermined formation position of the source/drain electrode, so that the dummy gate structure 83 is not formed above the structure corresponding to the broken line B-B' in fig. 20, and the broken line B-B 'direction is parallel to the broken line A-A' direction, and the broken line B-B 'direction and the broken line C-C' direction will not be described in detail.

Eighteenth step: the first isolation layer 21A, the second isolation layer 22A, and the first sacrificial layer 231 in the active structure 20 are removed, and the first sacrificial layer 231 removes the position filling isolation material, forming a new first sacrificial layer 231A (see fig. 20).

Nineteenth step: based on the first portion 201, a first source structure 312 and a first drain structure 313 are epitaxially grown.

Referring to fig. 21, on the basis of the structure shown in fig. 20, the isolation material of the surface is etched until the first portion 201 of the active structure 20 is exposed, and the first portion 201 is etched to form at least two trenches arranged at intervals in a direction D perpendicular to and directed toward the substrate 24, the at least two trenches extending downward to the surface of the new first sacrificial layer 231a or into the new first sacrificial layer 231a, and adjacent two trenches exposing opposite ends of the new first sacrificial layer 231a in the direction D. The exposed pair of ends are epitaxially grown to form a first source structure 312 and a first drain structure 313 as shown in fig. 23. The second semiconductor layer 22B located between the first source structure 312 and the first drain structure 313 constitutes a channel of the front side transistor.

Twenty-step: the dummy gate structure 83 is removed and a first dielectric wall fork 291 and a first gate structure 311 are formed.

Referring to fig. 22, a thin film deposition process and a chemical mechanical polishing process may be used to form a second interlayer dielectric layer 822 on the basis of the structure shown in fig. 21, and the material of the second interlayer dielectric layer 822 includes silicon oxide; removing part of the dummy gate structure 83 and the reserved second isolation layer 22A, filling metal materials in the positions where the dummy gate structure 83 and the reserved second isolation layer 22A are removed, and performing planarization treatment to form an initial gate; the initial gate is etched to form a gate isolation trench, and the gate isolation trench is filled with a gate isolation material to form a first dielectric wall yoke 291, wherein the first dielectric wall yoke 291 separates the initial gate into a first gate structure 311 and a second gate structure 411, and at this time, the gate structures of a pair of front transistors can be simultaneously fabricated and physically isolated by the first dielectric wall yoke 291.

In some embodiments, the first gate structure is physically isolated from the first source structure 312 and the first drain structure 313 by a spacer layer a, avoiding direct contact to cause leakage.

It should be noted that, before the dummy gate structure 83 and the second isolation layer 22A are filled with the metal material, one or more gate dielectric layers may be formed by an atomic layer deposition process. The material of the gate dielectric layer includes an electric dielectric material, and in this example, the gate dielectric layer is exemplified as an electric dielectric material with a high dielectric constant (high-k).

Thus, the preparation of a pair of front-side transistors is completed.

Twenty-first step: an interlayer dielectric layer 71 is formed on the source structure, and the interlayer dielectric layer 71 is etched to form an initial first trench 711A.

Referring to fig. 23, an ILD material is deposited on the source structure based on the structure shown in fig. 22 to form an interlayer dielectric layer 71, and the interlayer dielectric layer 71 is etched until the second dielectric layer 82 is stopped according to the position of the power connection in the layout, to form a wider initial first trench 711A. In one example, the location of the power connection is on the side of the first source structure 312.

In some embodiments, interlayer dielectric layer 71 covers second dielectric layer 82 and first source structure 312. In some embodiments, based on different types of transistors, located on the same side of the channel as the first source structure 312 may be the second source structure 412 or the second drain structure 413. In this example, the first source structure 312 and the second source structure 412 are located on the same side of the channel.

Twenty-second step: the second dielectric layer 82 and the remaining third isolation layer 232 are etched to form a first trench 711.

Referring to fig. 24, on the basis of the structure shown in fig. 23, the initial first trench 711A is further etched, and the second dielectric layer 82, the remaining third isolation layer 232, and the insulating layer around the first power rail 27 are removed to expose the first power rail 27, so that a conductive path (i.e., the first trench 711) between the first source structure 312 and the first power rail 27 is formed.

Twenty-third step: the first trench 711 is filled with a metal material to form a first metal communication structure 712 connecting the first source structure 312 and the first power rail 27, and then, a first metal interconnection layer 715 is formed by a subsequent process to connect the second source structure 412 (see fig. 25).

To this end, the first source structure 312 is formed to be connected to the first power rail 27 at a side surface of the first source structure 312, and the first source structure 312 connected to the first power rail 27 does not need to be led out.

In some embodiments, the first power rail 27 is connected to the first source structure 312 through a first metal communication structure 712 and to the second source structure 412 through a second metal communication structure 713, as shown in fig. 26 (a). The first power rail 27 is connected to the first source structure 312 through a first metal communication structure 712 or to the second source structure 412 through a second metal communication structure 713, as shown in (b) or (c) and in fig. 26. Of course, in other embodiments, as shown in fig. 26 (d), the first metal communication structure 712 and the second metal communication structure 713 may be omitted, and the first power rail 27 is connected to other logic circuits, which is not specifically limited in the embodiments of the present disclosure.

Twenty-fourth step: the semiconductor structure is wafer bonded and reworked (see fig. 27).

Twenty-fifth step: the substrate 24 and STI 30 are removed until a second portion 202 of a pair of active structures 20 is exposed (see fig. 28).

Twenty-sixth step: the same process is used to fabricate the backside transistor, the second power rail 272, and the second metal interconnect layer 714 in accordance with the seventh through twenty-third steps described above. Further, a third metal communication structure 716 and/or a fourth metal communication structure 717 may also be prepared (see fig. 29).

Thus, the stacked fork plate transistor 10, in which the first semiconductor is a nano-plate field effect transistor, is prepared.

In the embodiment of the application, when the front-side transistor and the back-side transistor are planar transistors or fin field effect transistors, other structures are the same as those of the stacked fork-plate transistor formed by the nano-sheet field effect transistors except that the front-side active structure and the back-side active structure of the stacked fork-plate transistor formed by the nano-sheet field effect transistors are different from those of the front-side active structure and the back-side active structure of the stacked fork-plate transistor formed by the nano-sheet field effect transistors; accordingly, except for the difference between the preparation processes of the front-side active structure and the back-side active structure, the preparation processes of the other structures are the same as those shown in the above examples, and the description of the embodiments of the present application will be omitted.

In the embodiment of the application, the front active structure is symmetrically arranged at two sides of the dielectric fork plate structure, the back active structure is symmetrically arranged at two sides of the dielectric fork plate structure, the front transistor comprises the first front transistor and the second front transistor which are symmetrically arranged at two sides of the dielectric fork plate structure, and the back transistor comprises the first back transistor and the second back transistor which are symmetrically arranged at two sides of the dielectric fork plate structure, so that the interval between devices symmetrically arranged at two sides of the dielectric fork plate structure can be reduced, and the integration density is improved.

Further, stacking the fork plate transistor enables a combination of the stacked transistor and the fork plate transistor, and further improves integration density while enabling self-alignment of the front side transistor and the back side transistor.

An embodiment of the present application provides a semiconductor device including: the power rail of the stacked fork transistor according to the above embodiment may be specifically defined by referring to the stacked fork transistor shown in fig. 2, and will not be described herein.

An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device includes the stacked fork plate transistor described above. For specific limitation of the stacked fork transistor, reference may be made to the stacked fork transistor shown in fig. 2 and will not be described herein.

In the description of the present application, a description of the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1.A method of fabricating a stacked fork plate transistor, comprising:

forming a first semiconductor structure on a substrate, the first semiconductor structure comprising: the device comprises a pair of active structures and a shallow trench isolation layer, wherein the active structures comprise a first part and a second part, the first part is farther away from a substrate than the second part, and at least a first sacrificial layer and an isolation layer which are stacked in sequence are arranged between the first part and the second part along the direction vertical to the substrate; the shallow trench isolation layer wraps the first part and is flush with the first sacrificial layer;

Forming a first power rail on the first semiconductor structure, the first power rail being located between first portions of the pair of active structures;

Forming a first dielectric wall structure on the first power rail;

Forming a second semiconductor structure and a third semiconductor structure based on the first portion of the pair of active structures, the second semiconductor structure including a first gate structure, a first source structure, and a first drain structure, the third semiconductor structure including a second gate structure, a second source structure, and a second drain structure; the first gate structure is isolated from the second gate structure by a first dielectric wall fork plate on the first dielectric wall structure;

Removing the isolation layer and forming a first metal communication structure connected with the first power rail in the first source electrode structure;

Forming a first metal interconnection layer on the second semiconductor structure and the third semiconductor structure;

rewinding the second semiconductor structure and the third semiconductor structure;

Removing a portion of the substrate and the shallow trench isolation layer until a second portion of the pair of active structures is exposed;

Forming a second dielectric wall structure between a second portion of the pair of active structures;

forming a fourth semiconductor structure and a fifth semiconductor structure based on the second portion of the pair of active structures, the fourth semiconductor structure including a third gate structure, a third source structure, and a third drain structure, the fifth semiconductor structure including a fourth gate structure, a fourth source structure, and a fourth drain structure; the third gate structure is isolated from the fourth gate structure by a second dielectric wall fork plate on the second dielectric wall structure;

a second metal interconnect layer is formed over the fourth semiconductor structure and the fifth semiconductor structure.

2. The method of claim 1, wherein after said removing the isolation layer, the method further comprises:

A second metal communication structure is formed in the second source structure that is connected to the first power rail.

3. The method of claim 1, wherein a second sacrificial layer is further disposed between the first portion and the second portion in a direction perpendicular to the substrate, the second sacrificial layer being closer to the second portion than the first sacrificial layer;

After said removing a portion of the substrate and the shallow trench isolation layer until a second portion of the pair of active structures is exposed, the method further comprises:

forming a second power rail on another portion of the shallow trench isolation layer, the second power rail being located between a second portion of the pair of active structures;

after the forming of the fourth semiconductor structure and the fifth semiconductor structure based on the second portion of the pair of active structures, the method further comprises:

And removing the second sacrificial layer, and forming a third metal communication structure connected with the second power rail in the third source electrode structure.

4. The method of claim 3, wherein after said removing said second sacrificial layer, said method further comprises:

A fourth metal communication structure is formed in the fourth source structure that is connected to the second power rail.

5. The method of claim 1, wherein forming a first power rail on the first semiconductor structure comprises:

depositing an oxide on the first semiconductor structure to form a first insulating layer;

depositing a metal material on the first insulating layer to form a first metal structure;

etching the first metal structure to a preset height to form a second metal structure;

Etching a region of the second metal structure outside the first portions of the pair of active structures to obtain a third metal structure between the second portions of the pair of active structures;

an oxide is deposited over the third metal structure to form the first power rail.

6. The method of claim 1, wherein forming a first metal communication structure in the first source structure that is connected to the first power rail comprises:

depositing a semiconductor material on the first source electrode structure to form an interlayer dielectric layer;

Etching the interlayer dielectric layer until the first power rail is exposed, so as to form a first groove;

And filling a metal material in the first groove to form the first metal communication structure.

7. The method of claim 1, wherein after forming a first dielectric wall structure on the first power rail, the method further comprises:

the first dielectric wall fork plate is formed on the first dielectric wall structure based on an isolation material.

8. A stacked fork plate transistor, characterized in that it is prepared by the method of any one of claims 1 to 7; the stacked fork plate transistor includes: a second semiconductor structure, a third semiconductor structure, a fourth semiconductor structure, a fifth semiconductor structure, a first power rail, a first dielectric wall structure, a first dielectric wall fork plate, a second dielectric wall structure and a second dielectric wall fork plate, wherein the first dielectric wall fork plate is positioned on the first dielectric wall structure, and the second dielectric wall fork plate is positioned on the second dielectric wall structure; the first power rail is located between the second semiconductor structure and the third semiconductor structure;

The second semiconductor structure comprises a first gate structure, a first source structure and a first drain structure, and the third semiconductor structure comprises a second gate structure, a second source structure and a second drain structure; the first gate structure is isolated from the second gate structure by the first dielectric wall fork plate; the fourth semiconductor structure comprises a third gate structure, a third source structure and a third drain structure, and the fifth semiconductor structure comprises a fourth gate structure, a fourth source structure and a fourth drain structure; the third gate structure is isolated from the fourth gate structure by the second dielectric wall fork plate;

The stacked fork plate transistor further includes at least one of:

the second semiconductor structure further comprises a first metal communication structure connected with the first source structure and the first power rail;

the third semiconductor structure further includes a second metal communication structure connected with the second source structure and the first power rail.

9. The stacked fork plate transistor of claim 8, further comprising a second power rail located between the fourth semiconductor structure and the fifth semiconductor structure;

The stacked fork plate transistor further includes at least one of:

The fourth semiconductor structure further comprises a third metal communication structure connected with the third source structure and the second power rail;

The fifth semiconductor structure further includes the fourth metal communication structure connected with the fourth source structure and the second power rail.

10. An electronic device, comprising: a circuit board and the stacked fork transistor of claim 8 or 9, the stacked fork transistor being disposed on the circuit board.