CN118248633A - Preparation method of stacked transistor, device and equipment - Google Patents

Preparation method of stacked transistor, device and equipment Download PDF

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Publication number
CN118248633A
CN118248633A CN202410443039.4A CN202410443039A CN118248633A CN 118248633 A CN118248633 A CN 118248633A CN 202410443039 A CN202410443039 A CN 202410443039A CN 118248633 A CN118248633 A CN 118248633A
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Prior art keywords
transistor
active
semiconductor
active structure
forming
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Inventor
吴恒
葛延栋
卢浩然
吴旭升
卜伟海
王润声
黎明
黄如
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Beijing Intellectual Property Management Co ltd
Peking University
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Beijing Intellectual Property Management Co ltd
Peking University
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Priority to CN202410443039.4A priority Critical patent/CN118248633A/en
Publication of CN118248633A publication Critical patent/CN118248633A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application provides a preparation method of a stacked transistor, the stacked transistor, a device and equipment. The preparation method comprises the following steps: forming an active structure on a substrate, the active structure comprising a first active structure and a second active structure, the first active structure being remote from the substrate relative to the second active structure; forming a shallow trench isolation structure on the substrate and exposing the first active structure; forming a first transistor based on the first active structure; rewinding the first transistor and exposing the second active structure; forming a second transistor based on the second active structure; wherein after exposing the first active structure and/or after exposing the second active structure, a semiconductor structure is formed, the semiconductor structure being used to isolate the first transistor from the second transistor.

Description

Preparation method of stacked transistor, device and equipment
Technical Field
The present application relates to the field of integrated semiconductors, and in particular, to a method for manufacturing a stacked transistor, a device, and an apparatus.
Background
While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. The stacked transistor stacked transistor further improves the transistor integration density by integrating two or more layers of transistors in a vertical space, which is one of the important technologies for continuing the miniaturization of integrated circuit dimensions.
In the related art, in the fabrication of stacked transistors, shallow trench isolation (shallow trench isolation, STI) structures are typically formed on a substrate, and then front-side and back-side transistors (upper and lower transistors) are formed on the STI based on active structures. However, some etching operations during the fabrication of the upper and lower transistors may cause STI loss, resulting in the problem of upper and lower transistor cross-over in the stacked transistors.
Disclosure of Invention
The application provides a preparation method of a stacked transistor, the stacked transistor, a device and equipment, which can solve the problem of the series connection of upper and lower layers of transistors in the stacked transistor.
In a first aspect, an embodiment of the present application provides a method for manufacturing a stacked transistor, including: forming an active structure on a substrate, the active structure comprising a first active structure and a second active structure, the first active structure being remote from the substrate relative to the second active structure; forming a shallow trench isolation structure on the substrate and exposing the first active structure; forming a first transistor based on the first active structure; rewinding the first transistor and exposing the second active structure; forming a second transistor based on the second active structure; wherein after exposing the first active structure and/or after exposing the second active structure, a semiconductor structure is formed, the semiconductor structure being used to isolate the first transistor from the second transistor.
In one possible embodiment, after exposing the first active structure, forming a semiconductor structure includes: depositing a semiconductor material on the shallow trench isolation structure to form a semiconductor structure; forming a first transistor based on the first active structure, comprising: on the semiconductor structure, a first transistor is formed based on the first active structure.
In one possible embodiment, exposing the second active structure includes: removing the substrate; and thinning the shallow trench isolation structure to a preset height so as to expose the second active structure.
In one possible embodiment, after exposing the second active structure, forming a semiconductor structure includes: depositing semiconductor material on the reserved shallow trench isolation structure to form a semiconductor structure; forming a second transistor based on the second active structure, comprising: on the semiconductor structure, a second transistor is formed based on the second active structure.
In one possible embodiment, the semiconductor structure comprises a first semiconductor material, or the semiconductor structure comprises at least a first semiconductor material and a second semiconductor material alternately stacked in sequence along the direction of arrangement of the active structure.
In one possible implementation, forming a first transistor based on a first active structure includes: epitaxially growing a first source-drain structure on the first active structure; forming a first gate structure based on the first active structure; forming a first source drain metal on the first source drain structure; forming a second transistor based on the second active structure, comprising: epitaxially growing a second source-drain structure on the second active structure; forming a second gate structure based on the second active structure; and forming a second source-drain metal on the second source-drain structure.
In one possible implementation, the first transistor is one of a fin field effect transistor, a fully-around gate transistor, and a planar transistor, and the second transistor is one of a fin field effect transistor, a fully-around gate transistor, and a planar transistor.
In a second aspect, an embodiment of the present application provides a stacked transistor, which is manufactured by the method described in the first aspect and any embodiment thereof, including: a first transistor; the first transistor and the second transistor are arranged in a back-to-back manner; the semiconductor structure is used for isolating the first transistor from the second transistor.
In one possible implementation, the first transistor is one of a fin field effect transistor, a fully-around gate transistor, and a planar transistor, and the second transistor is one of a fin field effect transistor, a fully-around gate transistor, and a planar transistor.
In a third aspect, an embodiment of the present application provides a semiconductor device, including: a stacked transistor as described in the second aspect above.
In a fourth aspect, an embodiment of the present application provides an electronic device, including: a circuit board and the semiconductor device according to the third aspect, the semiconductor device being provided to the circuit board.
The technical scheme provided by the application can comprise the following beneficial effects:
In the embodiment of the application, a shallow trench isolation structure is formed on a substrate, and then a first transistor is formed based on the exposed first active structure; and rewinding the first transistor to form a second transistor based on the exposed second active structure; after the first active structure is exposed and/or after the second active structure is exposed, the semiconductor structure is formed to isolate the first transistor from the second transistor. Thus, embodiments of the present application may form semiconductor structures on the front and/or back sides of the stacked transistors, and then form front and/or back side transistors on the semiconductor structures. That is, a semiconductor structure exists between the front side transistor and the back side transistor, so that the problem of the cross-over of the upper and lower layer transistors in the stacked transistor can be solved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic flow chart of a method for manufacturing a stacked transistor according to an embodiment of the present application;
FIG. 2 is a schematic top view of a stacked transistor according to an embodiment of the present application;
fig. 3 to 9 are schematic structural views of stacked transistors in a first manufacturing process according to an embodiment of the present application;
fig. 10 is a schematic diagram of a first structure of a stacked transistor according to an embodiment of the present application;
Fig. 11 to 15 are schematic structural views of stacked transistors in a second manufacturing process according to an embodiment of the present application;
FIG. 16 is a schematic diagram of a second structure of a stacked transistor according to an embodiment of the present application;
fig. 17 to 23 are schematic structural views of stacked transistors in a third manufacturing process according to an embodiment of the present application;
fig. 24 is a schematic diagram of a third structure of a stacked transistor according to an embodiment of the present application;
fig. 25 to 33 are schematic structural views of a stacked transistor in a fourth manufacturing process according to an embodiment of the present application;
Fig. 34 to 37 are schematic views showing a fourth structure of a stacked transistor according to an embodiment of the present application;
fig. 38 to 43 are schematic structural views of a stacked transistor in a fifth manufacturing process according to an embodiment of the present application;
FIG. 44 is a fifth schematic diagram of a stacked transistor according to an embodiment of the present application;
FIG. 45 is a schematic diagram of a sixth structure of a stacked transistor according to an embodiment of the present application;
FIG. 46 is a schematic top view of another stacked transistor according to an embodiment of the present application;
fig. 47 to 48 are schematic views of a seventh structure of a stacked transistor according to an embodiment of the present application.
The figures above:
10. Stacking transistors; 11. a first transistor (front side transistor); 111. a first active structure; 112. a first source drain structure; 113. a first interlayer dielectric layer; 114. a first gate structure; 115. a first source drain metal; 116. a first metal interconnect layer; 12. a second transistor (back side transistor); 121. a second active structure; 122. a second source drain structure; 123. a second interlayer dielectric layer; 124. a second gate structure; 125. a second source drain metal; 126. a second metal interconnect layer; 20. a substrate; 21. an active structure; 22. shallow trench isolation structures; 23. a first semiconductor structure; 24. an insulating layer; 25. a carrier wafer; 26. a second semiconductor structure; 27. and a BOX layer.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.
While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits.
In one embodiment, the fabrication process of the stacked transistor has two schemes, the first is a monolithic scheme and the second is a sequential scheme.
In the first approach, N-channel field effect transistors (N FIELD EFFECT transistors, NFETs) and P-channel field effect transistors (P FIELD EFFECT transistors, PFETs) are fabricated on the same substrate, and substrate bonding techniques are not employed. This determines that the same layer transistors must be of the same type, i.e., NFET or PFET. And the transistors on the upper layer and the lower layer are strictly in the same plane space, and no alignment deviation exists. The advantage of this solution is a better integration density. Drawbacks of this approach include the following two points: (1) The process is complex, and a large number of process technologies need to be developed and optimized; (2) Each layer of transistors has a fixed polarity, and two layers of transistors must be relied upon to form a basic Complementary Metal Oxide Semiconductor (CMOS) circuit, which has poor design flexibility.
The second approach is based on substrate bonding and layer-by-layer processing. Specifically, the two transistors are vertically stacked by bonding a substrate on top of the fabricated lower transistor to prepare an upper transistor. However, this approach requires tight temperature control during the thermal process of processing the upper layer transistors, avoiding affecting the lower layer transistors and the interconnect lines. The scheme has the advantages that the device structure, the channel crystal orientation and even the channel material adopted by the upper layer transistor and the lower layer transistor can be correspondingly optimized to obtain better and more matched device performance due to substrate bonding. This solution currently presents the following technical challenges: (1) preparation of a high-quality upper transistor active layer; (2) thinning and defect control of the upper bonded substrate; (3) The upper and lower layer transistors have alignment errors and have extremely high requirements on photoetching precision.
From the common point of view, the two schemes have the following technical difficulties: (1) Thermal stability of the bottom layer transistor when the top layer transistor is prepared; (2) performance of top-level transistors at low thermal budget; (3) layer-to-layer transistor metal interconnect.
The self-aligned flip-chip stacked transistor is an organic fusion of a sequential scheme and a single-chip scheme, and gives consideration to the problems of consistency, defect density, alignment, thermal budget and the like of active regions of upper and lower layers of transistors.
In the process scheme of self-aligned flip-chip stacked transistors, there is a problem of STI loss. For example, when forming the source-drain structure, the source-drain regions of the stacked transistor are etched to form recesses for epitaxially growing the source-drain structure. In this case, some STI may be etched, which causes problems such as source-drain crosstalk and source-drain metal crosstalk in the upper and lower transistors.
Based on the above-mentioned problems, the embodiment of the application provides a method for manufacturing a stacked transistor, which can solve the problem of crosstalk between upper and lower transistors in the stacked transistor.
In the embodiment of the application, the stacked transistor can be applied to semiconductor devices such as memories, processors and the like.
In an embodiment, the stacked transistor may include at least two transistors, for example, a first transistor and a second transistor, which are stacked, the first transistor being formed based on a first active structure, the second transistor being formed based on a second active structure, and the first active structure and the second active structure being formed through the same process, so it may be understood that the first transistor and the second transistor are self-aligned. Furthermore, the stacked transistor further includes a semiconductor structure for isolating the first transistor from the second transistor.
In the embodiment of the application, the first transistor and the second transistor in the semiconductor structure are transistors of the same type, such as any one of the following: a fin field effect transistor (FIN FIELD EFFECT transistor, finFET), a full-around gate transistor (gate-all-around FIELD EFFECT transistor, GAAFET), and a planar transistor (planar transistor).
Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing a stacked transistor according to an embodiment of the application, and as shown in fig. 1, the method for manufacturing a stacked transistor includes the following steps.
Step S110: an active structure is formed on a substrate structure.
The active structure comprises a first active structure and a second active structure, and the first active structure is far away from the substrate relative to the second active structure.
In some embodiments, the implementation procedure of step S110 may be: providing a substrate; the first portion of the substrate is etched to form an active structure.
The substrate may be, for example, any semiconductor substrate such as a silicon (Si) substrate, a germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or the like.
In one embodiment, the SOI substrate comprises a three-layer structure: a thin top silicon (thin top silicon) layer, a Buried Oxide (BOX) layer, and a bottom silicon wafer (base silicon) layer that acts as a support. That is, a BOX layer is disposed between the top silicon and the bottom silicon substrate, and the SOI substrate can realize dielectric isolation of components in the integrated circuit, and eliminate parasitic latch-up in the bulk silicon CMOS circuit. The integrated circuit prepared by the SOI substrate has the advantages of small parasitic capacitance, high integration density, high speed, simple process, small short channel effect, particular suitability for low-voltage and low-power consumption circuits and the like. In a self-aligned flip-chip stacked transistor structure, the BOX layer may act as a natural isolation of the front-side and back-side transistor active regions, reducing coupling between stacked transistors.
After providing the substrate, a number of active structures upstanding from the substrate may be formed on the substrate, also immediately etching the first portion of the substrate to form the active structures.
In an embodiment, the etching of the first portion of the substrate to form the active structure may be performed by: forming an epitaxial layer on the surface of the substrate through an epitaxial growth process; the epitaxial layer is etched to a depth into the epitaxial layer or to the substrate surface or to a depth into the substrate, thereby forming a plurality of active structures.
Here, each active structure includes a first active structure and a second active structure, the first active structure being farther from the substrate than the second active structure.
The substrate is illustratively etched to form active structures such as fin structures extending in the same direction, parallel-disposed nanoplatelets, bulk planar structures, and the like in the active region. Wherein, in the case that the active structure is a fin structure, the transistor is a fin field effect transistor; in the case that the active structure is a plurality of nano-sheets arranged in parallel, the transistor is a fully-around gate transistor; in the case where the active structure is a bulk planar structure, the transistor is a planar transistor.
The etching process may be at least one of dry etching, wet etching, reactive ion etching, and the like, for example.
It can be appreciated that in the embodiment of the present application, since the upper and lower transistors in the stacked transistor share the active structure, that is, the first active structure of the upper transistor (front transistor) and the second active structure of the lower transistor (back transistor) are formed by the same etching process, a larger etching depth can be used when forming the active structure on the substrate, so as to obtain a higher active structure. For example, the height of the etched active structure may be made greater than 100 nanometers (nm).
Step S120: shallow trench isolation structures are formed on the substrate and the first active structures are exposed.
It will be appreciated that after the active structure is formed, oxide material may be deposited on the second portion of the substrate and the surface of the active structure to form a shallow trench isolation structure that encapsulates the second active structure.
It will be appreciated that oxide material may be deposited on the surfaces of the substrate and the active structure and a chemical-mechanical planarization (CMP) process may be used to remove the top surface of the oxide material until the top surface of the active structure is exposed, thereby forming a shallow trench isolation structure having a top surface level with the top surface of the active structure, and further etching back the shallow trench isolation structure to a depth such that the shallow trench isolation structure wraps around the second active structure, exposing the first active structure.
The oxide material forming the shallow trench isolation structure may be any of the following, for example: silicon nitride (SiN, si3N 4), silicon dioxide (SiO 2), silicon oxycarbide (SiCO), or the like.
In addition, the embodiment of the application can protect the shallow trench isolation structure at the front side transistor so as to avoid crosstalk between the front side transistor and the back side transistor. Based on this, in some embodiments, after exposing the first active structure, a semiconductor structure may be formed for isolating the first transistor (front side transistor) and the second transistor (back side transistor).
In some embodiments, the implementation of forming the semiconductor structure may be: a semiconductor material is deposited over the shallow trench isolation structure to form a semiconductor structure.
In some embodiments, the semiconductor structure may include a first semiconductor material, or the semiconductor structure may include at least a first semiconductor material and a second semiconductor material alternately stacked in sequence along an arrangement direction of the active structure.
The first semiconductor material may include a dielectric material such as silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), and the like, and the second semiconductor material may be a material used for forming a shallow trench isolation structure, such as an oxide material SiO2, and the like.
It will be appreciated that after the shallow trench isolation structure is formed, a first semiconductor material and a second semiconductor material may be deposited sequentially over the shallow trench isolation structure, or only a layer of the first semiconductor material may be deposited to form the semiconductor structure. That is, the semiconductor structure may include only one layer of the first semiconductor material, or may include a plurality of layers of semiconductor materials stacked by stacking the first semiconductor material and the second semiconductor material.
In one example, a layer of SiN dielectric material may be deposited over the shallow trench isolation structure and a further layer of STI deposited to form a semiconductor structure including SiN-STI.
In another example, a SiN dielectric material and STI may also be deposited sequentially over the shallow trench isolation structure to form a semiconductor structure including SiN-STI-SiN-STI.
Step S130: a first transistor is formed based on the first active structure.
By means of a first one of the active structures, a front-side transistor, i.e. a first transistor, of the stacked transistors can be prepared.
In the case of depositing a semiconductor material on the shallow trench isolation structure to form a semiconductor structure in step S120, the embodiment of the present application may form a first transistor on the semiconductor structure based on the first active structure. Thus, the semiconductor structure can serve as isolation between the first transistor and the second transistor.
In some embodiments, the implementation procedure of step S130 may be: epitaxially growing a first source-drain structure on the first active structure; forming a first gate structure based on the first active structure; and forming a first source-drain metal on the first source-drain structure.
It will be appreciated that after the shallow trench isolation structure is formed, semiconductor material may also be deposited in the gate region of a first transistor in the stacked transistors to form a first dummy gate structure; forming first spacers (spacers) on both sides of the first dummy gate structure; and forming a first source drain structure on the first dummy gate structure and the first active structure on two sides of the first spacer.
In an embodiment, the semiconductor material forming the first dummy gate structure may be polysilicon, amorphous silicon, or the like.
The first spacer is used for isolating the first source-drain structure and the first grid structure. The structure of the first spacer may be set according to actual requirements, which is not particularly limited in the embodiment of the present application.
Illustratively, the first spacer may have a single layer structure, and be entirely made of the same material, such as porous carbon silicon oxide (SiCOH).
In some embodiments, the implementation process of forming the first source-drain structure on the first dummy gate structure and the first active structure on both sides of the first spacer may be: etching a first active structure of the first transistor in the source drain region to form a first source drain groove, and performing source drain epitaxial growth at the first source drain groove to form a first source drain structure.
For example, a strained material such as silicon germanium or silicon carbide may be formed in the source-drain recess by selective epitaxial growth to fill the source-drain recess of the first transistor, and then a first source-drain structure may be formed on the strained material by a heavy doping process.
In some embodiments, after forming the first source-drain structure, an interlayer dielectric may be further deposited on the first source-drain structure, and the interlayer dielectric may be thinned to a top layer of the first source-drain structure, so as to form a first interlayer dielectric layer.
For example, an insulating material (such as silicon dioxide SiO 2) may be deposited over the first source-drain structure and the first active structure, and planarized to form a first interlayer dielectric layer, which may cover the first source-drain structure and the first active structure.
The planarization process may be, for example, a CMP process or the like.
After forming the first source-drain structure, a gate structure of the first transistor may be formed, i.e., the first gate structure is formed.
In some embodiments, the first dummy gate structure formed in the foregoing manner may be removed by an etching process to obtain a first gate recess, an insulating material is deposited in the first gate recess to form a first gate dielectric layer, and a metal material is deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together form a first gate structure.
By way of example, the first gate dielectric layer may be formed of a silicon oxide layer plus a K-value hafnium oxide layer, and the thickness of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.
By way of example, the first gate electrode layer may be composed of multiple layers of electrode materials, each layer of electrode material including, but not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).
After forming the first gate structure, a metal material may be deposited on the first source-drain structure formed as described above to form a first source-drain metal.
In some embodiments, in the case of forming the first interlayer dielectric layer after forming the first source-drain structure, the first source-drain metal may be formed in the first interlayer dielectric layer.
For convenience of explanation, the first source-drain structure in the embodiment of the present application is referred to as simply, and specifically refers to the first source structure and/or the first drain structure. In addition, the first source-drain metal, the first source-drain groove, the second source-drain structure, the second source-drain metal, the second source-drain groove and the like are similar to those of the first source-drain structure, wherein 'source-drain' is abbreviated as 'source electrode and/or drain electrode'.
It should be noted that, the first source-drain structure, the first interlayer dielectric layer, the first gate structure, and the first source-drain metal may be formed by standard steps of the semiconductor manufacturing process, which is not particularly limited in the embodiment of the present application.
It should be noted that, the two operations of forming the first source drain metal and forming the first gate structure do not distinguish the sequence, that is, the first source drain metal may be formed first and then the first gate structure may be formed first, or the first gate structure may be formed first and then the first source drain metal may be formed first, which is not limited in the embodiment of the present application. The above embodiments are described taking the first gate structure and then the first source-drain metal as an example.
In addition, in some embodiments, after the first transistor is completed, a first metal interconnection layer may be further formed on the first transistor.
It will be appreciated that a first metal interconnect layer may be formed by performing subsequent processes (e.g., dielectric deposition between interconnect lines, metal line formation, lead-out pad formation, etc.) on the first transistor.
It will be appreciated that the semiconductor structure is formed over the STI and then the first transistor is formed over the semiconductor structure, where the semiconductor structure located over the STI is capable of protecting the STI loss of the source drain region.
Step S140: the first transistor is reworked and the second active structure is exposed.
It is understood that after forming the first transistor comprising the first source drain structure, the first gate structure, the first source drain metal, and the first metal interconnect layer, the first transistor may be bonded to the carrier wafer. The first transistor is then reworked for subsequent preparation of the back side transistor.
In one embodiment, an insulating material (e.g., silicon oxide) may be deposited over the first metal interconnect layer to form a first insulating layer and bond the first insulating layer to the carrier wafer.
In some embodiments, the implementation procedure of exposing the second active structure in step S140 may be: removing the substrate; and thinning the shallow trench isolation structure to a preset height so as to expose the second active structure.
After flipping the second transistor, the substrate may be removed and the shallow trench isolation structure underneath the substrate etched such that the second active structure is exposed to fabricate the second transistor based on the exposed second active structure.
In one embodiment, the substrate may be removed after rewinding using a polishing process or a chemical mechanical planarization process.
After the substrate is removed, the top layer of the second active structure is flush with the top layer of the shallow trench isolation structure, so that the shallow trench isolation structure can be thinned to a preset height, and the peripheral side of the second active structure is exposed, so that a second transistor is formed according to the second active structure exposed on the peripheral side.
The preset height can be set according to actual requirements, which is not limited in the embodiment of the present application.
For example, a portion of the shallow trench isolation structure may be etched, or the shallow trench isolation structure may be completely etched, which is not limited in the embodiment of the present application.
In addition, the embodiment of the application can also be used as a semiconductor structure at the back side transistor. Based on this, in some embodiments, the semiconductor structure may be formed after exposing the second active structure.
In some embodiments, the implementation of forming the semiconductor structure may be: depositing semiconductor material on the remaining shallow trench isolation structure to form a semiconductor structure.
The method for forming the semiconductor structure at the back side transistor may refer to the related content of forming the semiconductor structure at the front side transistor in the step S120, which is not described herein.
Illustratively, a layer of SiN material may be deposited over the remaining shallow trench isolation structures as a semiconductor structure.
In the case of fully etching the shallow trench isolation structure, if a semiconductor structure has been formed at the front side transistor, the semiconductor structure is again formed on the semiconductor structure formed by the front side transistor. If the semiconductor structure is not formed at the front side transistor, the semiconductor structure is formed on the front side transistor.
That is, the semiconductor structure in the embodiment of the present application may be formed only at the single-sided transistor, that is, only at the front-sided transistor, or only at the back-sided transistor, or may be formed at both the front and back-sided transistors, which is not limited in the embodiment of the present application.
Step S150: a second transistor is formed based on the second active structure.
After the front-side transistor is reworked, the back-side transistor, i.e. the second transistor, in the stacked transistor may be prepared based on the exposed second active structure.
In the case of depositing semiconductor material at the back side transistor to form a semiconductor structure in step S140, embodiments of the present application may form a second transistor on the semiconductor structure based on the second active structure. Thus, the semiconductor structure can serve as isolation between the first transistor and the second transistor.
In some embodiments, the implementation procedure of step S150 may be: epitaxially growing a second source-drain structure on the second active structure; forming a second gate structure based on the second active structure; and forming a second source-drain metal on the second source-drain structure.
In some embodiments, after forming the second source-drain structure, an interlayer dielectric may be further deposited on the second source-drain structure, thinned to a top layer of the second source-drain structure to form a second interlayer dielectric layer, and then a second source-drain metal is formed in the second interlayer dielectric layer.
The preparation methods of the second source-drain structure, the second interlayer dielectric layer, the second gate structure and the second source-drain metal of the second transistor are the same as those of the first source-drain structure, the first interlayer dielectric layer, the first gate structure and the first source-drain metal of the first transistor, and are not described herein again.
It should be noted that, because the second source-drain structure is epitaxially grown based on the second active structure, the first source-drain structure is epitaxially grown based on the first active structure, and the first active structure and the second active structure are self-aligned structures, the second source-drain structure and the first source-drain structure are self-aligned structures, so that symmetry of the stacked transistor structure is effectively improved.
After the second transistor is completed, a second metal interconnection layer may be formed on the second transistor.
The implementation process of forming the second metal interconnection layer may be related to forming the first metal interconnection layer on the first transistor in the step S130, which is not described herein.
In the embodiment of the application, a shallow trench isolation structure is formed on a substrate, and then a first transistor is formed based on the exposed first active structure; and rewinding the first transistor to form a second transistor based on the exposed second active structure; after the first active structure is exposed and/or after the second active structure is exposed, the semiconductor structure is formed to isolate the first transistor from the second transistor. Thus, embodiments of the present application may form semiconductor structures on the front and/or back sides of the stacked transistors, and then form front and/or back side transistors on the semiconductor structures. That is, a semiconductor structure is present between the front side transistor and the back side transistor, which can solve the problem of crosstalk between the upper and lower layer transistors in the stacked transistor. Therefore, the embodiment of the application optimizes the process scheme of the flip-chip stacked transistor, solves the problem that the STI loss of the source-drain region possibly leads to the crosstalk of transistors on the upper layer and the lower layer, and provides a process scheme with better STI isolation regulation. And comprehensively considers the influences of various process viable schemes and possible structures, parasitic capacitance and other device characteristics.
Furthermore, the scheme of the embodiment of the application optimizes the process flow of the stacked transistor, and also considers the problems of consistency, defect density, alignment, thermal budget and the like of the active region and the grid electrode of the upper layer transistor and the lower layer transistor.
In addition, the flip-chip stacked transistor is also an organic fusion of the current sequence and the single-chip stacked transistor scheme, so that the mature technology has high multiplexing degree, can avoid a great deal of high-cost process development to save cost, and has high feasibility. Meanwhile, the flip-chip stacked transistor adopts a self-aligned back-to-back active area and metal grid design, the front and back transistors have independent signal and power supply networks and are connected through local interconnection, metal wiring resources are greatly released under the condition of not changing the extremely miniature 4T track unit design, and the space is huge in the process design collaborative optimization direction. And the flip-chip stacked transistor scheme is compatible with the existing mainstream device architecture, can realize front-back stacking of planar transistors, finFETs, GAA Nanosheet and even vertical transistors (VTFET), does not need special process development aiming at specific device architecture, and has strong flexibility. From the iteration point of view of the semiconductor processing node, the extensibility is very strong. The flip-chip stacked transistor is very advanced in concept, has important industrial value, and has strong practicability and wide expansion prospect.
The following describes a method for manufacturing a stacked transistor according to an embodiment of the present application, taking an active structure in the stacked transistor as a fin structure as an example. Fig. 2 is a schematic top view of a stacked transistor according to an embodiment of the application. For ease of understanding, only fin structures, gate structures, and source-drain structures are shown in top view. Wherein the A-A' direction is the tangential direction of the stacked transistor along the gate structure; the B-B' direction is the tangential direction of the stacked transistor along the source-drain structure; the C-C' direction is the tangential direction of the stacked transistor along the fin structure.
Next, a first process of forming a semiconductor structure including two layers of semiconductor materials only at the positive transistor is described, fig. 3 to 9 are schematic structural diagrams of the stacked transistor in the first process of forming the stacked transistor according to the embodiment of the present application, and fig. 10 is a schematic structural diagram of the stacked transistor according to the embodiment of the present application. Fig. 3 to 10 (a) are cross-sectional views along a cross-sectional direction (i.e., A-A ' direction) of the gate structure, fig. 3 to 10 (B) are cross-sectional views along a cross-sectional direction (i.e., B-B ' direction) of the source-drain structure, and fig. 3 to 10 (C) are cross-sectional views along a cross-sectional direction (i.e., C-C ' direction) of the fin structure.
In one example, the first fabrication process of stacked transistor 10 may include the steps of:
the first step: the silicon substrate (wafer) 20 is etched using standard processes to form fin structures (active structures) 21 resulting in the structure shown in fig. 3.
And a second step of: oxide material is deposited on the substrate 20 to form shallow trench isolation structures 22 resulting in the structure shown in fig. 4.
Wherein a filled STI oxide is deposited on the substrate 20 and CMP is performed to form shallow trench isolation structures 22, where the shallow trench isolation structures 22 cover the fin structures 21.
And a third step of: STI 22 is etched to expose first fin structure 111, resulting in the structure shown in fig. 5.
Wherein the fin structure 21 comprises a portion distant from the substrate 20, i.e. a first fin structure (first active structure) 111, and a portion close to the substrate 20, i.e. a second fin structure (second active structure) 121.
Fourth step: a first semiconductor structure 23 is formed over the STI 22 resulting in the structure shown in fig. 6.
As shown in fig. 6, an isolation layer may be formed on the STI, and the isolation layer may include, but is not limited to, dielectric materials such as SiN, siCN SiON, etc., and the STI may be formed on the isolation layer, and the first semiconductor structure 23 may include the isolation layer and the STI.
Fifth step: on the first semiconductor structure 23, a front-side transistor is fabricated using standard processes based on the first fin structure 111, and the subsequent process of the front-side transistor is completed, resulting in the structure shown in fig. 7.
The front side transistor may include a first source drain structure 112, a first interlayer dielectric layer 113, a first gate structure 114, and a first source drain metal 115.
It will be appreciated that a polysilicon material may be deposited in the gate region of the stacked transistor, forming a first dummy gate structure, and forming a first spacer (spacer) on the sidewalls of the first dummy gate structure, then epitaxially growing a first source-drain structure 112 based on the first fin structure 111 at the source-drain region, and depositing an interlayer dielectric on the first source-drain structure 112 to form a first interlayer dielectric layer 113. The first dummy gate structure is then removed, a first gate structure 114 is formed in the gate region, and a first source drain metal 115 is formed over the first source drain structure 112. The first gate structure 114 includes a first gate dielectric layer and a first gate electrode layer coated on the first fin structure 111.
After the front-side transistor is completed, a subsequent process may be performed on the front-side transistor to form the first metal interconnect layer 116.
Sixth step: oxide is deposited on the first metal interconnect layer 116 to form the insulating layer 24, the carrier wafer 25 is bonded to the insulating layer 24 and then reworked, followed by removal of the substrate 20 to expose the bottom of the fin structure and STI 22, resulting in the structure shown in fig. 8.
Seventh step: STI 22 is etched to a predetermined height to expose second fin structure 121, resulting in the structure shown in fig. 9.
Eighth step: on the remaining STI 22, a back-side transistor is fabricated using standard processes based on the second fin structure 121, and the subsequent process of the back-side transistor is completed, resulting in the structure shown in fig. 10.
The back side transistor may include a second source drain structure 122, a second interlayer dielectric layer 123, a second gate structure 124, and a second source drain metal 125.
It will be appreciated that a polysilicon material may be deposited in the gate region of the stacked transistor, forming a second dummy gate structure, and forming a second spacer on the sidewalls of the second dummy gate structure, then epitaxially growing a second source-drain structure 122 based on the second fin structure 121 at the source-drain region, and depositing an interlayer dielectric on the second source-drain structure 122 to form a second interlayer dielectric layer 123. The second dummy gate structure is then removed, a second gate structure 124 is formed in the gate region, and a second source drain metal 125 is formed over the second source drain structure 122. The second gate structure 124 includes a second gate dielectric layer and a second gate electrode layer coated on the second fin structure 121.
After the back side transistor is completed, a subsequent process may be performed on the back side transistor to form the second metal interconnect layer 126. The fabrication of the first structure of the stacked transistor is completed.
A second process for forming a semiconductor structure including a layer of semiconductor material only at the back side transistor is described below, and fig. 11 to 15 are schematic structural views of the stacked transistor in the second process in the embodiment of the present application, and fig. 16 is a schematic structural view of the stacked transistor in the embodiment of the present application. Here, (a) in fig. 11 to 16 is a cross-sectional view along a tangential direction (i.e., A-A ' direction) of the gate structure, (B) in fig. 11 to 16 is a cross-sectional view along a tangential direction (i.e., B-B ' direction) of the source-drain structure, and (C) in fig. 11 to 16 is a cross-sectional view along a tangential direction (i.e., C-C ' direction) of the fin structure.
In one example, the second fabrication process of stacked transistor 10 may include the steps of:
The first step: the substrate 20 is etched to form fin structures 21 and STI 22 is formed, the STI 22 exposing the first fin structure 111, resulting in the structure shown in fig. 11, following standard steps.
Reference is made here to the first to third steps of the preparation process of the first structure described above.
And a second step of: based on the first fin structure 111, a front-side transistor is fabricated using standard processes, and the subsequent process of the front-side transistor is completed, resulting in the structure shown in fig. 12.
There is no first semiconductor structure at the front side transistor, so during the preparation of the front side transistor, there is a certain loss of STI in the source-drain region, while STI in the gate region is not consumed due to the protection of the dummy gate structure. As shown in fig. 12, the STI of the source-drain region in fig. 12 (b) is less than the STI of the gate region in fig. 12 (a), which means that the source-drain region is more likely to cross-over.
And a third step of: oxide is deposited on the first metal interconnect layer 116 to form the insulating layer 24, the carrier wafer 25 is bonded to the insulating layer 24 and then reworked, followed by removal of the substrate 20 to expose the bottom of the fin structure and STI 22, resulting in the structure shown in fig. 13.
Fourth step: STI 22 is etched to a predetermined height to expose second fin structure 121, resulting in the structure shown in fig. 14.
Fifth step: a second semiconductor structure 26 is formed over the STI 22 resulting in the structure shown in fig. 15.
As shown in fig. 15, it can be seen that the second semiconductor structure 26 includes only one isolation layer.
Sixth step: on the second semiconductor structure 26, a back side transistor is fabricated using standard processes based on the second fin structure 121, and the subsequent processing of the back side transistor is completed, resulting in the structure shown in fig. 16.
A third fabrication process is described below, namely forming a semiconductor structure comprising only one layer of semiconductor material at the front-side transistor. Fig. 17 to 23 are schematic structural views of a stacked transistor in a third manufacturing process according to an embodiment of the present application, and fig. 24 is a schematic structural view of a stacked transistor in an embodiment of the present application. Here, (a) in fig. 17 to 24 is a cross-sectional view along a tangential direction (i.e., A-A ' direction) of the gate structure, and (B) in fig. 17 to 24 is a cross-sectional view along a tangential direction (i.e., B-B ' direction) of the source-drain structure, and (C) in fig. 17 to 24 is a cross-sectional view along a tangential direction (i.e., C-C ' direction) of the fin structure.
In one example, a third fabrication process of stacked transistor 10 may include the steps of:
The first step: the substrate 20 is etched to form fin structures 21 and STI 22 in accordance with standard procedures, the STI 22 exposing the first fin structure 111 resulting in the structure shown in fig. 17.
Reference is made here to the first to third steps of the preparation process of the first structure described above.
And a second step of: a first semiconductor structure 23 is formed over the STI 22 resulting in the structure shown in fig. 18.
As shown in fig. 18, the first semiconductor structure 23 includes only one isolation layer.
And a third step of: on the first semiconductor structure 23, a front-side transistor is fabricated using standard processes based on the first fin structure 111, and the subsequent process of the front-side transistor is completed, resulting in the structure shown in fig. 19.
Fourth step: oxide is deposited on the first metal interconnect layer 116 to form the insulating layer 24, the carrier wafer 25 is bonded to the insulating layer 24 and then reworked, followed by removal of the substrate 20 to expose the bottom of the fin structure and STI 22, resulting in the structure shown in fig. 20.
Fifth step: STI 22 is completely etched, exposing second fin structure 121 and first semiconductor structure 23, resulting in the structure shown in fig. 21.
In this case, all STI is consumed, and only the first semiconductor structure 23 is used as isolation between the upper and lower transistors.
Or portions of STI 22 are etched, exposing second fin structure 121, resulting in the structure shown in fig. 22.
In this case, the STI is partially consumed, and thus, the first semiconductor structure 23 and the remaining part of the STI serve as isolation between the upper and lower layer transistors.
Sixth step: based on the structure of fig. 21, on the first semiconductor structure 23, a back side transistor is fabricated using standard processes based on the second fin structure 121, and the subsequent process of the back side transistor is completed, resulting in the structure shown in fig. 23.
Or based on the structure of fig. 22, on the remaining STI 22, a back side transistor is fabricated using standard processes based on the second fin structure 121, and the subsequent process of the back side transistor is completed, resulting in the structure shown in fig. 24.
A fourth fabrication process is described below, namely forming a semiconductor structure comprising multiple layers of semiconductor material at the front-side transistor. Fig. 25 to 33 are schematic structural views of a stacked transistor in a fourth manufacturing process according to an embodiment of the present application, and fig. 34 to 37 are schematic structural views of a stacked transistor in an embodiment of the present application. Here, (a) in fig. 25 to 37 is a cross-sectional view along a tangential direction (i.e., A-A ' direction) of the gate structure, and (B) in fig. 25 to 37 is a cross-sectional view along a tangential direction (i.e., B-B ' direction) of the source-drain structure, and (C) in fig. 25 to 37 is a cross-sectional view along a tangential direction (i.e., C-C ' direction) of the fin structure.
In one example, a fourth fabrication process of stacked transistor 10 may include the steps of:
The first step: the substrate 20 is etched to form fin structures 21 and STI 22 is formed, the STI 22 exposing the first fin structure 111, resulting in the structure shown in fig. 25, following standard steps.
Reference is made here to the first to third steps of the preparation process of the first structure described above.
And a second step of: over the STI 22, a first semiconductor structure 23 is formed, resulting in the structure of fig. 26. The first semiconductor structure 23 here includes an isolation layer, an STI, and an isolation layer stacked in this order. For example, when the isolation layer is a SiN material, the first semiconductor structure 23 may be a SiN-STI-SiN structure.
Alternatively, the first semiconductor structure 23 is formed on the STI 22, resulting in the structure of fig. 27. The first semiconductor structure 23 here includes an isolation layer, an STI, an isolation layer, and an STI stacked in this order. For example, when the isolation layer is a SiN material, the first semiconductor structure 23 may be a SiN-STI-SiN-STI structure.
And a third step of: based on the structure of fig. 26, on the first semiconductor structure 23, a front-side transistor is fabricated using standard processes based on the first fin structure 111, and the subsequent process of the front-side transistor is completed, resulting in the structure shown in fig. 28.
Fourth step: based on the structure of fig. 28, oxide is deposited on the first metal interconnect layer 116 to form the insulating layer 24, the carrier wafer 25 is bonded to the insulating layer 24 and then reworked, followed by removal of the substrate 20 to expose the bottom of the fin structure and STI 22, resulting in the structure shown in fig. 29.
Fifth step: based on the structure of fig. 29, STI 22 is completely etched, exposing the isolation layer of second fin structure 121 and first semiconductor structure 23, resulting in the structure shown in fig. 30.
Or based on the structure of fig. 29, etching a portion of the STI 22, exposing the second fin structure 121 and a portion of the STI 22, resulting in the structure shown in fig. 31.
Or based on the structure formed in the steps from fig. 27 to fig. fourth, STI 22 is completely etched, exposing the isolation layer of second fin structure 121 and first semiconductor structure 23, resulting in the structure shown in fig. 32.
Or based on the structure of fig. 27 through the structure formed in the fourth step, etching a portion of the STI 22 to expose the second fin structure 121 and a portion of the STI 22, resulting in the structure shown in fig. 33.
Sixth step: based on the structure of fig. 30, on the first semiconductor structure 23, a back side transistor is fabricated using standard processes based on the second fin structure 121, and the subsequent process of the back side transistor is completed, resulting in the structure shown in fig. 34.
Alternatively, based on the structure of fig. 31, on the first semiconductor structure 23, based on the second fin structure 121, a back side transistor is fabricated using standard processes, and the subsequent process of the back side transistor is completed, resulting in the structure shown in fig. 35.
Or based on the structure of fig. 32, on the first semiconductor structure 23, based on the second fin structure 121, a back side transistor is fabricated using standard processes, and the subsequent process of the back side transistor is completed, resulting in the structure shown in fig. 36.
Or based on the structure of fig. 33, on the first semiconductor structure 23, based on the second fin structure 121, a back side transistor is prepared using standard processes, and the subsequent process of the back side transistor is completed, resulting in the structure shown in fig. 37.
A fifth fabrication process is described below, in which a semiconductor structure comprising a layer of semiconductor material is formed at the front-side transistor and the back-side transistor, respectively. Fig. 38 to 43 are schematic structural views of a stacked transistor in a fifth manufacturing process according to an embodiment of the present application, and fig. 44 is a schematic structural view of a stacked transistor in an embodiment of the present application. Here, (a) in fig. 38 to 44 is a cross-sectional view along a tangential direction (i.e., A-A ' direction) of the gate structure, (B) in fig. 38 to 44 is a cross-sectional view along a tangential direction (i.e., B-B ' direction) of the source-drain structure, and (C) in fig. 38 to 44 is a cross-sectional view along a tangential direction (i.e., C-C ' direction) of the fin structure.
In one example, a fifth fabrication process of stacked transistor 10 may include the steps of:
The first step: the substrate 20 is etched to form fin structures 21 and STI 22 in accordance with standard procedures, the STI 22 exposing the first fin structure 111 resulting in the structure shown in fig. 38.
Reference is made here to the first to third steps of the preparation process of the first structure described above.
And a second step of: over the STI 22, a first semiconductor structure 23 is formed, resulting in the structure shown in fig. 39.
Here, the first semiconductor structure 23 includes a layer of semiconductor material, and the semiconductor structure 23 may include a SiN structure, for example.
And a third step of: on the first semiconductor structure 23, a front-side transistor is fabricated using standard processes based on the first fin structure 111, and the subsequent process of the front-side transistor is completed, resulting in the structure shown in fig. 40.
Fourth step: oxide is deposited on the first metal interconnect layer 116 to form the insulating layer 24, the carrier wafer 25 is bonded to the insulating layer 24 and then reworked, followed by removal of the substrate 20 to expose the bottom of the fin structure and STI 22, resulting in the structure shown in fig. 41.
Fifth step: STI 22 is etched to a predetermined height to expose second fin structure 121, resulting in the structure shown in fig. 42.
Sixth step: a second semiconductor structure 26 is formed over the remaining STI 22 resulting in the structure shown in fig. 43.
As shown in fig. 43, it can be seen that the second semiconductor structure 26 includes only one isolation layer.
Seventh step: on the second semiconductor structure 26, a back side transistor is fabricated using standard processes based on the second fin structure 121, and the subsequent processing of the back side transistor is completed, resulting in the structure shown in fig. 44.
For the fifth preparation scheme, the isolation layer (illustratively, siN material) may be formed and then the STI may be formed, so as to form various cases such as an STI-SiN-STI-SiN structure, an SiN-STI-SiN-STI structure, an STI-SiN-STI structure, and the like.
In addition, the embodiment of the application also provides a stacked transistor taking the SOI as the substrate. Fig. 45 is a schematic diagram of a fifth structure of a stacked transistor in an embodiment of the application. The structure shown in fig. 45 is a structure of a stacked transistor obtained by the above-described manufacturing method of the fourth structure, and as shown in fig. 45, in the case where an SOI substrate is used as a substrate, the intermediate BOX layer 27 can be seen as an isolation structure of an active region between a front-side transistor and a back-side transistor.
Additionally, in some embodiments, the first transistor and the second transistor may also be fully-around gate transistors. Fig. 46 is a schematic top view of another stacked transistor according to an embodiment of the present application. For ease of understanding, only the nanoplatelets, gate structures, and source-drain structures are shown in the top view. Wherein the A-A' direction is the tangential direction of the stacked transistor along the gate structure; the B-B' direction is the tangential direction of the stacked transistor along the source-drain structure; the C-C' direction is the tangential direction of the stacked transistor along the nanoplates.
Fig. 47 and 48 are schematic diagrams of a sixth structure of a stacked transistor in an embodiment of the present application. Wherein (a) of fig. 47 to 48 is a tangential plane along a tangential plane direction (i.e., A-A ' direction) of the gate structure, (B) of fig. 47 to 48 is a tangential plane along a tangential plane direction (i.e., B-B ' direction) of the source-drain structure, and (C) of fig. 47 to 48 is a tangential plane along a tangential plane direction (i.e., C-C ' direction) of the nano-sheet.
The structure shown in fig. 47 is, among other things, a first semiconductor structure 23 comprising two layers of semiconductor material formed at the front-side transistor. The structure shown in fig. 48 is a first semiconductor structure 23 comprising four layers of semiconductor material formed at the front side transistor.
In the embodiment of the application, a shallow trench isolation structure is formed on a substrate, and then a first transistor is formed based on the exposed first active structure; and rewinding the first transistor to form a second transistor based on the exposed second active structure; after the first active structure is exposed and/or after the second active structure is exposed, the semiconductor structure is formed to isolate the first transistor from the second transistor. Thus, embodiments of the present application may form semiconductor structures on the front and/or back sides of the stacked transistors, and then form front and/or back side transistors on the semiconductor structures. That is, a semiconductor structure is present between the front side transistor and the back side transistor, which can solve the problem of crosstalk between the upper and lower layer transistors in the stacked transistor. Therefore, the embodiment of the application optimizes the process scheme of the flip-chip stacked transistor, solves the problem that the STI loss of the source-drain region possibly leads to the crosstalk of transistors on the upper layer and the lower layer, and provides a process scheme with better STI isolation regulation. And comprehensively considers the influences of various process viable schemes and possible structures, parasitic capacitance and other device characteristics.
Further, the stacked transistor provided by the embodiment of the application can be detected by using a detection analysis instrument, for example: scanning electron microscope (scanning electron microscope, SEM), transmission electron microscope (transmission electron microscope, TEM), scanning transmission electron microscope (scanning transmission electron microscopy, STEM), and the like. Taking TEM as an example, the embodiment of the present application may detect the structure of the stacked transistor by using a TEM section.
An embodiment of the present application provides a semiconductor device including: stacked transistors as in the above embodiments. For specific limitation of the stacked transistor, reference may be made to the above stacked transistor, and detailed description thereof is omitted herein.
An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device includes the above-described stacked transistor. For specific limitation of the stacked transistor, reference may be made to the above stacked transistor, and detailed description thereof is omitted herein.
In the description of the embodiments of the present application, the descriptions of the terms "one embodiment," "an example," "a particular example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (11)

1. A method of fabricating a stacked transistor, comprising:
Forming an active structure on a substrate, the active structure comprising a first active structure and a second active structure, the first active structure being remote from the substrate relative to the second active structure;
forming a shallow trench isolation structure on the substrate and exposing the first active structure;
forming a first transistor based on the first active structure;
rewinding the first transistor and exposing the second active structure;
Forming a second transistor based on the second active structure;
wherein after exposing the first active structure and/or after exposing the second active structure, a semiconductor structure is formed, the semiconductor structure being used to isolate the first transistor from the second transistor.
2. The method of claim 1, wherein forming a semiconductor structure after exposing the first active structure comprises:
depositing a semiconductor material on the shallow trench isolation structure to form the semiconductor structure;
the forming a first transistor based on the first active structure includes:
the first transistor is formed on the semiconductor structure based on the first active structure.
3. The method of claim 1, wherein the exposing the second active structure comprises:
Removing the substrate;
And thinning the shallow trench isolation structure to a preset height so as to expose the second active structure.
4. The method of claim 3, wherein forming a semiconductor structure after exposing the second active structure comprises:
depositing a semiconductor material on the reserved shallow trench isolation structure to form the semiconductor structure;
the forming a second transistor based on the second active structure includes:
The second transistor is formed on the semiconductor structure based on the second active structure.
5. The method of claim 1, wherein the semiconductor structure comprises a first semiconductor material, or the semiconductor structure comprises at least a first semiconductor material and a second semiconductor material alternately stacked in sequence along an arrangement direction of the active structure.
6. The method of claim 1, wherein forming a first transistor based on the first active structure comprises:
Epitaxially growing a first source-drain structure on the first active structure;
forming a first gate structure based on the first active structure;
forming a first source drain metal on the first source drain structure;
the forming a second transistor based on the second active structure includes:
epitaxially growing a second source-drain structure on the second active structure;
Forming a second gate structure based on the second active structure;
and forming a second source-drain metal on the second source-drain structure.
7. The method of claim 1, wherein the first transistor is one of a fin field effect transistor, a fully-surrounding gate transistor, and a planar transistor, and the second transistor is one of a fin field effect transistor, a fully-surrounding gate transistor, and a planar transistor.
8. A stacked transistor manufactured using the manufacturing method according to any one of claims 1 to 7, comprising:
A first transistor;
a second transistor, the first transistor and the second transistor being arranged in opposition;
and the semiconductor structure is used for isolating the first transistor from the second transistor.
9. The stacked transistor of claim 8, wherein the first transistor is one of a fin field effect transistor, a fully-surrounding gate transistor, and a planar transistor, and the second transistor is one of a fin field effect transistor, a fully-surrounding gate transistor, and a planar transistor.
10. A semiconductor device, comprising: a stacked transistor as claimed in claim 8 or 9.
11. An electronic device, comprising: a circuit board and the semiconductor device according to claim 10, wherein the semiconductor device is provided on the circuit board.
CN202410443039.4A 2024-04-12 2024-04-12 Preparation method of stacked transistor, device and equipment Pending CN118248633A (en)

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