CN118538670A

CN118538670A - Preparation method of stacked fork plate transistor, stacked fork plate transistor and device

Info

Publication number: CN118538670A
Application number: CN202410778408.5A
Authority: CN
Inventors: 吴恒; 刘煜; 孙嘉诚; 王润声; 黎明; 黄如
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2024-06-17
Filing date: 2024-06-17
Publication date: 2024-08-23

Abstract

The application provides a preparation method of a stacked fork plate transistor, the stacked fork plate transistor and a device, wherein the method comprises the following steps: forming a pair of active structures on a substrate, wherein a space exists between the pair of active structures, and the pair of active structures comprises a pair of first active structures and a pair of second active structures; sequentially forming an isolation layer and a dielectric structure in the interval of the pair of active structures, wherein the isolation layer wraps the dielectric structure; forming a front-side transistor based on the pair of first active structures; removing the isolation layer located in the space between the pair of first active structures to form a first groove; forming a front grid structure of the front transistor in a grid region of the front transistor, wherein a metal material exists in the first groove; rewinding and removing the substrate to expose a pair of second active structures; the back gate structure of the back-side transistor is formed based on the same method of forming the front-side gate structure of the front-side transistor. The front and back transistors in the application are four-gate devices, which can enhance the gate control function.

Description

Preparation method of stacked fork plate transistor, stacked fork plate transistor and device

Technical Field

The present application relates to the field of semiconductors, and in particular, to a method for manufacturing a stacked fork transistor, and a device.

Background

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. The stacked transistor stacked transistor further improves the transistor integration density by integrating two or more layers of transistors in a vertical space, which is one of the important technologies for continuing the miniaturization of integrated circuit dimensions.

In the related art, the stacked fork plate transistor is prepared by placing transistors in pairs on two sides of a dielectric structure, but one side of a gate structure of the transistor is connected with the dielectric structure, so that the gate control function of the stacked fork plate transistor is reduced.

Disclosure of Invention

The application provides a preparation method of a stacked fork plate transistor, the stacked fork plate transistor and a device, so as to enhance the gate control function of the stacked fork plate transistor.

In a first aspect, an embodiment of the present application provides a method for manufacturing a stacked fork plate transistor, the method including: forming a pair of active structures on the substrate, wherein a gap exists between the pair of active structures, the pair of active structures comprises a pair of first active structures and a pair of second active structures, the first active structures are far away from the substrate than the second active structures, and the active structures are nano-sheet structures; sequentially forming an isolation layer and a dielectric structure in the interval of the pair of active structures, wherein the isolation layer wraps the dielectric structure; forming a front-side transistor based on the pair of first active structures, wherein the front-side transistor comprises a front-side source-drain structure and a front-side interlayer dielectric layer; removing the isolation layer located in the space between the pair of first active structures to form a first groove; forming a front-side gate structure of the front-side transistor in a gate region of the front-side transistor, wherein a metal material exists in the first groove; rewinding and removing the substrate to expose a pair of second active structures; forming a back transistor based on the pair of second active structures, wherein the back transistor comprises a back source-drain structure and a back interlayer dielectric layer; removing the isolation layer located in the space between the pair of second active structures to form a second groove; and forming a back gate structure of the back transistor in the gate region of the back transistor, wherein a metal material exists in the second groove.

In some possible embodiments, after sequentially forming the isolation layer and the dielectric structure in the space between the pair of active structures, the method further comprises: etching the isolation layer and the dielectric structure located in the space between the pair of first active structures; forming a shallow trench isolation structure on the substrate to cover the pair of second active structures and the isolation layer and the dielectric structure located in the space of the pair of second active structures and expose the pair of first active structures and the isolation layer and the dielectric structure located in the space of the pair of first active structures; sequentially forming an isolation layer and a dielectric structure positioned in the interval of a pair of first active structures on the shallow trench isolation structure; forming a front-side transistor based on a pair of first active structures, comprising: on the shallow trench isolation structure, a front-side transistor is formed based on a pair of first active structures.

In some possible embodiments, after sequentially forming the isolation layer and the dielectric structure in the space between the pair of active structures, the method further comprises: forming a shallow trench isolation structure on the substrate to cover the pair of second active structures and the isolation layer and the dielectric structure located in the space of the pair of second active structures and expose the pair of first active structures and the isolation layer and the dielectric structure located in the space of the pair of first active structures; forming a front-side transistor based on a pair of first active structures, comprising: on the shallow trench isolation structure, a front-side transistor is formed based on a pair of first active structures.

In some possible embodiments, rewinding and removing the substrate to expose a pair of second active structures, comprising: rewinding and removing the substrate; the shallow trench isolation structure is thinned to a predetermined height to expose the pair of second active structures and the isolation layer and the dielectric structure located in the space between the pair of second active structures.

In some possible embodiments, forming the isolation layer and the dielectric structure sequentially in the space between the pair of active structures comprises: forming a shallow trench isolation structure on the substrate to cover the pair of second active structures and expose the pair of first active structures; sequentially forming an isolation layer and a dielectric structure positioned in the interval of a pair of first active structures on the shallow trench isolation structure; rewinding and removing the substrate to expose a pair of second active structures, comprising: rewinding and removing the substrate; thinning the shallow trench isolation structure to a preset height to expose a pair of second active structures; after rewinding and removing the substrate to expose the pair of second active structures, the method further comprises: an isolation layer and a dielectric structure are sequentially formed in the space between the pair of second active structures.

In some possible embodiments, forming a pair of active structures on a substrate includes: providing a substrate, wherein the substrate comprises a top stacking layer, an intermediate sacrificial layer and a bottom stacking layer which are sequentially stacked; depositing semiconductor material on a first region of the top stack layer to form a pair of oppositely disposed sidewall structures with a space therebetween; and etching the substrate by taking the side wall structure as a mask to form a pair of active structures.

In some possible embodiments, before forming the front-side transistor based on the pair of first active structures, the method further comprises: removing the intermediate sacrificial layer to form a third groove; an insulating material is deposited in the third recess to form an intermediate isolation layer, the intermediate isolation layer being used to isolate the first active structure from the second active structure.

In some possible embodiments, after forming the front-side gate structure of the front-side transistor in the gate region of the front-side transistor, the method further comprises; performing a back-end process on top of the front-side gate structure to form a front-side metal interconnect layer of the front-side transistor; after forming the back gate structure of the back side transistor in the gate region of the back side transistor, the method further comprises: a back-end process is performed over the back-gate structure to form a back-metal interconnect layer of the back-side transistor.

In a second aspect, an embodiment of the present application provides a stacked fork plate transistor, which is manufactured by using the manufacturing method as described in the first aspect and any one of the embodiments thereof, including: a front side transistor; a back side transistor, the front side transistor being self-aligned with the back side transistor; the dielectric structure penetrates through the first active structure of the front transistor and the second active structure of the back transistor, the dielectric structure divides the first active structure into two parts which are symmetrically arranged, the second active structure is divided into two parts which are symmetrically arranged, the peripheral side of the dielectric structure at the front transistor is a front grid structure of the front transistor, the peripheral side of the dielectric structure at the back transistor is a back grid structure of the back transistor, and the first active structure and the second active structure are nano-sheet structures.

In a third aspect, an embodiment of the present application provides a semiconductor device including: a stacked fork plate transistor as in the second aspect above.

In a fourth aspect, an embodiment of the present application provides an electronic device, including: a circuit board and the semiconductor device according to the third aspect, the semiconductor device being provided to the circuit board.

According to the application, the isolation layer and the dielectric structure are sequentially arranged in the interval of the pair of active structures, the isolation layer wraps the dielectric structure, then the isolation layer positioned in the middle of the active structures is removed to form the groove before the grid structure is formed, so that metal materials are filled in the groove in the process of forming the grid structure in the grid region of the transistor, and the front grid structure of the front transistor and the back grid structure of the back transistor which are finally formed are four-grid devices, so that the control capability of the grid structure on a channel can be enhanced, and the short channel effect is weakened.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic flow chart of a method for manufacturing a stacked fork-plate transistor according to an embodiment of the present application;

FIG. 2 is a schematic top view of a stacked fork plate transistor according to an embodiment of the present application;

fig. 3A to 3H are schematic structural diagrams of stacked fork-plate transistors in a first manufacturing process according to an embodiment of the present application;

FIG. 3I is a schematic diagram of a first structure of a stacked fork plate transistor according to an embodiment of the present application;

fig. 4A to 4E are schematic structural diagrams of stacked fork plate transistors according to an embodiment of the present application in a second manufacturing process;

fig. 4F is a schematic diagram of a second structure of a stacked fork transistor according to an embodiment of the present application;

fig. 5A to 5E are schematic structural diagrams of stacked fork plate transistors according to an embodiment of the present application in a third manufacturing process;

fig. 5F is a schematic diagram of a third structure of a stacked fork transistor according to an embodiment of the present application.

The figures above:

10. Stacking fork plate transistors; 11. a front side transistor; 111. a first nanoplatelet structure; 112. a front source drain structure; 113. a front interlayer dielectric layer; 114. a front gate structure; 1141. a front gate dielectric layer; 1142. a front gate electrode layer; 115. front source drain metal; 116. a front side metal interconnect layer; 12. a back side transistor; 121. a second nanoplatelet structure; 122. a back source drain structure; 123. a back interlayer dielectric layer; 124. a back gate structure; 1241. a back gate dielectric layer; 1242. a back gate electrode layer; 125. back source drain metal; 126. a backside metal interconnect layer; 13. an insulating layer; 14. a carrier wafer; 20. a substrate; 201. a top stack layer; 202. an intermediate sacrificial layer; 203. a bottom stack layer; 21. a side wall structure; 22. an active structure; 221. a first active structure; 222. a second active structure; 23. a first intermediate sacrificial layer; 24. shallow trench isolation structures; 25. an isolation layer at the front side transistor; 26. a dielectric structure at the front side transistor; 27. a front dummy gate structure; 28. a third groove; 29. an intermediate isolation layer; 30. a front spacer; 31. a first groove; 32. a first isolation structure; 33. an isolation layer at the back side transistor; 34. a dielectric structure at the back side transistor; 35. a second groove; 36. a second isolation structure; 37. an isolation layer at the front side transistor and the back side transistor; 38. dielectric structures at the front side and back side transistors.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.

While moore's law is continually deepening, continuing to advance transistor scaling after fully surrounding the technology node of gate-all-around FIELD EFFECT transistors (GAAFET) is a hot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits.

In one embodiment, the fabrication process of the stacked transistor has two schemes, the first is a monolithic stacking scheme and the second is a sequential scheme.

In the first approach, N-channel field effect transistors (N FIELD EFFECT transistors, NFETs) and P-channel field effect transistors (P FIELD EFFECT transistors, PFETs) are fabricated on the same substrate, and wafer bonding techniques are not used. This determines that the same layer transistors must be of the same type, i.e., NFET or PFET. And the transistors on the upper layer and the lower layer are strictly in the same plane space, and no alignment deviation exists. The advantage of this solution is a better integration density. Drawbacks of this approach include the following two points: (1) The process is complex, and a large number of process technologies need to be developed and optimized; (2) Each layer of transistors has a fixed polarity, and two layers of transistors must be relied upon to form a basic Complementary Metal Oxide Semiconductor (CMOS) circuit, which has poor design flexibility.

The second scheme is based on wafer bonding and layer-by-layer processing. Specifically, the two transistors are stacked vertically by bonding a wafer on top of the fabricated lower transistor to prepare the upper transistor. However, this approach requires tight temperature control during the thermal process of processing the upper layer transistors, avoiding affecting the lower layer transistors and the interconnect lines. The scheme has the advantages that the device structure, the channel crystal orientation and even the channel material adopted by the upper layer transistor and the lower layer transistor can be correspondingly optimized to obtain better and more matched device performance due to wafer bonding. This solution currently presents the following technical challenges: (1) preparation of a high-quality upper transistor active layer; (2) thinning and defect control of the upper bonded wafer; (3) The upper and lower layer transistors have alignment errors and have extremely high requirements on photoetching precision.

Among them, between two types of transistors, N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS), which constitute Complementary Metal Oxide Semiconductor (CMOS) logic, a certain separation distance must be maintained to limit capacitance that impairs device performance and affects power consumption, reducing interference between adjacent transistors. This spacing limits the scaling of logic based on nanoplatelet structures. Fork plate transistors (forksheet) are one way to break this limitation, forksheet is constructed by placing transistors in pairs on either side of dielectric walls (also called dielectric structures) that allow devices to be placed closely without capacitance problems, and that allow logic cells to be scaled down with additional space, and that allow wider transistors to be fabricated using existing space to achieve better performance.

However, the transistors are arranged in pairs on two sides of the dielectric structure, one side of the gate of each transistor is connected with the dielectric structure, namely a tri-gate device is formed, and the side connected with the dielectric structure cannot play a role in gate control, so that the gate control effect of the stacked fork plate transistor is reduced, and a short channel effect is generated.

In order to solve the technical problems, the embodiment of the application provides a preparation method of a stacked fork plate transistor, which can enhance the gate control function of the stacked fork plate transistor and weaken the short channel effect.

In the embodiment of the application, the stacked fork plate transistor can be applied to semiconductor devices such as memories, processors and the like.

In some embodiments, the stacked fork plate transistor may include a front side transistor, a back side transistor, and a dielectric structure extending through a first active structure of the front side transistor, dividing the first active structure of the front side transistor into two symmetrically disposed portions, i.e., forming a pair of first active structures; similarly, the dielectric structure penetrates through the second active structure of the back side transistor, and the second active structure of the back side transistor is divided into two parts which are symmetrically arranged, namely a pair of second active structures is formed.

It will be appreciated that, since the dielectric structure penetrates the first active structure of the front-side transistor, which corresponds to the active region penetrating the front-side transistor, the active region of the front-side transistor is divided into two parts symmetrically disposed on both sides of the dielectric structure, and the front-side transistor can be divided into two symmetrical transistors, such as the first front-side transistor and the second front-side transistor, due to the separation of the active regions. Accordingly, the back side transistor may also be divided into two symmetrical transistors, such as a first back side transistor and a second back side transistor.

In the embodiment of the application, the active region is a combination of a source region, a drain region and a channel region.

In some embodiments, the perimeter side of the dielectric structure at the front side transistor is the front side gate structure of the front side transistor and the perimeter side of the dielectric structure at the back side transistor is the back side gate structure of the back side transistor. The front gate structure and the back gate structure thus formed are four gate devices.

In embodiments of the present application, the front side and back side transistors are of a "back-to-back" design and are self-aligned. Wherein the first front side transistor corresponds to a first back side transistor, the first front side transistor and the first back side transistor being self-aligned; accordingly, the second front side transistor corresponds to a second back side transistor, the second front side transistor and the second back side transistor being self-aligned.

In the embodiment of the application, the polar types of the first front-side transistor and the second front-side transistor are the same (n-type or p-type), and the polar types of the first back-side transistor and the second back-side transistor are the same (n-type or p-type), so that the step of depositing work function metal (namely a grid structure) can be simplified, and the threshold voltage can be regulated and controlled.

In an embodiment of the present application, the first active structure and the second active structure are nano-sheet (nanosheet) structures, and the stacked fork-plate transistor so formed is GAAFET. In addition, the front side transistor and the back side transistor in the stacked fork plate transistor may be the same type of transistor, and as fork plate transistors, the first front side transistor and the second front side transistor in the front side transistor may be the same type of transistor (such as NFET or PFET) or may be different types of transistors (such as NFET and PFET), and if the transistors of different types require more complex process steps; accordingly, the first back side transistor and the second back side transistor in the back side transistors may be the same type of transistor or may be different types of transistors; the embodiment of the application does not particularly limit the types of the plurality of transistors in the fork plate transistor in the front surface area or the back surface area.

Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing a stacked fork transistor according to an embodiment of the present application, and as shown in fig. 1, the method for manufacturing a stacked fork transistor according to an embodiment of the present application may include:

step S110: a pair of active structures is formed on a substrate.

The active structures comprise a pair of first active structures and a pair of second active structures, the first active structures are far away from the substrate than the second active structures, and the active structures are nano-sheet structures.

It will be appreciated that when the active structure is a nano-plate structure, the stacked fork plate transistor in the embodiments of the present application includes GAAFET.

By etching the substrate, a first active structure of the front side transistor and a second active structure of the back side transistor may be formed.

In some embodiments, the implementation process of step S110 may be divided into the following three steps: step S111: providing a substrate, wherein the substrate comprises a top stacking layer, an intermediate sacrificial layer and a bottom stacking layer which are sequentially stacked; step S112: depositing semiconductor material on a first region of the top stack layer to form a pair of oppositely disposed sidewall structures with a space therebetween; step S113: and etching the substrate by taking the side wall structure as a mask to form a pair of active structures.

It is understood that in step S111, the preparation process of the substrate may include: a sacrificial layer of material is epitaxially deposited on the original substrate (i.e., the bottom stack layer) to form an intermediate sacrificial layer, and then the same semiconductor material as the bottom stack layer is epitaxially deposited over the intermediate sacrificial layer to form a top stack layer. The substrate formed by the preparation method comprises a top stacking layer, an intermediate sacrificial layer and a bottom stacking layer which are stacked in sequence. Wherein the top stack is used to fabricate the front side transistor and the bottom stack is used to fabricate the back side transistor.

In some embodiments, the material of the intermediate sacrificial layer may be a silicon germanium (SiGe) material, or may be another semiconductor material, which is not particularly limited in this embodiment of the present application.

In some embodiments, the top and bottom stacked layers are each of a stacked structure (i.e., stacked layers formed by alternating deposition of silicon and silicon germanium) in which the germanium content of the silicon germanium material used in the top and bottom stacked layers is different from the germanium content of the silicon germanium material used in the intermediate sacrificial layer (i.e., siGe 1 is used to make the top and bottom stacked layers and SiGe2 is used to make the intermediate sacrificial layer). Thus, the selective etching of the middle sacrificial layer can be completed in the subsequent preparation process.

In some embodiments, the thickness of the silicon layer located at the lowermost of the bottom stack may be greater than the thickness of the other silicon layers in the stack, and the substrate is formed by sequentially depositing material layers of different materials based on the lowermost silicon layer of the bottom stack.

In some embodiments, the height of the top stack layer may be designed according to practical requirements, such as 50 nanometers (nm), the height of the bottom stack layer is greater than the top stack layer, and the height of the middle sacrificial layer is less than the height of the top stack layer.

In some embodiments, after forming the substrate, a semiconductor material may be deposited on the first region of the top stack layer to form a pair of oppositely disposed sidewall structures in step S112. Wherein the first region is located on a surface of the top stack layer remote from the bottom stack layer and is disposed on both sides of the top stack layer such that there is a space between a pair of sidewall structures formed on the first region.

It will be appreciated that after the substrate preparation is completed, the top stack layer is placed upwards, and sidewall materials may be deposited on two sides of the upper surface of the top stack layer, so as to form two sidewall structures that are disposed oppositely, namely a first sidewall structure and a second sidewall structure, and the first sidewall structure and the second sidewall structure are disposed symmetrically on two sides of the central axis of the substrate.

In the embodiment of the present application, the deposited sidewall material may be a hard mask material, such as any one of the following: silicon nitride (SiN), silicon dioxide (SiO ₂), titanium nitride (TiN), and the like.

In some embodiments, after forming a pair of sidewall structures, the substrate is etched to form a pair of active structures using the sidewall structures as a mask in step S113. The etching process may be at least one of dry etching, wet etching, reactive ion etching, and the like, for example.

It will be appreciated that the top stack layer, the intermediate sacrificial layer and the bottom stack layer are etched sequentially with the pair of sidewall structures as masks, with the etch stopping to the lowermost silicon layer of the bottom stack layer, to form a pair of first active structures, a pair of intermediate sacrificial layers and a pair of second active structures disposed in opposition. The etched bottom stacked layer is used as a pair of second active structures, the etched middle sacrificial layer is used as a pair of middle sacrificial layers, and the etched top stacked layer is used as a pair of first active structures.

In some embodiments, after forming a pair of active structures, the mask may be removed, i.e., a pair of sidewall structures may be removed, for subsequent fabrication of a stacked fork plate transistor based on the exposed pair of active structures.

Step S120: an isolation layer and a dielectric structure are sequentially formed in the space between a pair of active structures. Wherein the isolation layer encapsulates the dielectric structure.

In step S110, a pair of active structures are disposed opposite to each other with a space therebetween, and thus an isolation layer and a dielectric structure may be sequentially formed in the space therebetween.

In some embodiments, the implementation procedure of step S120 may be: forming a shallow trench isolation structure on the substrate to cover the pair of second active structures and expose the pair of first active structures; an isolation layer and a dielectric structure are sequentially formed on the shallow trench isolation structure in the space between the pair of first active structures.

It is appreciated that an oxide material is deposited over the second portion of the substrate and the surfaces of the pair of active structures and a planarization process is employed to remove the top surfaces of the oxide material until the top surfaces of the pair of active structures are exposed, thereby forming shallow trench isolation structures having top surfaces that are level with the top surfaces of the pair of active structures. And then, etching the shallow trench isolation structure back to a certain depth, so that the shallow trench isolation structure wraps the pair of second active structures and exposes the pair of first active structures. This is so that a front-side transistor is subsequently formed based on the exposed pair of first active structures. Wherein the second region of the substrate is a region not covered by the pair of active structures.

In an example, the oxide material forming the shallow trench isolation structure may be, for example, any of the following: silicon nitride (SiN, si3N 4), silicon dioxide (SiO 2), silicon oxycarbide (SiCO), or the like. The planarization process may be, for example, a chemical-mechanical planarization (CMP) process or the like.

In some embodiments, after forming the shallow trench isolation structure, an isolation layer and a dielectric structure located in the space of the pair of first active structures may be formed on the shallow trench isolation structure.

In some embodiments, the forming of the isolation layer and the dielectric structure located in the space between the pair of first active structures on the shallow trench isolation structure may be performed by: depositing isolation material on the shallow trench isolation structure and the pair of first active structures to form an isolation layer, depositing dielectric material on the isolation layer to form a dielectric structure, and etching the isolation layer and the dielectric structure located on both sides of the pair of first active structures, wherein the isolation layer and the dielectric structure after etching are located in the interval of the pair of first active structures. Among them, the isolation material used for forming the isolation layer may be, for example, a material such as silicon dioxide. The dielectric material used to form the dielectric structure may be, for example, alumina, zirconia, etc., and embodiments of the present application are not limited thereto.

In the embodiment of the application, the method is to form the isolation layer and the dielectric structure at the front side transistor first, and then form the isolation layer and the dielectric structure at the back side transistor.

In some embodiments, the spacers and dielectric structures at the front side and back side transistors may also be one-shot.

In some embodiments, the implementation procedure of step S120 may be: depositing an isolation material over the second region of the stack layer and the pair of active structures to form an isolation layer, depositing a dielectric material over the isolation layer to form a dielectric structure, and then etching the isolation layer and the dielectric structure on both sides of the pair of active structures such that the etched isolation layer and dielectric structure are located in the space between the pair of active structures. Thus, the isolation layer and dielectric structure at the front side and back side transistors are formed in one piece.

In some embodiments, after forming the isolation layer and the dielectric structure at the front side transistor and the back side transistor, a shallow trench isolation structure may also be formed on the stacked layer to cover the pair of second active structures and the isolation layer and the dielectric structure in the space to the second active structures and expose the pair of first active structures and the isolation layer and the dielectric structure in the space to the pair of first active structures. A front side transistor may be fabricated on the shallow trench isolation structure thereafter based on the exposed pair of first active structures.

In other embodiments, after forming the isolation layer and the dielectric structure at the front side transistor and the back side transistor, the isolation layer and the dielectric structure in the space of the pair of first active structures may also be etched; forming a shallow trench isolation structure on the substrate to cover the pair of second active structures and the isolation layer and the dielectric structure located in the space of the pair of second active structures and expose the pair of first active structures and the isolation layer and the dielectric structure located in the space of the pair of first active structures; an isolation layer and a dielectric structure are sequentially formed on the shallow trench isolation structure in the space between the pair of first active structures.

It will be appreciated that after forming the isolation layer and dielectric structure at the front side transistor and the back side transistor, the isolation layer and dielectric structure at the back side transistor may be etched first, and then shallow trench isolation structures are formed on the substrate such that the shallow trench isolation structures cover the isolation layer and dielectric structure at the back side transistor. And then depositing isolation materials on the shallow trench isolation structure and the pair of first active structures to form isolation layers, depositing dielectric materials on the isolation layers to form dielectric structures, and etching the isolation layers and the dielectric structures which are positioned on two sides of the pair of first active structures so as to form the isolation layers and the dielectric structures which are positioned in the interval of the pair of first active structures. In this method, shallow trench isolation structures isolate isolation layers at the front-side and back-side transistors from dielectric structures.

It should be noted that, in the above three ways of forming the isolation layer and the dielectric structure, the shallow trench isolation structure covers the second active structure of the back transistor, and exposes the first active structure of the front transistor and the intermediate sacrificial layer between the first active structure and the second active structure, so that the intermediate sacrificial layer is removed subsequently to form the intermediate isolation layer between the first active structure and the second active structure.

Step S130: a front side transistor is formed based on a pair of first active structures.

The front-side transistor comprises a front-side source-drain structure and a front-side interlayer dielectric layer.

In some embodiments, the implementation procedure of step S130 may be: epitaxially growing a pair of front-side source-drain structures on the pair of first active structures; an interlayer dielectric is deposited over the pair of front side source drain structures to form a pair of front side interlayer dielectric layers.

It should be noted that, since the stacked fork plate transistors are disposed in pairs on two sides of the dielectric structure, the front side transistor includes two transistors in pairs, which may be a first front side transistor and a second front side transistor, and the pair of front side source drain structures includes a first front side source drain structure and a second front side source drain structure disposed in pairs, and the pair of front side interlayer dielectric layers includes a first front side interlayer dielectric layer and a second front side interlayer dielectric layer disposed in pairs.

It will be appreciated that a semiconductor structure may be deposited over the shallow trench isolation structure within the gate region of the front side transistor to form a front side dummy gate structure of the front side transistor; forming front spacers (spacers) on both sides of the dummy gate structure of the front transistor; and forming a front source drain structure on the front dummy gate structure and the first active structure on two sides of the front gap wall. In one embodiment, the front spacer is used to isolate the front source drain structure from the front gate structure. Illustratively, the front side spacers may have a single layer structure, entirely made of the same material, such as porous carbosiloxy (SiCOH). Of course, the structure of the front spacer may be set according to practical requirements, which is not particularly limited in the embodiment of the present application.

In some embodiments, the semiconductor material forming the dummy gate structure of the front-side transistor may be polysilicon, amorphous silicon, or the like. In some embodiments, the implementation process of forming the front source drain structure on the first active structure on both sides of the front dummy gate structure and the front spacer may be: and etching the first active structure of the front-side transistor in the source-drain region to form a front-side source-drain groove, and performing source-drain epitaxial growth at the front-side source-drain groove to form a front-side source-drain structure.

For example, a strained material such as silicon germanium or silicon carbide may be formed in the source-drain recess by selective epitaxial growth to fill the source-drain recess of the front-side transistor, and then a front-side source-drain structure may be formed on the strained material by a heavy doping process.

In some possible embodiments, after forming the front-side dummy gate structure, the intermediate sacrificial layer may also be removed to form a third recess; an insulating material is deposited in the third recess to form an intermediate isolation layer. The intermediate isolation layer is used for isolating the first active structure and the second active structure.

It will be appreciated that the intermediate sacrificial layer is removed after the formation of the front side dummy gate structure, so that the front side dummy gate structure can support the first active structure to prevent the first active structure from collapsing during the removal of the intermediate sacrificial layer. And removing the intermediate sacrificial layer to form a third groove positioned between the first active structure and the second active structure, and filling an insulating material in the third groove to form an intermediate isolation layer.

The middle isolation layer and the front spacer may be made of the same insulating material, and further, the middle isolation layer and the front spacer may be formed in the same process.

In some embodiments, after forming the front-side source-drain structure, an interlayer dielectric may be deposited on the front-side source-drain structure and thinned to an upper surface of the front-side source-drain structure to form a front-side interlayer dielectric layer.

For example, an insulating material (such as silicon dioxide SiO 2) may be deposited over the front-side source-drain structure and the first active structure, and planarized to form a front-side interlayer dielectric layer, where the front-side interlayer dielectric layer covers the front-side source-drain structure and the first active structure.

In some embodiments, after the structure of the source-drain portion of the front-side transistor is completed, the gate structure of the front-side transistor is next prepared.

In some embodiments, the front side dummy gate structure formed by the foregoing steps may be removed first to expose the gate region of the front side transistor for subsequent formation of the front side gate structure.

Step S140: the isolation layer located in the space between the pair of first active structures is removed to form a first groove.

Wherein, there is metal material in the first recess.

It will be appreciated that after the front side dummy gate structure is removed, the silicon germanium layer in the stack structure of the top stack layer may also be selectively etched, and then the isolation layer located in the space between the pair of first active structures is removed to expose the gate region of the front side transistor adjacent to the dielectric structure. Since the isolation layer wraps the dielectric structure, after the isolation layer is removed, a first recess is formed in the space between the pair of first active structures.

When the isolation layer is removed, the etching rate needs to be strictly controlled so as to stop at the intermediate sacrificial layer separating the front and back transistors, in the case where the isolation layers and the dielectric structures of the front and back transistors are formed at one time and the isolation of the shallow trench isolation structure does not exist in the middle.

It should be noted that, since the front-side source-drain structure formed as described above covers the isolation layer at the source-drain region, the isolation layer at the source-drain region is maintained. In addition, the isolation layer at the source-drain region is also used as a support of the dielectric structure, so that the dielectric structure is prevented from collapsing in the process of removing the isolation layer.

Step S150: in the gate region of the front-side transistor, a front-side gate structure of the front-side transistor is formed. In some embodiments, after removing the spacer, a front-side gate structure may be formed in the gate region of the front-side transistor. The front grid structure comprises a first front grid structure and a second front grid structure which are oppositely arranged.

It will be appreciated that an insulating material may be deposited on the surface of the first active structure in the gate region of the front side transistor to form a front side gate dielectric layer, and a metal material may be deposited on the front side gate dielectric layer to form a front side gate electrode layer. The front gate dielectric layer and the front gate electrode layer form a front gate structure.

It should be noted that, in the process of forming the front gate structure, the first groove is also located in the gate region, so that a metal material is also present in the first groove, and the front gate structure formed in this way surrounds the periphery of the first active structure, that is, the front gate structure formed is a four-gate device, so that the gate control effect can be enhanced.

By way of example, the front side gate dielectric layer may be comprised of a hafnium oxide layer with a silicon oxide layer having a high K (high-K) value, and the thickness of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

By way of example, the front side gate electrode layer may be composed of multiple layers of electrode materials, each layer of electrode material including, but not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

In addition, during the depositing of the metal material, an isolation material may be deposited at a first portion of the gate region to form a first isolation structure, the first portion corresponding to the dielectric structure; and depositing a metal material in the rest area except the first part of the grid electrode area to form a first front grid electrode structure and a second front grid electrode structure, wherein the first front grid electrode structure and the second front grid electrode structure are symmetrically arranged on two sides of the first isolation structure.

It should be noted that the first isolation structure is located on the surface of the dielectric structure between the pair of first active structures, and the height of the first isolation structure in the horizontal direction is identical to the height of the front gate structure. The first front gate structure of the first front transistor and the second front gate structure of the second front transistor form the front gate structure, and the first isolation structure is used for isolating the first front gate structure and the second front gate structure.

In addition, in some embodiments, after forming the front-side gate structure, front-side source-drain metal of the front-side transistor may be formed, wherein the front-side source-drain metal includes a first front-side source-drain metal and a second front-side source-drain metal.

It will be appreciated that a portion of the front side interlayer dielectric layer of the source drain region may be etched to expose the front side source drain structure, followed by deposition of a metal material on the front side source drain structure to form a front side source drain metal.

It should be noted that, the front-side source-drain structure represents a source and/or a drain in the front-side transistor, and correspondingly, other expressions related to "source-drain" in the embodiments of the present application are used to represent "source and/or drain", for example: front source drain metal, back source drain structure, back source drain metal, etc.

In some embodiments, after forming the front-side source-drain structure, the front-side gate structure, and the front-side source-drain metal, a subsequent process may be performed over the front-side source-drain metal to form a front-side metal interconnect layer of the front-side transistor.

It will be appreciated that subsequent processes (e.g., dielectric deposition between interconnect lines, metal line formation, lead-out pad formation, etc.) may be performed on the front side source drain metal to form a front side metal interconnect layer.

Step S160: the substrate is rewound and removed to expose a pair of second active structures.

In some embodiments, the implementation procedure of step S160 may be: wafer bonding and rewinding are carried out on the front-side transistor, and the substrate is removed; the shallow trench isolation structure is thinned to a preset height so as to expose a pair of second active structures. The thinned shallow trench isolation structure is used for isolating the front-side transistor and the back-side transistor.

It will be appreciated that after the front side transistor is formed, the front side transistor may be bonded to a carrier wafer and then flipped so that the bottom stack layer is placed up. And then removing the lowest silicon layer (namely the first silicon layer placed upwards) of the bottom stacked layer, and thinning the shallow trench isolation structure to expose a pair of second active structures, so that the subsequent preparation of the back transistor based on the pair of second active structures is facilitated.

In one embodiment, an insulating material (e.g., silicon oxide) may be deposited over the front side metal interconnect layer to form a first insulating layer and bond the insulating layer to the carrier wafer.

In one embodiment, the first silicon layer of the bottom stack layer may be removed after rewinding using a polishing process or a chemical mechanical planarization process.

After the first silicon layer of the bottom stacked layer is removed, the top layers of the pair of second active structures are flush with the top layers of the shallow trench isolation structures, so that the shallow trench isolation structures can be thinned to a preset height, and the peripheral sides of the pair of second active structures are exposed so as to form a back transistor according to the exposed pair of second active structures.

The preset height can be set according to actual requirements, which is not limited in the embodiment of the present application.

In the case of forming the isolation layer and the dielectric structure at the front-side transistor before forming the isolation layer and the dielectric structure at the back-side transistor (the isolation layer and the dielectric structure at the front-side transistor are formed twice), the isolation layer and the dielectric structure do not exist at the back side at this time, so that after the shallow trench isolation structure is thinned, the exposed structure is a pair of second active structures.

In the case where the isolation layer and the dielectric structure at the front side transistor and the back side transistor are formed at one time, the isolation layer and the dielectric structure in the space of the pair of second active structures located at the back side are formed in the foregoing steps, and thus after the shallow trench isolation structure is thinned, the exposed structure is the pair of second active structures, and the isolation layer and the dielectric structure located in the space of the pair of second active structures.

In addition, in the case where the isolation layer and the dielectric structure at the front-side transistor and the back-side transistor are formed twice, the isolation layer and the dielectric structure may be formed once in the interval of the pair of second active structures after the shallow trench isolation structure is thinned to expose the pair of second active structures.

In some embodiments, the implementation process of sequentially forming the isolation layer and the dielectric structure in the interval of the pair of second active structures may be: depositing isolation materials on the thinned shallow trench isolation structure and the pair of second active structures to form isolation layers, depositing dielectric materials on the isolation layers to form dielectric structures, and etching the isolation layers and the dielectric structures which are positioned on two sides of the pair of second active structures, wherein the etched isolation layers and the etched dielectric structures are positioned in the interval between the pair of second active structures.

Step S170: a back side transistor is formed based on the pair of second active structures.

The back side transistor comprises a back side source-drain structure and a back side interlayer dielectric layer.

In some embodiments, the implementation procedure of step S170 may be: epitaxially growing a pair of back source-drain structures on the pair of second active structures; an interlayer dielectric is deposited over the pair of back side source drain structures to form a pair of back side interlayer dielectric layers.

It should be noted that, since the stacked fork plate transistors are disposed in pairs on two sides of the dielectric structure, the back side transistors include two transistors in pairs, which may be a first back side transistor and a second back side transistor, the pair of back side source drain structures includes a first back side source drain structure and a second back side source drain structure disposed in pairs, and the pair of back side interlayer dielectric layers includes a first back side interlayer dielectric layer and a second back side interlayer dielectric layer disposed in pairs.

The preparation methods of the back source drain structure and the back interlayer dielectric layer of the back transistor are the same as those of the front source drain structure and the front interlayer dielectric layer of the front transistor, and are not described herein.

After the structure of the source-drain portion of the back-side transistor is completed, the gate structure of the back-side transistor is next prepared.

In some embodiments, the back side dummy gate structure formed by the foregoing steps may be removed first to expose the gate region of the back side transistor for subsequent formation of the back side gate structure.

Step S180: the isolation layer located in the space between the pair of second active structures is removed to form a second groove.

Wherein, there is metal material in the second recess.

It will be appreciated that after the back side dummy gate structure is removed, the silicon germanium layer in the stack structure of the bottom stack layer may also be selectively etched, and then the isolation layer located in the space between the pair of second active structures is removed to expose the gate region of the back side transistor adjacent to the dielectric structure. Since the isolation layer wraps the dielectric structure, after the isolation layer is removed, a second recess is formed in the space between the pair of second active structures.

Step S190: a back gate structure of the back transistor is formed in the gate region of the back transistor.

After removing the spacer, a back gate structure may be formed in the gate region of the back side transistor. The back gate structure comprises a first back gate structure and a second back gate structure which are oppositely arranged.

It should be noted that, in the process of forming the back gate structure, the second groove is also located in the gate region, so that a metal material is also present in the second groove, and the back gate structure is formed to surround the periphery of the second active structure, that is, the formed back gate structure is a four-gate device, so that the gate control effect can be enhanced.

In addition, during the deposition of the metal material, an isolation material may be deposited at a first portion of the gate region to form a second isolation structure, the first portion corresponding to the dielectric structure; and depositing a metal material in the rest area except the first part of the grid area to form a first back grid structure and a second back grid structure, wherein the first back grid structure and the second back grid structure are symmetrically arranged on two sides of the second isolation structure.

It should be noted that the second isolation structure is located on the surface of the dielectric structure between the pair of second active structures, and the height of the second isolation structure in the horizontal direction is identical to the height of the back gate structure. The first back gate structure of the second back transistor and the second gate structure of the second back transistor form the back gate structure, and the second isolation structure is used for isolating the first back gate structure and the second back gate structure.

In the embodiment of the present application, the metal materials forming the front gate structure and the back gate structure may be the same or different, which is not limited in the embodiment of the present application.

In some embodiments, after forming the back gate structure, back source drain metal of the back side transistor may be formed.

In some embodiments, after forming the back source drain structure, the back gate structure, and the back source drain metal, a back pass process may be performed over the back source drain metal to form a back metal interconnect layer of the back side transistor. The preparation methods of the back gate structure, the back source drain metal and the back metal interconnection layer of the back transistor are the same as those of the front gate structure, the front source drain metal and the front metal interconnection layer of the front transistor, and are not described herein.

In the embodiment of the application, the isolation layer and the dielectric structure are sequentially arranged in the interval of the pair of active structures, the isolation layer wraps the dielectric structure, then the isolation layer positioned in the middle of the active structures is removed to form the groove before the grid structure is formed, so that metal materials are filled in the groove in the process of forming the grid structure in the grid region of the transistor, and the front grid structure of the front transistor and the back grid structure of the back transistor which are finally formed are four-grid devices, thereby enhancing the control capability of the grid structure on a channel and weakening the short channel effect. And a certain design margin can be ensured especially when the fluctuation of the device structure and the metal work function occurs.

The stacked fork-plate transistor provided by the embodiment of the application is described below. Fig. 2 is a schematic top view of a stacked fork transistor according to an embodiment of the present application, where, for ease of understanding, only a nano-sheet structure, a gate structure, and a source-drain structure are shown in the top view. Wherein the A-A' direction is the tangential direction of the stacked fork plate transistor eye gate structure; the B-B' direction is the tangential direction of the stacked fork plate transistor along the source-drain structure; the C-C' direction is the tangential direction of the stacked transistor along the nanoplatelet structure.

The first fabrication process is described below, namely, forming the isolation layer and dielectric structure at the front-side transistor, and then forming the isolation layer and dielectric structure at the back-side transistor. Fig. 3A to 3H are schematic structural diagrams of a stacked fork transistor according to an embodiment of the present application in a first manufacturing process, and fig. 3I is a schematic structural diagram of a stacked fork transistor according to an embodiment of the present application.

It should be noted that the different steps (i.e., different processes) in the following examples may show the manufacturing process of the stacked fork plate transistor 10 with A-A ' direction, B-B ' direction, C-C ' direction, or different combinations of the above directions, respectively, according to the structural changes.

The first step: a substrate 20 is provided (see (a) in fig. 3A).

The preparation method of the substrate 20 comprises providing a Si layer, alternately depositing SiGe 1 material and Si material on the Si layer to form a laminated layer with a preset thickness, wherein the laminated layer is a bottom laminated layer 203; next, a SiGe 2 material is deposited on the bottom stack layer 203, forming an intermediate sacrificial layer 202; finally, siGe 1 material and Si material are alternately deposited on the intermediate sacrificial layer 202 to form a stack of a predetermined thickness, which is a top stack 201.

And a second step of: a semiconductor material is deposited on a portion of the region of the top stack 201 to form a pair of sidewall structures 21 (see (b) in fig. 3A).

And a third step of: the top stack layer 201, the intermediate sacrificial layer 202, and the bottom stack layer 203 are sequentially etched using the sidewall structure 21 as a mask, and the etching is stopped to the upper surface of the lowermost silicon layer of the bottom stack layer 203 to form a pair of active structures 22 (see (c) in fig. 3A).

Wherein the active structure 22 comprises a first active structure 221 remote from the bottom stack layer, a second active structure 222 close to the bottom stack layer, and an intermediate first intermediate sacrificial layer 23.

Fourth step: the sidewall structure 21 is removed (see (d) in fig. 3A).

Fifth step: oxide material is deposited on the lowermost Si layer of the bottom stack 203 to form shallow trench isolation structures 24 and CMP is performed to the top layer of the active structure 22 (see (e) in fig. 3A).

Sixth step: the shallow trench isolation structure 24 is etched to the first intermediate sacrificial layer 23 exposing the front side of the stacked fork plate transistor (see (f) in fig. 3A).

Seventh step: an isolation material is deposited over the shallow trench isolation structures 24 to form isolation layers 25, and a dielectric material is deposited over the isolation layers 25 to form dielectric structures 26 (see (g) in fig. 3A).

The isolation material may be, for example, siO2. As shown in (g) of fig. 3A, it can be seen that the isolation layer 25 and the dielectric structure 26 cover the middle and both sides of the pair of first active structures 221. The isolation layer 25 is referred to herein as an isolation layer at the front side transistor and the dielectric structure 26 is referred to as a dielectric structure at the front side transistor.

Eighth step: the isolation layer and the dielectric structure located at both sides of the pair of first active structures 221 are wet etched, leaving only the isolation layer and the dielectric structure located in the space of the pair of first active structures 221 (see (h) in fig. 3A).

Ninth step: the gate region of the front side transistor is opened by photolithography and a semiconductor structure is deposited in the gate region to form a front side dummy gate structure 27 (see (a) in fig. 3B).

Tenth step: the first intermediate sacrificial layer 23 is removed with the support of the front dummy gate structure 27, forming a third recess 28 (see (B) in fig. 3B).

An eleventh step; an insulating material is deposited in the third recess 28 and on the sidewalls of the front dummy gate structure 27 to form an intermediate isolation layer 29 and a front spacer 30 (see (c) in fig. 3B).

Twelfth step: the front-side source-drain structure 112 and the front-side interlayer dielectric layer 113 of the front-side transistor are formed in accordance with standard procedures (see (a) in fig. 3C).

Thirteenth step: the front dummy gate structure 27 is removed (see (b) in fig. 3C).

Fourteenth step: the SiGe 1 material in the first active structure 221 is selectively etched to form the first nanoplatelet structure 111 of the front-side transistor, exposing the gate region of the front-side transistor (see (C) in fig. 3C).

Fifteenth step: the isolation layer 25 in the space between the pair of first nano-sheet structures 111 is wet etched to form a first recess 31 to expose the gate region of the front-side transistor close to the dielectric structure (see (a) in fig. 3D).

As shown by B-B' in fig. 3D (a), the isolation layer 25 of the source drain region is preserved and serves as a support for the dielectric structure 26, since the front-side source drain structure 112 covers the isolation layer of the source drain region.

Sixteenth step: in the gate region of the front side transistor, an insulating material is deposited on the surface of the first nano-sheet structure 111, forming a front side gate dielectric layer 1141 (see (b) in fig. 3D).

Seventeenth step: depositing an isolation material over the dielectric structure 26 at the front side transistor to form a first isolation structure 32; depositing a metal material in the front gate dielectric layer 1141 and the first recess 31 in the gate region to form a front gate electrode layer 1142; depositing a metal material on the front-side source-drain structure 112 to form a front-side source-drain metal 115; a subsequent process is performed on the front-side source drain metal 115 to form a front-side metal interconnect layer 116 (see (c) in fig. 3D).

The front side gate dielectric layer 1141 and the front side gate electrode layer 1142 form the front side gate structure 114.

It will be appreciated that as shown by A-A' in fig. 3D (c), the first recess 31 is also located in the gate region, so that during the deposition of the metal material to form the front gate structure 114, the metal material is also present in the first recess 31, so that it can be seen that the periphery of the first nano-sheet structure 111 surrounds the front gate structure 114. That is, the gate structure of the final formed front-side transistor is a four-gate device.

Eighteenth step: depositing an insulating material on the front side metal interconnect layer 116 to form an insulating layer 13; bonding the carrier wafer 14 to the insulating layer 13; the front-side transistor 11 is rewound so as to be placed upward (see (a) in fig. 3E).

Nineteenth step: the lowermost Si layer of the bottom stacked layer 201 is removed by a wafer thinning process and a CMP process, and finally stops at the shallow trench isolation structure 24 (see (b) in fig. 3E).

Twenty-step: the shallow trench isolation structures 24 are thinned to expose a pair of second active structures 222 (see (a) in fig. 3F).

Twenty-first step: isolation material is deposited over the thinned shallow trench isolation structures 24 and the second active structure 222 to form isolation layers 33, and dielectric material is deposited over the isolation layers 33 to form dielectric structures 34 (see (b) in fig. 3F).

As shown in fig. 3F (b), it can be seen that the isolation layer 33 and the dielectric structure 34 cover the middle and both sides of the pair of second active structures. The isolation layer 33 is referred to herein as an isolation layer located at the back side transistor and the dielectric structure 34 is referred to as a dielectric structure located at the back side transistor.

Twenty-second step: the isolation layer and the dielectric structure located at both sides of the pair of second active structures 222 are wet etched, leaving only the isolation layer and the dielectric structure located in the space of the pair of second active structures 232 (see (a) in fig. 3G).

Twenty-third step: the source and drain portions of the back side transistor 12 are prepared in accordance with standard procedures to form a back side source and drain structure 122 and a back side interlayer dielectric layer 123 (see (b) in fig. 3G).

It will be appreciated that the gate region of the back side transistor 12 is first opened by photolithography and a semiconductor structure is deposited in the gate region to form a back side dummy gate structure; depositing an insulating material on the side wall of the back dummy gate structure to form a back spacer; sequentially forming a back source drain structure 122 and a back interlayer dielectric layer 123 according to standard steps; removing the back dummy gate structure; the SiGe 1 material in the second active structure 222 is selectively etched to form the second nano-sheet structure 121 of the back-side transistor.

Twenty-fourth step: the isolation layer 33 located in the space of the pair of second nano-sheet structures 121 is wet etched, forming a second recess 35 to expose the gate region of the back-side transistor close to the dielectric structure (see (a) in fig. 3H).

Twenty-fifth step: in the gate region of the back side transistor, an insulating material is deposited on the surface of the second nano-sheet structure 121, forming a back side gate dielectric layer 1241 (see (b) in fig. 3H).

Twenty-sixth step: depositing an isolation material over the dielectric structure 34 at the back side transistor to form a second isolation structure 36; depositing a metal material in the back gate dielectric layer 1241 and the second recess 35 in the gate region to form a back gate electrode layer 1242; depositing a metal material on the back source drain structure 122 to form a back source drain metal 125; a subsequent process is performed on the back side source drain metal 125 to form a back side metal interconnect layer 126 (see fig. 3I).

The back gate dielectric layer 1241 and the back gate electrode layer 1242 form the back gate structure 124.

It will be appreciated that as shown by A-A' in fig. 3I, the second recess 35 is also located in the gate region, so that during the deposition of the metal material to form the back gate structure 124, the metal material is also present in the second recess 35, so that it can be seen that the periphery of the second nano-sheet structure 121 surrounds the back gate structure 124. That is, the gate structure of the final formed back side transistor is a four gate device.

Based on the first preparation process of the embodiment of the application, the GAA gate-all-around device is finally formed to replace the original forksheet formed three-gate device, so that the control capability of the gate structure on the channel is further enhanced on the original basis, and the short channel effect is weakened. And a certain design margin is ensured especially when the fluctuation of the device structure and the metal work function occurs. While also ensuring self-alignment of the dielectric structure and the active region.

The second manufacturing process, i.e., one-shot forming of the isolation layer and dielectric structure at the front-side and back-side transistors, is described below. Fig. 4A to fig. 4E are schematic structural diagrams of a stacked fork transistor according to an embodiment of the present application in a second manufacturing process, and fig. 4F is a schematic structural diagram of a stacked fork transistor according to an embodiment of the present application.

The first step: the substrate 20 is etched in accordance with standard procedures to form a pair of active structures 22 and to remove the sidewall structures (see (a) in fig. 4A).

Reference is made here to the first to fourth steps of the preparation process of the first structure described above.

And a second step of: isolation material is deposited on the sidewalls of the substrate 20 and active structure 22 to form an isolation layer 37, and dielectric material is deposited on the isolation layer 37 to form a dielectric structure 38 (see (b) in fig. 4A).

The isolation material may be, for example, siO2. As shown in fig. 4A (b), it can be seen that isolation layer 37 and dielectric structure 38 cover the middle and both sides of a pair of active structures 22. The isolation layer 37 is referred to herein as the isolation layer at the front side and back side transistors and the dielectric structure 38 is referred to herein as the dielectric structure at the front side and back side transistors.

And a third step of: wet etching the isolation layer and dielectric structure located on both sides of the pair of active structures 22, leaving only the isolation layer and dielectric structure located in the space between the pair of active structures 22 (see (c) in fig. 4A)

Fourth step: oxide material is deposited on the lowermost Si layer of the bottom stack layer to form shallow trench isolation structures 24, and CMP is performed to the first inter-sacrificial layer 23 to expose a pair of first active structures 221 (see (d) in fig. 4A).

Fifth step: the front-side source-drain structure 112 and the front-side interlayer dielectric layer 113 of the front-side transistor are prepared in accordance with standard procedures, and the front-side dummy gate structure is removed (see (a) in fig. 4B).

Reference is made here to the ninth to thirteenth steps in the preparation of the first structure described above.

Sixth step: the SiGe 1 material in the first active structure 221 is selectively etched to form the first nanoplatelet structure 111 of the front-side transistor (see (B) in fig. 4B).

Seventh step: the isolation layer in the space of the first nano-sheet structure 111 is wet etched to form a first recess 31 to expose the gate region of the front-side transistor close to the dielectric structure (see (c) in fig. 4B).

Here, the etching rate needs to be strictly controlled so as to stop at the intermediate sacrificial layer separating the front and back transistors.

Eighth step: in the gate region of the front side transistor, an insulating material is deposited on the surface of the first nano-sheet structure 111, forming a front side gate dielectric layer 1141 (see (a) in fig. 4C).

Ninth step: depositing an isolation material over the dielectric structure at the front side transistor to form a first isolation structure 32; depositing a metal material in the front gate dielectric layer 1141 and the first recess 31 in the gate region to form a front gate electrode layer 1142; depositing a metal material on the front-side source-drain structure 112 to form a front-side source-drain metal 115; a subsequent process is performed on the front-side source drain metal 115 to form a front-side metal interconnect layer 116 (see (b) in fig. 4C).

It will be appreciated that as shown by A-A' in fig. 4C (b), the first recess 31 is also located in the gate region, so that during the deposition of the metal material to form the front gate structure 114, the metal material is also present in the first recess 31, so that it can be seen that the periphery of the first nano-sheet structure 111 surrounds the front gate structure 114. That is, the gate structure of the final formed front-side transistor is a four-gate device.

Tenth step: depositing an insulating material on the front side metal interconnect layer 116 to form an insulating layer 13; bonding the carrier wafer 14 to the insulating layer 13; the front side transistor 11 is reworked and the lowermost Si layer of the bottom stacked layer is removed, eventually stopping at the shallow trench isolation structure 24 (see (a) in fig. 4D).

Eleventh step: the front-side source-drain structure 122 and the back-side interlayer dielectric layer 123 of the back-side transistor are prepared, and the back-side dummy gate structure is removed, and the SiGe1 material in the second active structure 222 is selectively etched, forming a second nano-sheet structure 121 of the back-side transistor (see (b) in fig. 4D).

Twelfth step: the isolation layer in the space of the first nanoplatelet structure 121 is etched to form a second recess 35 to expose the gate region of the back side transistor close to the dielectric structure (see (a) in fig. 4E).

Here, the etching rate needs to be strictly controlled so that the isolation layer at the intermediate sacrificial layer remains as isolation.

Thirteenth step: in the gate region of the back side transistor, an insulating material is deposited on the surface of the second nano-sheet structure 121, forming a back side gate dielectric layer 1241 (see (b) in fig. 4E).

Fourteenth step: depositing an isolation material over the dielectric structure 34 at the back side transistor to form a second isolation structure 36; depositing a metal material in the back gate dielectric layer 1241 and the second recess 35 in the gate region to form a back gate electrode layer 1242; depositing a metal material on the back source drain structure 122 to form a back source drain metal 125; a subsequent process is performed on the back side source drain metal 125 to form a back side metal interconnect layer 126 (see fig. 4F).

It will be appreciated that as shown by A-A' in fig. 4F, the second recess 35 is also located in the gate region, so that during the deposition of the metal material to form the back gate structure 124, the metal material is also present in the second recess 35, so that it can be seen that the periphery of the second nano-sheet structure 121 surrounds the back gate structure 124. That is, the gate structure of the final formed back side transistor is a four gate device.

The second preparation process of the embodiment of the application has the advantages of a four-gate device, simultaneously the oxide layer and the dielectric structure of forksheet are completed in one step, the alignment and the consistency are stronger, the process flow can be simplified, and the influence of the high-temperature environment on the front-side transistor when the isolation layer is deposited for preparing the back-side transistor is avoided.

A third manufacturing process is described below, in which the isolation layer and dielectric structure at the front side and back side transistors are formed in one step, with shallow trench isolation structures in between. Fig. 5A to 5E are schematic structural diagrams of a stacked fork transistor according to a third embodiment of the present application, and fig. 5F is a schematic structural diagram of a stacked fork transistor according to a third embodiment of the present application.

The first step: the substrate 20 is etched in accordance with standard procedures to form a pair of active structures 22 and to remove the sidewall structures (see (a) in fig. 5A).

And a second step of: isolation material is deposited on the sidewalls of the substrate 20 and active structure 22 to form an isolation layer 37, and dielectric material is deposited on the isolation layer 37 to form a dielectric structure 38 (see (b) in fig. 5A).

And a third step of: the isolation layer 37 and the dielectric structure 38 are wet etched, leaving only the isolation layer and the structure of the back side transistor fork plate portion (see (c) in fig. 5A).

As shown in fig. 5A (c), the remaining isolation layer 37 and dielectric structure 38 are present only in the space between the pair of second active structures 222.

Fourth step: an oxide material is deposited on the lowermost Si layer of the bottom stack layer to form shallow trench isolation structures 24, and CMP is performed to the intermediate sacrificial layer to expose a pair of first active structures 221 (see (d) in fig. 5A).

As shown in fig. 5A (d), the shallow trench isolation structure 24 is covered over the isolation layer 37 and the dielectric structure 38 to serve as an isolation layer for the front-back transistor and the dielectric structure.

Fifth step: isolation material is deposited on the sidewalls of the shallow trench isolation structures 24 and the first active structures 221 to form isolation layers 25, and dielectric material is deposited on the isolation layers 25 to form dielectric structures 26 (see (e) in fig. 5A).

The isolation layer 25 is referred to herein as an isolation layer at the front side transistor and the dielectric structure 26 is referred to as a dielectric structure at the front side transistor.

Sixth step: the isolation layer 25 and the dielectric structure 26 are wet etched, leaving only the isolation layer and the dielectric structure located in the space of the pair of first active structures 221 (see (f) in fig. 5A).

Seventh step: the front-side source-drain structure 112 and the front-side interlayer dielectric layer 113 of the front-side transistor are prepared in accordance with a standard flow, and the front-side dummy gate structure is removed (see (a) in fig. 5B).

Eighth step: the SiGe 1 material in the first active structure 221 is selectively etched to form the first nanoplatelet structure 111 of the front-side transistor (see (B) in fig. 5B).

Ninth step: the isolation layer in the space of the first nano-sheet structure 111 is etched to form a first recess 31 to expose the gate region of the front-side transistor close to the dielectric structure (see (c) in fig. 5B).

It should be noted that this step only needs to selectively etch the isolation layer portion by using the selectivity of etching, so that strict control of the etching rate is not required.

Tenth step: in the gate region of the front side transistor, an insulating material is deposited on the surface of the first nano-sheet structure 111, forming a front side gate dielectric layer 1151 (see (a) in fig. 5C).

Eleventh step: depositing an isolation material over the dielectric structure at the front side transistor to form a first isolation structure 32; depositing a metal material in the front gate dielectric layer 1151 and the first recess 31 in the gate region to form a front gate electrode layer 1152; depositing a metal material on the front-side source-drain structure 112 to form a front-side source-drain metal 115; a subsequent process is performed on the front-side source drain metal 115 to form a front-side metal interconnect layer 116 (see (b) in fig. 5C).

Wherein the front side gate dielectric layer 1151 and the front side gate electrode layer 1152 constitute the front side gate structure 115.

It will be appreciated that as shown by A-A' in fig. 5C (b), the first recess 31 is also located in the gate region, so that during the deposition of the metal material to form the front gate structure 115, the metal material is also present in the first recess 31, so that it can be seen that the periphery of the first nano-sheet structure 111 surrounds the front gate structure 115. That is, the gate structure of the final formed front-side transistor is a four-gate device.

Twelfth step: depositing an insulating material on the front side metal interconnect layer 116 to form an insulating layer 13; bonding the carrier wafer 15 to the insulating layer 13; the front side transistor 11 is reworked and the lowermost Si layer of the bottom stacked layer is removed, eventually stopping at the shallow trench isolation structure 24 (see (a) in fig. 5D).

Thirteenth step: the front-side source-drain structure 122 and the back-side interlayer dielectric layer 123 of the back-side transistor are prepared, and the back-side dummy gate structure is removed, and the SiGe1 material in the second active structure 222 is selectively etched, forming a second nano-sheet structure 121 of the back-side transistor (see (b) in fig. 5D).

Fourteenth step: the isolation layer in the space of the second nanoplatelet structure 121 is etched to form a second recess 35 to expose the gate region of the back side transistor close to the dielectric structure (see (a) in fig. 5E).

Fifteenth step: in the gate region of the back side transistor, an insulating material is deposited on the surface of the second nano-sheet structure 121, forming a back side gate dielectric layer 1251 (see (b) in fig. 5E).

Sixteenth step: depositing an isolation material on the dielectric structure 35 at the back side transistor to form a second isolation structure 36; depositing a metal material in the back gate dielectric layer 1251 and the second recess 35 in the gate region to form a back gate electrode layer 1252; depositing a metal material on the back source drain structure 122 to form a back source drain metal 125; a subsequent process is performed on the back side source drain metal 125 to form a back side metal interconnect layer 126 (see fig. 5F).

Wherein back gate dielectric layer 1251 and back gate electrode layer 1252 constitute back gate structure 125.

It will be appreciated that as shown by A-A' in fig. 5F, the second recess 35 is also located in the gate region, so that during the deposition of the metal material to form the back gate structure 125, the metal material is also present in the second recess 35, so that the second nano-sheet structure 121 is seen to surround the back gate structure 125 around its periphery. That is, the gate structure of the final formed back side transistor is a four gate device.

The third preparation process of the embodiment of the application also has the advantages of the four-gate device. Compared with the first preparation process, the isolation layer and the dielectric structure are manufactured at the beginning, the consistency is good, the thermal budget can be saved, and the influence of heating on the device during deposition is avoided. Meanwhile, compared with the second preparation process, the method has better selectivity when etching the isolation layer at the dielectric structure, and has lower requirement on the accuracy of etching time, and the etching time is strictly controlled when etching the isolation layer in the second preparation process.

Further, the stacked fork plate transistor provided by the embodiment of the application can be detected by using a detection analysis instrument, for example: scanning electron microscope (scanning electron microscope, SEM), transmission electron microscope (transmission electron microscope, TEM), scanning transmission electron microscope (scanning transmission electron microscopy, STEM), and the like. Taking TEM as an example, the embodiment of the present application may detect the structure of the stacked fork plate transistor by using a TEM section method.

An embodiment of the present application provides a semiconductor device including: stacked fork plate transistors as in the above embodiments. Specific limitations of stacked fork plate transistors can be found in the stacked fork plate transistors described above, and are not described herein.

An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device includes the stacked fork plate transistor described above. Specific limitations of stacked fork plate transistors can be found in the stacked fork plate transistors described above, and are not described herein.

In the description of the present application, a description of the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method of making a stacked fork plate transistor, the method comprising:

Forming a pair of active structures on a substrate, wherein a space exists between the pair of active structures, the pair of active structures comprises a pair of first active structures and a pair of second active structures, the first active structures are far away from the substrate than the second active structures, and the active structures are nano-sheet structures;

sequentially forming an isolation layer and a dielectric structure in the interval of the pair of active structures, wherein the isolation layer wraps the dielectric structure;

forming a front-side transistor based on the pair of first active structures, wherein the front-side transistor comprises a front-side source-drain structure and a front-side interlayer dielectric layer;

Removing the isolation layer located in the space between the pair of first active structures to form a first groove;

Forming a front-side gate structure of the front-side transistor in a gate region of the front-side transistor, wherein a metal material exists in the first groove;

Rewinding and removing the substrate to expose the pair of second active structures;

Forming a back side transistor based on the pair of second active structures, wherein the back side transistor comprises a back side source-drain structure and a back side interlayer dielectric layer;

removing the isolation layer located in the space between the pair of second active structures to form a second groove;

and forming a back gate structure of the back transistor in a gate region of the back transistor, wherein a metal material exists in the second groove.

2. The method of claim 1, wherein after sequentially forming the isolation layer and the dielectric structure in the space between the pair of active structures, the method further comprises:

Etching the isolation layer and the dielectric structure located in the space between the pair of first active structures;

Forming shallow trench isolation structures on the substrate to cover the pair of second active structures and the isolation layer and the dielectric structure located in the space of the pair of second active structures and to expose the pair of first active structures and the isolation layer and the dielectric structure located in the space of the pair of first active structures;

sequentially forming an isolation layer and a dielectric structure positioned in the interval of the pair of first active structures on the shallow trench isolation structure;

the forming a front-side transistor based on the pair of first active structures includes:

the front side transistor is formed on the shallow trench isolation structure based on the pair of first active structures.

3. The method of claim 1, wherein after sequentially forming the isolation layer and the dielectric structure in the space between the pair of active structures, the method further comprises:

4. A method according to claim 2 or 3, wherein the rewinding and removing the substrate to expose the pair of second active structures comprises:

Rewinding and removing the substrate;

And thinning the shallow trench isolation structure to a preset height so as to expose the pair of second active structures, and isolating layers and dielectric structures which are positioned in the interval of the pair of second active structures.

5. The method of claim 1, wherein sequentially forming an isolation layer and a dielectric structure in the space between the pair of active structures comprises:

forming a shallow trench isolation structure on the substrate to cover the pair of second active structures and expose the pair of first active structures;

the rewinding and removing the substrate to expose the pair of second active structures, comprising:

Rewinding and removing the substrate;

Thinning the shallow trench isolation structure to a preset height so as to expose the pair of second active structures;

after rewinding and removing the substrate to expose the pair of second active structures, the method further comprises:

An isolation layer and a dielectric structure are sequentially formed in the space between the pair of second active structures.

6. The method of claim 1, wherein forming a pair of active structures on a substrate comprises:

providing a substrate, wherein the substrate comprises a top stacking layer, an intermediate sacrificial layer and a bottom stacking layer which are stacked in sequence;

Depositing semiconductor material on a first region of the top stack layer to form a pair of oppositely disposed sidewall structures with a space therebetween;

And etching the substrate by taking the side wall structure as a mask to form the pair of active structures.

7. The method of claim 6, wherein prior to forming a front-side transistor based on the pair of first active structures, the method further comprises:

removing the intermediate sacrificial layer to form a third groove;

An insulating material is deposited in the third recess to form an intermediate isolation layer for isolating the first active structure from the second active structure.

8. The method of claim 1, wherein after forming a front-side gate structure of the front-side transistor within a gate region of the front-side transistor, the method further comprises;

performing a back-end process over the front-side gate structure to form a front-side metal interconnect layer of the front-side transistor;

after forming the back gate structure of the back side transistor in the gate region of the back side transistor, the method further comprises:

and performing a back-end process on the back gate structure to form a back metal interconnection layer of the back transistor.

9. A stacked fork plate transistor prepared using the method of any one of claims 1-8, comprising:

A front side transistor;

A back side transistor, the front side transistor being self-aligned with the back side transistor;

The dielectric structure penetrates through the first active structure of the front transistor and the second active structure of the back transistor, the dielectric structure divides the first active structure into two parts which are symmetrically arranged, the second active structure is divided into two parts which are symmetrically arranged, the peripheral side of the dielectric structure at the front transistor is a front grid structure of the front transistor, the peripheral side of the dielectric structure at the back transistor is a back grid structure of the back transistor, and the first active structure and the second active structure are nano-sheet structures.

10. A semiconductor device, comprising: the stacked fork plate transistor of claim 9.

11. An electronic device, comprising: a circuit board and the semiconductor device according to claim 10, the semiconductor device being provided to the circuit board.