CN117940998A - 存储器裸片与逻辑裸片之间的信号路由 - Google Patents

存储器裸片与逻辑裸片之间的信号路由 Download PDF

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Publication number
CN117940998A
CN117940998A CN202280054049.8A CN202280054049A CN117940998A CN 117940998 A CN117940998 A CN 117940998A CN 202280054049 A CN202280054049 A CN 202280054049A CN 117940998 A CN117940998 A CN 117940998A
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China
Prior art keywords
die
memory
signals
logic
logic die
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CN202280054049.8A
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English (en)
Inventor
S·S·艾勒特
G·E·胡申
K·R·帕雷克
A·T·扎伊迪
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Micron Technology Inc
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Micron Technology Inc
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Publication of CN117940998A publication Critical patent/CN117940998A/zh
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Abstract

一种存储器装置包含经由晶片上晶片接合而接合到逻辑裸片的存储器裸片。耦合到所述存储器裸片的所述存储器装置的控制器可激活所述存储器裸片的一行。响应于激活所述行，所述存储器裸片的感测放大器条带可锁存第一多个信号。收发器可将第二多个信号从所述感测放大器路由到所述逻辑裸片。

Description

存储器裸片与逻辑裸片之间的信号路由
技术领域
本公开大体上涉及存储器，且更特定来说，涉及与用于在存储器裸片与逻辑裸片之间路由信号的存储器装置相关联的设备及方法。
背景技术
存储器装置通常被提供为计算机或其它电子装置中的内部半导体集成电路。存在许多不同类型的存储器，其包含易失性及非易失性存储器。易失性存储器需要电力来维持其数据且包含随机存取存储器(RAM)、动态随机存取存储器(DRAM)及同步动态随机存取存储器(SDRAM)等。非易失性存储器可通过在未被供电时保存所存储数据来提供持久数据且可包含NAND快闪存储器、NOR快闪存储器、只读存储器(ROM)、电可擦除可编程ROM(EEPROM)、可擦除可编程ROM(EPROM)及电阻可变存储器(例如相变随机存取存储器(PCRAM))、电阻性随机存取存储器(RRAM)及磁阻随机存取存储器(MRAM)等。
存储器还用作各种电子应用的易失性及非易失性数据存储装置，所述应用包含(但不限于)个人计算机、便携式记忆棒、数码相机、蜂窝电话、例如MP3播放器的便携式音乐播放器、电影播放器及其它电子装置中。存储器单元可布置成阵列，其中阵列用于存储器装置中。
附图说明
图1说明根据本公开的数个实施例的呈包含存储器装置及逻辑装置的系统的形式的设备的框图。
图2说明根据本公开的数个实施例的包含存储器裸片及逻辑裸片的经接合晶片的一部分。
图3说明根据本公开的数个实施例的存储器裸片的电路图。
图4说明根据本公开的数个实施例的存储体的电路图。
图5说明根据本公开的数个实施例的存储器裸片及逻辑裸片。
图6A说明根据本公开的数个实施例的感测放大器及多路复用器的电路图。
图6B说明根据本公开的数个实施例的本地输入输出(LIO)线的电路图。
图7是根据本公开的一些实施例的对应于用于在存储器裸片与逻辑裸片之间路由信号的方法的流程图。
具体实施方式
本公开包含用于在存储器裸片与逻辑裸片之间路由信号的与存储器装置有关的设备及方法。已经提出廉价且节能的逻辑装置。此类装置可从紧密耦合到存储器装置获益。逻辑装置可为加速器。加速器可包含人工智能(AI)加速器，例如深度学习加速器(DLA)。
AI是指例如通过“学习”(例如通过存储可用于在稍后时间采取动作的模式及/或实例)改进机器的能力。深度学习是指装置从作为实例提供的数据学习的能力。深度学习可为AI的子集。神经网络以及其它类型的网络可被分类为深度学习。低功率、廉价设计的深度学习加速器可实施于物联网(IOT)装置中。DLA可在运行时进行处理并做出智能决策。包含边缘DLA的存储器装置也可部署于远程位置中，而无需云或卸载能力。
三维集成电路(3D IC)是一种金属-氧化物半导体(MOS)IC，其通过堆叠半导体晶片或裸片并使用例如穿硅通路(TSV)或金属连接将它们竖直互连来制造，以充当单个装置来以与常规二维工艺相比降低的功率及较小的占用面积实现性能改进。3D IC的实例包含混合存储器立方体(HMC)及高带宽存储器(HBM)以及其它。
实施使用3D IC耦合存储器裸片及逻辑裸片的存储器装置可从数据在存储器裸片与逻辑裸片之间的高效传送获益。将数据从存储器裸片传送到逻辑裸片可包含将数据从存储器裸片传送到全局数据总线及将所述数据从全局数据总线传送到逻辑裸片。然而，将数据从全局数据总线传送到逻辑裸片可能是低效的。
本公开的方面解决上述及其它缺点。例如，本公开的至少一个实施例可经由通过晶片上晶片接合工艺接合的存储器裸片与逻辑裸片之间的宽总线提供高带宽。存储器裸片与逻辑裸片之间的总线可经实施使得数据被传送到逻辑裸片而无需通过全局数据总线。使用宽总线在存储器裸片与逻辑裸片之间传送数据可比经由全局数据总线传送数据更高效。
本文中的图遵循编号惯例，其中首位或前几位数字对应于图号且剩余数字识别图式中的元件或组件。不同图之间的类似元件或组件可通过使用类似数字来识别。举例来说，100指代图1中的“00”，且类似元件在图2中被标注为200。图内的类似元件可用连字符及额外数字或字母来指代。参见例如图6中的元件663-1、663-2。应了解，本文各种实施例中展示的元件可经添加、交换及/或消除以便提供本公开的数个额外实施例。另外，应了解，图中提供的元件的比例及相对尺度希望说明本发明的某些实施例且不应被视为意在限制。
图1说明根据本公开的数个实施例的呈包含存储器装置102及逻辑装置104的系统100的形式的设备的框图。如本文中使用，例如，存储器装置102、存储器阵列110及/或逻辑装置104也可被单独视作一“设备”。
在此实例中，系统100包含经由接口112(例如输入/输出“IO”接口)耦合到逻辑装置104的存储器装置102。系统100可为个人膝上型计算机、台式计算机、数码相机、移动电话、存储卡读取器、服务器或具有物联网(IoT)能力的装置以及各种其它类型的系统的部分。系统100可包含单独集成电路，或存储器装置102及逻辑装置104两者都可在同一集成电路上。逻辑装置104可为人工智能(AI)加速器，作为实例，其在本文中也被称为深度学习加速器(DLA)。逻辑装置104在本文中可称为DLA 104。DLA 104可实施于系统100的边缘上。举例来说，DLA 104可实施于存储器装置102外部。DLA可耦合到IO电路系统112且因此耦合到数据路径114，数据路径114耦合到存储器阵列110。
在各种实例中，DLA 104可接合到存储器装置102。举例来说，存储器装置的存储器裸片可接合到DLA 104的逻辑裸片。逻辑裸片104可包含控制电路系统118。控制电路系统118可控制逻辑裸片104的收发器经由将存储器裸片耦合到逻辑裸片的晶片上晶片接合将数据从存储器装置102路由到逻辑裸片104。
为了清楚，系统100已经简化以集中于与本公开特别相关的特征。例如，存储器阵列110可为DRAM阵列、SRAM阵列、STT RAM阵列、PCRAM阵列、TRAM阵列、RRAM阵列、NAND快闪阵列、NOR快闪阵列及/或3D交叉点阵列。作为实例，存储器阵列110在本文中可被称为DRAM阵列。阵列110可包括布置成通过存取线(其在本文中可被称为字线或选择线)耦合的行及通过感测线(其在本文中可被称为数字线或数据线)耦合的列的存储器单元。尽管存储器阵列110被展示为单个存储器阵列，但存储器阵列110可表示布置成存储器装置102的存储体的多个存储器阵列。
尽管未明确说明，但存储器装置102包含用以锁存经由主机接口提供的地址信号的地址电路系统。例如，主机接口可包含采用合适协议的物理接口(例如，数据总线、地址总线及命令总线或组合的数据/地址/命令总线)。此协议可为自定义或专有的，或主机接口可采用标准化协议，例如外围组件互连快速(PCIe)、Gen-Z互连、加速器的高速缓存一致互连(CCIX)或类似物。地址信号由行解码器及列解码器接收及解码以存取存储器阵列110。数据可通过使用感测电路系统感测感测线上的电压及/或电流变化来从存储器阵列110读取。感测电路系统可耦合到存储器阵列110。每一存储器阵列110及对应感测电路系统可构成存储器装置102的存储体。例如，感测电路系统可包括可读取及锁存来自存储器阵列110的一页(例如，一行)数据的感测放大器。IO电路系统112可用于沿着数据路径114与逻辑装置104进行双向数据通信。读取/写入电路系统用于将数据写入到存储器阵列110或从存储器阵列110读取数据。读取/写入电路系统可包含各种驱动器、锁存电路系统等。
控制电路系统116(例如内部控制件)可解码由主机提供的信号。信号可为由主机提供的命令。这些信号可包含用于控制对存储器阵列110执行的操作的芯片启用信号、写入启用信号及地址锁存信号，所述操作包含数据读取操作、数据写入操作及数据擦除操作。在各种实施例中，控制电路系统116负责执行来自主机的指令。控制电路系统116可包括状态机、序列发生器及/或某种其它类型的控制电路系统，其可以硬件、固件或软件或所述三者的任何组合的形式实施。在一些实例中，主机可为存储器装置102外部的控制器。举例来说，主机可为耦合到计算装置的处理资源的存储器控制器。数据可经由将逻辑装置104耦合到IO电路系统112的数据线被提供到逻辑装置104及/或从逻辑装置104提供。
DLA104也可耦合到控制电路系统116。控制电路系统116可控制DLA 104。举例来说，控制电路系统116可将信令提供到行解码器及列解码器以致使数据从存储器阵列102传送到DLA 104，以将输入提供到DLA104及/或由DLA 104托管的人工神经网络(ANN)。控制电路系统116还可致使DLA 104及/或ANN的输出被提供到IO电路系统112及/或存储回到存储器阵列110。
ANN模型可由DLA 104、控制电路系统116及/或由外部主机(未明确说明)训练。举例来说，主机及/或控制电路系统116可训练可被提供到DLA 104的ANN模型。DLA 104可按照控制电路系统116的指示实施经训练ANN模型。ANN可经训练以执行所期望功能。
在将电子装置(例如存储器装置102及DLA 104)制造于第一晶片及第二晶片上之后，第一晶片及第二晶片可被切割(例如，由旋转锯片沿着第一晶片及第二晶片的切道切割)。然而，根据本公开的至少一个实施例，在将装置制造于第一晶片及第二晶片上之后，且在切割之前，第一晶片及第二晶片可通过晶片上晶片接合工艺接合在一起。在晶片上晶片接合工艺之后，可单切裸片(例如存储器裸片及逻辑裸片)。举例来说，存储器晶片可以面对面定向接合到逻辑晶片，这意味着其相应衬底(晶片)两者都在接合远端，而存储器裸片及逻辑裸片在接合近端。这使个别存储器裸片及逻辑裸片能够在存储器晶片及逻辑晶片接合在一起之后被一起单切为单个封装。
图2说明根据本公开的数个实施例的包含存储器裸片202及逻辑裸片204的经接合晶片的一部分。存储器裸片202被说明为接合到衬底208，然而，在至少一个实施例中，逻辑裸片204而不是存储器裸片202可接合到衬底208。衬底208、存储器裸片202、接合206及逻辑裸片204可形成经配置以执行一或多个所期望功能的系统200，例如集成电路。尽管未明确说明，但衬底208可包含额外电路系统以操作、控制存储器裸片202、逻辑裸片204及/或其它芯片外装置及/或与存储器裸片202、逻辑裸片204及/或其它芯片外装置通信。
根据本公开的至少一个实施例，存储器裸片202的典型功能性针对典型存储器操作不改变。然而，数据可替代地直接经由接合206从存储器裸片202传送到逻辑裸片204，而不是通过存储器裸片202的典型输入/输出电路系统路由。举例来说，存储器裸片202的测试模式及/或刷新循环可用于经由接合206(例如，经由存储器裸片202的LIO)将数据传送到逻辑裸片204及从逻辑裸片204传送数据。针对实例现存DRAM存储器装置使用刷新循环，在每存储体8行有效且刷新循环时间是80纳秒(与单个行的60纳秒相比)的情况下，对于4个并行存储体及16纳秒的存储体定序，带宽将是443千兆字节/秒。然而，根据本公开的至少一个实施例，使用晶片上晶片接合206，在每存储体32行有效的情况下，对于32个并行存储体，刷新循环时间可接近60纳秒，且在无存储体定序的情况下，在使用8瓦特时带宽是5太字节/秒。从存储器装置发送数据的这种显著带宽将压垮典型接口及/或主机装置。然而，某些逻辑装置(例如DLA)可经配置以经由由接合206提供的连接来使用所述数据带宽。数据的芯片外移动减少可有助于降低与以此方式操作存储器相关联的功率消耗。例如，与一些当前解决方案相比，本公开的一些实施例可在深度可分离网络中提供70x的性能提高及/或在自然语言处理(NLP)/推荐系统上提供130x的性能提高。当实施于边缘服务器中时，例如，与当前解决方案相比，本公开的一些实施例可提供16x到32x的存储器带宽。
尽管未明确说明，但多个存储器裸片202可经由类似于接合206的接合彼此上下堆叠。替代地或另外，TSV可用于在经堆叠存储器裸片202之间或通过经堆叠存储器裸片202传达数据。经堆叠存储器裸片202之间的接合垫可在以竖直定向(如所说明)复制于经堆叠存储器裸片202上的位置处使得经堆叠存储器裸片202对准。经堆叠存储器裸片202可通过常规工艺或在不同实施例中通过晶片上晶片接合(在不同存储器晶片之间)形成。
尽管未明确说明，但接合到衬底208的裸片(例如，存储器裸片202(如所说明)或逻辑裸片204)可在其中形成TSV以实现与在存储器裸片202及逻辑裸片204外部的电路系统的通信。TSV也可用于提供电源及接地触点。与通过晶片上晶片接合提供的触点相比，TSV通常具有更大电容及更大间距且不具有同样大的带宽。
尽管未明确说明，但在一些实施例中，额外组件可接合到系统200。举例来说，热解决方案组件可接合到逻辑裸片204的顶部以为系统200提供冷却。逻辑裸片204与存储器裸片202之间的物理紧密连接可产生热。热解决方案可有助于为系统200散热。
尽管未明确说明，但在一些实施例中，额外组件(非易失性存储器)可接合到系统200(例如，以便持久存储ANN的模型)。然而，在一些实施例中，非易失性存储器是不必要的，这是因为模型可能相对较小且频繁地进行更新。
图3说明根据本公开的数个实施例的存储器裸片302的电路图。实例存储器裸片302包含布置成由4个存储体组成的存储体群组324的16个存储体325。每一存储体群组324耦合到全局数据总线(GBUS)321(例如，256位宽总线)。实施例不限于这些特定实例。全局数据总线321可经建模为充电/放电电容器。全局数据总线321可符合用于经由IO总线从存储器裸片302发送数据的存储器标准。然而，尽管图3中未明确说明，但根据本公开的至少一个实施例，经由晶片上晶片接合耦合到存储器裸片302的逻辑裸片可包含用于经由晶片上晶片接合将数据从存储器裸片302传达到逻辑裸片的收发器。
图4说明根据本公开的数个实施例的存储体425。存储体425包含一定数量的存储器片块433，其各自包含由经填充点表示的相应数量的局部IO线431。每一片块433可包含一定数量的存储器单元行及一定数量的存储器单元列(例如，1024x 1024)。举例来说，每一片块可包含32个LIO 431。每一片块中的LIO 431耦合到相应全局IO线432及多路复用器461，多路复用器461在所属领域中也可称为收发器，在本文中称为多路复用器以与经配置以从局部IO线431、全局IO线432及/或全局数据总线421接收信号的逻辑裸片的收发器区分开。
多路复用器461可经配置以从局部IO线431接收信号。多路复用器461选择局部IO线431的一部分。多路复用器461可放大从局部IO线431的选定部分接收的信号。多路复用器461还可致使经放大信号经由全局IO线432进行传输。多路复用器461还可从全局IO线432接收信号且减少接收到的信号。多路复用器461可进一步将减少的信号传输到局部IO线431。
全局IO线432耦合到全局数据总线结构421。来自多个感测放大器的信号可被多路复用到局部IO线431中。局部IO线431可经由晶片上晶片接合耦合到多路复用器461及收发器(未展示)。逻辑裸片的收发器(未展示)可致使来自局部IO线431的信号经由晶片上晶片接合被提供到逻辑裸片。晶片上晶片接合提供足够精细的间距控制以允许在收发器(未展示)与局部IO线431之间有触点，这原本将是不可能的。
在至少一个实施例中，逻辑裸片的收发器(未展示)可从对应逻辑裸片接收启用/停用命令(例如，而不是从主机接收命令)。在一些实施例中，启用/停用命令可由逻辑裸片的多个收发器接收(例如，启用/停用命令可致使指示数据的信号经由对应收发器从每一存储体425中的特定行进行传送)。逻辑裸片的多个收发器的控制及操作类似于具有数千个存储器控制器，区别仅在于它们传送数据而不是控制所有操作。例如，对于涉及大量并行存储器存取操作的应用来说，此操作可为有益的。针对经配置以包含8千位行的实例存储器装置，逻辑裸片的每收发器可预取256位数据。因此，逻辑裸片的每一收发器可绑定有256个位。换句话说，针对每一8千位的所存储数据，本公开的至少一个实施例可传送256位数据(在此实例架构中)。相比之下，根据具有类似架构的一些先前方法，针对4千兆位的所存储数据，典型存储器接口(例如，经由全局IO)将仅能够传送256个位。
图5说明根据本公开的数个实施例的存储器裸片502及逻辑裸片504。存储器裸片502可包含包括LIO 531的多个LIO。逻辑裸片504也可包含包括LIO 541的多个LIO。
在各种实例中，信号可从存储器裸片502路由到LIO 541。信号也可从LIO 541路由到存储器裸片。信号可利用存储器裸片502的收发器及/或逻辑裸片504的收发器来在存储器裸片502与LIO 541之间路由。
在数个实例中，信号可利用存储器裸片502的LIO 531从存储器裸片502路由到逻辑裸片504。举例来说，信号可从存储器裸片502的存储器阵列路由到存储器裸片502的LIO531。信号可利用逻辑裸片的收发器从LIO 531路由到逻辑裸片504的LIO 541。信号可经路由以使逻辑裸片504能够从存储器裸片502读取数据。信号还可利用逻辑裸片的收发器从LIO 541路由到LIO 531。信号可从LIO 541路由到LIO 531以允许逻辑裸片504将数据写入到存储器裸片502。收发器可定位于逻辑裸片504中。
图6A说明根据本公开的数个实施例的感测放大器663-1、663-2、…、663-N、663-N+1、663-N+2、…、663-M、663-M+1、663-M+2、…、663-P及多路复用器664-1、664-2、…、664-S的电路图。感测放大器663-1、663-2、…、663-N、663-N+1、663-N+2、…、663-M、663-M+1、663-M+2、…、663-P可被称为感测放大器663。多路复用器664-1、664-2、…、664-S可被称为多路复用器664。图6A还包含存储器裸片的多路复用器661。
多路复用器661与收发器665-1、665-2、…、665-S有区别。多路复用器661可经配置以从局部IO线631接收信号。多路复用器661选择局部IO线631的一部分。多路复用器661可放大从局部IO线631的选定部分接收的信号。多路复用器661还可致使经放大信号经由全局IO线632进行传输。多路复用器661还可从全局IO线632接收信号且减少接收到的信号。多路复用器661可进一步将减少的信号传输到局部IO线631。尽管多路复用器661被称为多路复用器，但多路复用器661与多路复用器664不同且具有与多路复用器664不同的功能。
收发器665-1、665-2、…、665-S也可接收信号，选择信号的一部分，放大信号的部分及传输经放大信号。然而，收发器665-1、665-2、…、665-S可将经放大信号传输到逻辑裸片，而不是全局IO线632。
图6A进一步包含逻辑裸片的收发器665-1、665-2、…、665-S，在本文中称为收发器665。存储器裸片可包含感测放大器663、多路复用器664及多路复用器661。存储器裸片还可包含LIO 631及全局IO(GIO)632。举例来说，存储器裸片的图3的存储器片块334可包含感测放大器663、多路复用器664、多路复用器661、LIO 631及GIO 632。
存储器片块还可包含可编程以存储不同状态的存储器单元(未展示)。存储器单元中的每一者可编程以存储标示为逻辑0及逻辑1的两种状态。在一些情况下，存储器单元经配置以存储多于两种逻辑状态。存储器单元可包含用以存储表示可编程状态的电荷的电容器；例如，带电的电容器及不带电的电容器可表示两种逻辑状态。DRAM架构可通常使用此设计，且所采用的电容器可包含具有线性电极化性质的介电材料。
可通过激活或选择所当存取线及感测线来对存储器单元执行例如读取及写入的操作。激活或选择存取线或感测线可包含将电压电势施加于相应线。如本文中使用，激活或选择存取线可称为激活或选择一行存储器单元。存取线及感测线可由导电材料制成。在一些实例中，存取线及感测线由金属(例如，铜、铝、金、钨等)制成。每一行存储器单元连接到单根存取线，且每一列存储器单元连接到单根感测线。通过激活一根存取线及一根感测线，可存取其相交点处的单个存储器单元。存取线与感测线的相交点可被称为存储器单元的地址。通过激活一根存取线及多根感测线，可存取一行存储器单元。多根存取线与所述感测线的相交点可称为一行存储器单元的地址。
在一些架构中，单元的存储组件(例如，电容器)可通过选择装置与数字线电隔离。存取线可连接到选择装置且可控制选择装置。举例来说，所述选择装置可为晶体管，且存取线可连接到晶体管的栅极。激活存取线在存储器单元的电容器与其对应感测线之间产生电连接。感测线可接着经存取以读取或写入存储器单元。
存取存储器单元可通过行解码器及列解码器(未展示)来控制。举例来说，行解码器可从存储器控制器(例如控制电路系统)接收行地址且基于接收到的行地址激活适当存取线。类似地，列解码器从存储器控制器接收列地址且激活适当感测线。因此，通过激活一存取线及一感测线，可存取一存储器单元。通过激活一存取线及多根感测线，可存取一行存储器单元。
在存取之后，可由感测电路系统读取或感测存储器单元。感测电路系统可包括感测放大器663。举例来说，感测放大器663可将相关感测线的信号(例如，电压)与参考信号(未展示)作比较以便确定存储器单元的经存储状态。如果感测线具有高于参考电压的电压，那么感测放大器663可确定对应存储器单元中的所存储状态是逻辑1，且反之亦然。感测放大器663可包含各种晶体管或放大器以便检测及放大信号的差异，这可被称为锁存。感测放大器663可表示多个感测放大器的条带。存储器单元的检测到的逻辑状态可接着通过列解码器输出且输出到LIO 631。在各种例子中，感测放大器663-1、663-2、…、663-N可为第一条带感测放大器。感测放大器663-N+1、663-N+2、…、663-M可为第二条带感测放大器。感测放大器663-M+1、663-M+2、…、663-P可为第三条带感测放大器。
在各种实例中，晶片上晶片接合606可将感测放大器663的输出耦合到逻辑裸片的收发器665。收发器665可由逻辑裸片控制以致使感测放大器663的输出被提供到逻辑裸片的电路系统。举例来说，收发器665-1可致使从感测放大器663-1、663-2、…、663-N输出的信号被提供到在收发器665-1下游的逻辑裸片的电路系统。尽管展示单个收发器665-1，但收发器665-1可表示多个收发器，使得感测放大器663-1、663-2、…、663-N的输出中的每一者被并发提供到在逻辑裸片的多个收发器下游的电路系统。收发器665-2可致使感测放大器663-N-1、663-N+2、…、663-M的输出被提供到逻辑裸片的电路系统。收发器665-S可致使感测放大器663-M+1、663-M+2、…、663-P的输出被提供到逻辑裸片的电路系统。
存储器控制器(例如逻辑裸片的控制电路系统)可将信号发送到收发器665，以在芯片外选择性路由表示数据的信号(例如，路由到逻辑裸片“到DLA”)。所说明的从逻辑裸片的感测放大器663到收发器665的路径是存储器片块与对应逻辑裸片之间的电通路的表示。本公开的实施例可保留标准化存储器接口的功能性及制造，同时允许经由晶片上晶片接合606从存储器裸片到逻辑裸片的额外高带宽接口的功能性及制造。
在各种实例中，收发器665中的每一者可耦合到多个感测放大器663。举例来说，收发器665-1可耦合到感测放大器663-1、663-2、…、663-N。收发器665-2可耦合到感测放大器663-N+1、663-N+2、…、663-M。收发器665-S可耦合到感测放大器663-M+1、663-M+2、…、663-P。在各种例子中，收发器665中的每一者可引导多个信号。举例来说，收发器665-1可同时引导从感测放大器663-1、663-2、…、663-N提供的信号。收发器665-2可同时重新引导从感测放大器663-N+1、663-N+2、…、663-M提供的信号。收发器665-S可同时引导从感测放大器663-M+1、663-M+2、…、663-P提供的信号。
可通过激活相关存取线及感测线来设置或写入存储器单元。激活存取线会将对应行的存储器单元电连接到其相应数字线。通过在存取线被激活时控制相关感测线，存储器单元可被写入(逻辑值可被存储于存储器单元中)。列解码器可例如经由LIO 631接受要写入到存储器单元的数据。列解码器还可接受来自收发器665的要写入到存储器单元的数据。举例来说，列解码器可配置存储器单元存储信号，而逻辑裸片的存储器控制器配置收发器665将数据路由到感测放大器663。在各种实例中，将收发器665耦合到晶片上晶片接合606的线可称为逻辑裸片的LIO 662。将收发器665耦合到逻辑裸片的下游电路系统的线662也可称为逻辑裸片的LIO 662。
逻辑裸片的存储器控制器可致使表示数据的信号利用收发器665在逻辑裸片处从包含LIO 631的典型I/O路径接收。存储器裸片的存储器控制器还可致使表示数据的信号通过利用LIO 631、多路复用器661及全局IO 632的典型输入/输出路径来提供。
在一些存储器架构中，存取存储器单元可能会使经存储逻辑状态降级或损坏经存储逻辑状态，且重写或刷新操作可经执行以将原始逻辑状态返回到存储器单元。在DRAM中，例如，电容器可在感测操作期间部分或完全放电，从而破坏所存储逻辑状态。另外，激活单根存取线可致使行中的所有存储器单元都放电；因此，可能需要重写行中的若干或所有存储器单元。包含DRAM的一些存储器架构可随时间推移而丢失其所存储状态，除非它们由外部电源周期性刷新。举例来说，带电的电容器可随时间推移而通过泄漏电流变成不带电，从而导致所存储信息的丢失。逻辑状态可在重写操作期间被重写或在刷新操作期间被刷新。
存储器控制器可通过各种组件(例如，行解码器、列解码器及/或感测放大器663)控制存储器单元的操作(例如，读取、写入、重写、刷新，等等)。存储器控制器可产生行及列地址信号以便激活所期望存取线及感测线。存储器控制器还可产生并控制在存储器片块的操作期间使用的各种电压电势。举例来说，存储器控制器可操作选择组件以在感测期间隔离感测线(例如，将其与对应电容器隔离)。一般来说，本文中论述的所施加电压的振幅、形状或持续时间可被调整或改变且可针对用于操作存储器阵列的各种操作而不同。此外，可同时存取存储器片块内的一个、多个或所有存储器单元；例如，可在所有存储器单元或一群组存储器单元被设置到单个逻辑状态的复位操作期间同时存取存储器片块的多个或所有单元。
在各种例子中，收发器665可并发路由信号。举例来说，收发器665-1可与由收发器665-2、…及/或收发器665-S进行的信号路由并发地在感测放大器663-1、663-2、…、663-N与逻辑裸片之间路由信号。在各种实例中，收发器665-1可并发地在感测放大器663-1、663-2、…、663-2与逻辑裸片之间路由信号。
尽管未展示，但耦合到多个片块的逻辑裸片的收发器可并发地将信号从存储器裸片路由到逻辑裸片。举例来说，收发器665可与耦合到不同片块的其它收发器并发地路由数据。控制器可并发地激活多个片块的行以致使对应感测放大器(例如，包含感测放大器663)锁存信号。耦合到不同片块的收发器(例如，包含收发器665)可并发地将信号从多个片块的感测放大器路由到逻辑裸片。逻辑裸片可并发地经由收发器665从存储器裸片接收比可能经由GIO 632或GBUS输出的更大数量的信号。同样地，逻辑裸片可并发地经由收发器665将比经由GIO 632或GBUS可能实现的更大数量的信号提供到存储器裸片。收发器665还可与由经由晶片上晶片接合606耦合到不同存储体的收发器进行的数据路由并发地路由信号。
在各种实例中，存储器裸片可并发地将数据输出到GIO 632及收发器665。举例来说，存储器装置的存储器控制器可与由逻辑裸片的存储器控制器激活收发器665并发地激活LIO 631及GIO 632，以将信号输出到逻辑裸片并通过包括GIO 632的传统IO电路系统输出信号。
在各种例子中，信号可从存储器裸片的GBUS(例如图3中的GBUS 321)被提供到逻辑裸片。耦合到GBUS的逻辑裸片的收发器可经配置以将数据从存储器裸片路由到逻辑裸片。举例来说，逻辑裸片的收发器可经激活以将信号从GBUS路由到逻辑裸片。经配置以将信号从GBUS路由到逻辑裸片的收发器可与经配置以将信号从LIO 631路由到逻辑裸片的收发器不同。可提供两个独立路径用于将信号从存储器裸片路由到逻辑裸片。第一路径可起源于LIO 631，而第二路径可起源于存储器裸片的GBUS。第一路径可通过激活逻辑裸片的数个收发器来利用，而第二路径可通过激活逻辑裸片的不同数目个收发器来利用。在各种例子中，可并发地从LIO 631路由到逻辑裸片的信号的数量可大于可并发地从GBUS路由到逻辑裸片的信号的数量。
图6B说明根据本公开的数个实施例的LIO 631的电路图。在图6B中，与其中收发器665耦合到感测放大器663的图6A相比，收发器665耦合到LIO 631。
在图6B中，感测放大器663可输出多个信号。信号可被输出到多路复用器664。举例来说，感测放大器663-1、663-2、…、663-N可将第一多个信号输出到多路复用器664-1。感测放大器663-N+1、663-N+2、…、663-M可将第二多个信号输出到多路复用器664-2，而感测放大器663-M+1、663-M+2、…、663-P可将第S多个信号输出到多路复用器664-S。如本文中使用，“第S”表示变量使得“第S多个信号”表示可变多个信号。
多路复用器664中的每一者可将多个信号输出到LIO 631。举例来说，多路复用器664-1可输出第一多个信号的第一部分，多路复用器664-2可输出第二多个信号的第二部分，…、多路复用器664-S可输出第S多个信号的第S部分。
例如，收发器665可将存储器裸片的LIO 631的信号路由到逻辑裸片的LIO 662。在各种实例中，存储器装置可激活多路复用器661以通过存储器装置的传统IO电路系统将信号从LIO 631输出到GIO 632。逻辑裸片可与LIO 631及GIO 632的激活并发地激活收发器665以与数据经由存储器裸片的IO电路系统的输出并发地将数据输出到逻辑裸片。举例来说，存储器装置的存储器控制器可用于确定是否通过存储器装置的传统IO电路系统输出数据，而逻辑裸片的存储器控制器可用于确定是否将数据输出到接合到存储器裸片的逻辑裸片。
尽管展示单个收发器665，但多个收发器可用于将信号从存储器裸片的多根LIO路由到逻辑裸片。举例来说，第一收发器可耦合到存储器裸片的第一片块的第一LIO。第二收发器可耦合到存储器裸片的第二片块的第二LIO，等等。收发器中的每一者可通过将信号路由到逻辑裸片的LIO 662来将信号路由到逻辑裸片。收发器中的每一者可并发路由信号。
在各种例子中，收发器665可耦合到GIO 632，而不是感测放大器663或LIO 631。类似地，耦合到GIO的收发器可并发地将信号路由到逻辑裸片。
为了并发地将信号从存储器裸片路由到逻辑裸片，存储器控制器可激活多个片块的多个行。举例来说，存储器裸片的片块中的每一者的行可被并发激活以将数据从存储器裸片路由到逻辑裸片。在各种实例中，经由逻辑裸片的收发器将信号路由到逻辑裸片可包含将信号路由到逻辑裸片的处理资源。举例来说，数据可被路由到逻辑裸片的DLA或逻辑裸片的不同处理资源。
图7是根据本公开的一些实施例的对应于用于在存储器裸片与逻辑裸片之间路由信号的方法770的流程图。在操作771处，可经由耦合到存储器裸片的控制电路系统激活存储器裸片的行。存储器裸片可经由晶片上晶片接合来接合到逻辑裸片。
在操作772处，响应于激活行，可将第一多个信号锁存于存储器裸片的感测放大器条带中。感测放大器条带可由多个感测放大器组成。感测放大器条带可并入于存储器裸片的片块中。
在操作773处，可使用收发器将第二多个信号从感测放大器条带路由到逻辑裸片。第二多个信号可由感测放大器根据第一多个信号而产生。第二多个信号可被并发路由到逻辑裸片。
控制电路系统可配置多个多路复用器以使其将第二多个信号从感测放大器条带路由到存储器裸片的全局数据总线。第二多个信号可从感测放大器条带路由到全局数据总线以经由包括存储器裸片的存储器装置的IO电路系统输出第二多个信号。收发器可由逻辑裸片的控制电路系统配置以与将第二多个信号路由到全局数据总线并发地将第二多个信号路由到逻辑裸片。即，存储器裸片可将第二多个信号输出到逻辑裸片及存储器装置的IO电路系统。
第三多个信号可在感测放大器条带处从逻辑裸片接收以将第三多个信号存储于存储器裸片中。举例来说，逻辑裸片的处理资源可对从存储器裸片接收的数据执行多个操作。多个操作的输出可包括可从逻辑裸片路由到感测放大器条带以将第三多个信号存储于存储器裸片中的信号。在这方面，存储器裸片可用作存储器裸片的SRAM。在各种例子中，存储器裸片可用于从逻辑裸片输出数据。在不通过逻辑裸片所接合到的存储器裸片的情况下，逻辑裸片可不具有与存储器装置的多个引脚的直接连接。逻辑裸片可将表示数据的信号路由到存储器裸片。存储器裸片可接着将信号输出到存储器装置的IO电路系统以将数据从逻辑裸片输出到存储器装置的引脚。
响应于收发器路由第二多个信号，可不激活存储器裸片的全局数据总线。避免激活全局数据总线可防止信号从存储器裸片输出到存储器装置的IO电路系统。
第二多个信号可被路由到逻辑裸片的处理资源。第二多个信号可被路由到处理资源以允许处理资源执行多个操作。使用第二多个信号。
在各种例子中，可激活存储器裸片的多个行的存储器单元。可并发激活多个行。响应于激活多个行的存储器单元，可将第一多个信号锁存于多个感测放大器中。多个感测放大器可对应于多个行。举例来说，第一行可对应于第一多个感测放大器。第二行可对应于第二多个感测放大器，以此类推。多个行中的每一者可对应于存储器裸片的不同片块。
可将由多个感测放大器提供的第二多个信号多路复用到多个LIO线上。多个LIO线可包括LIO。经多路复用信号可经由耦合到多个LIO线中的每一者的相应收发器从对应LIO线路由到接合到存储器裸片的逻辑裸片。经多路复用信号可为已由多路复用器多路复用到多根线上的信号。在各种例子中，不同收发器可耦合到LIO线中的每一者，或收发器可经配置以并发地将多个信号从LIO线路由到逻辑裸片。
多个行中的每一者可对应于存储器裸片的多个片块中的不同片块。可激活类似地定位于存储器裸片的多个片块中的每一者中的多个行。激活多个行可包含激活第一片块的第一位置中的第一行、第二片块的第一位置中的第二行、第三片块的第一位置中的第三行等。
第二多个信号可在感测放大器条带的基础上被多路复用。举例来说，第一感测放大器条带可使用第一多路复用来多路复用，而第二感测放大器条带可使用第二多路复用来多路复用，等等。
可经由耦合到多个LIO线中的每一者的相应收发器将第三多个信号从逻辑裸片路由到对应LIO线。信号可从逻辑裸片路由到存储器裸片的LIO线以将数据存储于存储器裸片中。
在各种例子中，信号可从存储器裸片的LIO线路由到逻辑裸片的LIO。举例来说，经多路复用信号可从存储器裸片的对应LIO线路由到逻辑裸片的不同LIO线。
在各种实例中，存储器装置可包括存储器裸片、逻辑裸片及多个收发器。存储器裸片可包括多个感测放大器条带及控制电路系统。逻辑裸片可conde dot存储器裸片。
控制电路系统可激活存储器裸片的多个行。响应于激活多个行，控制电路系统可将多个信号锁存于感测放大器条带中。多个收发器可将第二多个信号从多个感测放大器条带路由到逻辑裸片。即，收发器可将信号直接从感测放大器条带的感测放大器路由到逻辑裸片。多个收发器可经配置以接收控制信号以将对应于第一多个信号的数据从多个感测放大器条带路由到逻辑裸片。即使收发器定位于存储器裸片上，控制信号也可从逻辑裸片接收。举例来说，多个收发器可经配置以从逻辑裸片的DLA接收控制信号。多个收发器可经配置以响应于控制信号的接收而并发地路由数据。举例来说，逻辑裸片可通过控制收发器来控制信号从存储器裸片到逻辑裸片的流动。来自多个收发器的每一收发器可进一步经配置以响应于控制信号的接收而与路由数据的其它部分并发地路由数据的不同部分。举例来说，第一收发器及第二收发器可并发地从逻辑裸片接收控制信号。第一收发器及第二收发器可并发地将信号路由到逻辑裸片。举例来说，第一收发器可与由第二收发器路由第二多个信号并发地路由第一多个信号。
如本文中使用，“数个”某物可指代此类事物中的一或多者。举例来说，数个存储器装置可指代一或多个存储器装置。“多个”某物意指两个或更多个。
尽管本文中已说明及描述特定实施例，所属领域的一般技术人员应了解，经计算以实现相同结果的布置可代替所展示的特定实施例。本公开希望涵盖本公开的各个实施例的调适或变化。应理解，上文描述已以说明方式而非限制方式进行。所属领域的技术人员将在检阅上文描述之后明白上述实施例的组合及本文中未明确描述的其它实施例。本公开的各个实施例的范围包含其中使用上述结构及方法的其它应用。因此，应参考所附权利要求书以及此权利要求书有权获得的等效物的全范围来确定本公开的各个实施例的范围。
在前述具体实施方式中，为了简化本公开，各种特征被一起分组于单个实施例中。本公开的方法不应被解译为反映本公开的所揭示实施例必须使用比每一权利要求中明确叙述的特征更多的特征的意图。确切来说，如所附权利要求书反映，发明标的物不具有单个揭示实施例的所有特征。因此，所附权利要求书特此并入到具体实施方式中，其中每个权利要求独立作为单独实施例。

Claims (20)

1.一种方法，其包括：
经由耦合到存储器裸片的控制电路系统激活所述存储器裸片的一行；
响应于激活所述行，将第一多个信号锁存于所述存储器裸片的感测放大器条带中；及
经由收发器将第二多个信号从所述感测放大器条带路由到经由晶片上晶片接合而接合到所述存储器裸片的逻辑裸片。
2.根据权利要求1所述的方法，其进一步包括：经由所述控制电路系统配置多个多路复用器以使其将所述第二多个信号从所述感测放大器条带路由到所述存储器裸片的全局数据总线。
3.根据权利要求2所述的方法，其进一步包括：配置所述收发器以使其与将所述第二多个信号路由到所述全局数据总线并发地将所述第二多个信号路由到所述逻辑裸片。
4.根据权利要求1至3中任一权利要求所述的方法，其进一步包括：在所述感测放大器条带处从所述逻辑裸片接收第三多个信号以将所述第三多个信号存储于所述存储器裸片中。
5.根据权利要求1至3中任一权利要求所述的方法，其进一步包括：响应于所述收发器路由所述第二多个信号，避免激活所述存储器裸片的全局数据总线。
6.根据权利要求1至3中任一权利要求所述的方法，其进一步包括：将所述第二多个信号路由到所述逻辑裸片的处理资源。
7.一种方法，其包括：
激活存储器裸片的多个行的存储器单元；
响应于激活所述多个行的存储器单元，将第一多个信号锁存于多个感测放大器中；
将由所述多个感测放大器提供的第二多个信号多路复用到多个局部输入/输出(LIO)线上；及
经由耦合到所述多个LIO线中的每一者的相应收发器将所述第二多个经多路复用信号中的经多路复用信号从对应LIO线路由到经由晶片上晶片接合而接合到所述存储器裸片的逻辑裸片。
8.根据权利要求7所述的方法，其进一步包括：激活所述多个行，所述多个行中的每一者对应于所述存储器裸片的多个片块中的不同片块。
9.根据权利要求7所述的方法，其进一步包括：激活类似地定位于所述存储器裸片的多个片块中的每一者中的所述多个行。
10.根据权利要求7所述的方法，其进一步包括：将所述第一多个信号锁存于包括所述多个感测放大器的感测放大器条带中。
11.根据权利要求10所述的方法，其进一步包括：在感测放大器条带的基础上多路复用所述第二多个信号。
12.根据权利要求10所述的方法，其进一步包括：经由耦合到所述多个LIO线中的每一者的所述相应收发器接收从所述逻辑裸片到所述对应LIO线的第三多个信号。
13.根据权利要求7至12中任一权利要求所述的方法，其进一步包括：并发激活所述多个行。
14.根据权利要求7至12中任一权利要求所述的方法，其进一步包括：将所述经多路复用信号从所述存储器裸片的所述对应LIO线路由到所述裸片的不同LIO线。
15.一种设备，其包括：
存储器裸片；
逻辑裸片，其经由晶片上晶片接合而接合到所述存储器裸片；
多个收发器，其耦合到所述存储器裸片的多个感测放大器条带；及
控制电路系统，其耦合到所述存储器裸片且经配置以：
激活所述存储器裸片的多个行；及
响应于激活所述多个行，将多个信号锁存于所述感测放大器条带中；
其中所述多个收发器经配置以将第二多个信号从所述多个感测放大器条带路由到所述逻辑裸片。
16.根据权利要求15所述的设备，其中所述多个收发器经配置以接收控制信号以将对应于所述第一多个信号的所述数据从所述多个感测放大器条带路由到所述逻辑裸片。
17.根据权利要求16所述的设备，其中所述多个收发器经配置以从所述逻辑裸片接收控制信号。
18.根据权利要求17所述的设备，其中所述多个收发器经配置以从所述逻辑裸片的深度学习加速器(DLA)接收所述控制信号。
19.根据权利要求18所述的设备，其中所述多个收发器经配置以响应于所述控制信号的接收而并发地路由所述数据。
20.根据权利要求18所述的设备，其中来自所述多个收发器的每一收发器经配置以响应于所述控制信号的接收而与路由所述数据的其它部分并发地路由所述数据的不同部分。
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