CN1179404C - 基板在晶片上的封装方法 - Google Patents

基板在晶片上的封装方法 Download PDF

Info

Publication number
CN1179404C
CN1179404C CNB011422440A CN01142244A CN1179404C CN 1179404 C CN1179404 C CN 1179404C CN B011422440 A CNB011422440 A CN B011422440A CN 01142244 A CN01142244 A CN 01142244A CN 1179404 C CN1179404 C CN 1179404C
Authority
CN
China
Prior art keywords
wafer
substrate
solvent
packing
dry film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB011422440A
Other languages
English (en)
Other versions
CN1405869A (zh
Inventor
�������ֿ�
林俊宏
钟卓良
黄国樑
李耀荣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipmos Technologies Inc
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to CNB011422440A priority Critical patent/CN1179404C/zh
Publication of CN1405869A publication Critical patent/CN1405869A/zh
Application granted granted Critical
Publication of CN1179404C publication Critical patent/CN1179404C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种基板在晶片上的封装方法,是在基板的上表面披覆一层两阶段特性的具有溶剂的热固性混合物,然后,加热基板,以除去溶剂,使热固性混合物形成无溶剂的粘着干膜,避免在粘晶时覆盖晶片的焊垫,并有利于基板在晶片上封装的加工。

Description

基板在晶片上的封装方法
技术领域
本发明是有关于一种基板在晶片上(Substrate-On-Chip,SOC)的封装方法,特别是有关于一种基板在晶片上的封装方法中的粘晶步骤。
背景技术
众所周知,所谓的「基板在晶片上的封装」即为Substrate-On-Chip封装,简称为SOC封装,属于一种常用的半导体封装结构,其是以一具有窗口的电路基板粘贴于一晶片,并以多数个金属焊线穿过该窗口,连接电路基板与晶片,该电路基板并形成有多数个矩阵排列的焊球。
在美国专利案第6,190,943号「晶片尺寸封装方法」中,揭示一种SOC封装结构及其封装方法,如图1所示,该SOC封装结构20是包含有一基板22、一晶片24及多数个焊球44,该基板22是具有一粘固晶片24的上表面30、一用以焊接焊球44的下表面38以及贯穿上表面30与下表面38的通孔34,其中晶片24是以热塑性粘着层28粘固于基板22的上表面30,由于基板22的通孔34是裸露在晶片24的主动面26(active surface)中间的焊垫36,使得金属焊线32可穿过通孔34,以电性连接晶片24的焊垫36与基板22的导接垫41,该导接垫41是由在基板22下表面38的导电层40所构成,并在通孔34处以及晶片24的周边形成有封胶层42,其是为一种绝缘性及热固性的环氧树脂硅氧填充材料。
上述美国专利案的封装方法,如图2所示,包含以下步骤:
(a)提供一基板22,在该基板22的上表面30具有至少一粘晶区域302,其包含上述的通孔34;
(b)将液态的热塑性粘着层28网版印刷(stenciling)于粘晶区域302;
(c)粘贴晶片24至粘晶区域302,使得晶片24的主动面26接触热塑性粘着层28,且在主动面26的焊垫36的位置对应于通孔34;
(d)在预定的温度、压力及时间之下,施压加热基板22与晶片24;
(e)以打线(wire-bonding)将金属焊线32经由通孔34连接基板22的导接垫41与晶片24的焊垫36;
(f)提供一封胶层42于该通孔34及晶片24的周边;
(g)在基板22的下表面38接植多数个呈矩阵排列的焊球44。
通过上述的步骤以制备SOC封装结构20,其主要缺陷在于:
1、在(b)步骤中的热塑性粘着层28是为一种无溶剂、弹性且半透明的硅橡胶(silicone rubber),由于未粘合前的热塑性粘着层28是呈液态,在(d)步骤中的施压加热容易使得液态热塑性粘着层28溢流,并覆盖晶片24的焊垫36,而导致封装失败,故这种基板在晶片上(SOC)的封装方法的优良率较低;
2、此外,另一不便之处为:在(b)步骤印刷上液态热塑性粘着层28之后,无法将多个基板22堆叠,以供搬运或储放,必须尽速粘固上晶片24,否则基板22会受到污染,以及基板22间会不当粘着,造成加工的困难。
发明内容
本发明的主要目的在于提供一种基板在晶片上的封装方法,利用一种两阶段特性(two stage)的具有溶剂的热固性混合物,以粘贴晶片,在印刷于基板及干燥后,在基板表面形成一不具粘性的热固性粘着干膜,使得在加热施压时,热固性粘着干膜不易覆盖晶片的焊垫,达到增加SOC封装的优良率的目的。
本发明的另一目的在于提供一种基板在晶片上的封装方法,利用一种两阶段特性(two stage)的具有溶剂的热固性混合物粘贴晶片,在印刷于基板及干燥后,在基板表面形成一不具粘性的热固性粘着干膜,使得具有热固性粘着干膜的基板可堆叠搬运或储放,达到有利于后续SOC封装的加工的目的。
本发明的目的是这样实现的:一种基板在晶片上的封装方法,其特征是:它依次包括如下步骤:
(a)提供一基板,该基板具有一上表面、一下表面及连通上下表面的通孔;
(b)在该基板的上表面形成一层两阶段特性的具有溶剂的热固性混合物;
(c)去除溶剂,使该热固性混合物形成无溶剂的粘着干膜;
(d)提供至少一晶片,该晶片具有一主动面及多数个在主动面的焊垫,其中该晶片的主动面是接触该基板的上表面的粘着干膜,该晶片的焊垫的位置对应于该基板的通孔;
(e)施压加热基板与晶片,使所述无溶剂的粘着干膜粘合晶片与基板;
(f)经由通孔打线电性连接晶片的焊垫至基板;
(g)形成一封胶层于该基板的通孔处。
该步骤(b)是以网版印刷方法形成一层热固性混合物。该步骤(b)是以印刷、喷涂、旋涂或浸染方法形成一层热固性混合物。该步骤(g)之后,另包含有接植多数个焊球于该基板的下表面。该步骤(g)是以压模方式形成该封胶层。该封胶层是密封晶片。该步骤(c)是以加热或真空干燥方式去除溶剂。该步骤(e)的施压加热的温度是高于该步骤(c)去除溶剂的温度。
另一种基板在晶片上的封装方法,其特征是:它依次包括如下步骤:
(a)提供一基板,该基板具有一上表面、一下表面及连通上下表面的通孔;
(b)在基板的上表面形成一层两阶段特性的具有溶剂的热固性混合物;
(c)去除溶剂,使热固性混合物形成无溶剂的粘着干膜;
(d)提供至少一晶片,该晶片具有一主动面及多数个在主动面的焊垫,该晶片的主动面是接触该基板的上表面的粘着干膜,该晶片的焊垫的位置对应于基板的通孔;
(e)施压加热基板与晶片,使所述无溶剂的粘着干膜粘合晶片与基板;
(f)经由通孔打线电性连接晶片的焊垫至基板;
(g)压模形成一封胶层于该基板的通孔处;
(h)加热固化该封胶层与无溶剂的粘着干膜。
下面结合较佳实施例和附图进一步说明。
附图说明
图1是传统基板在晶片上封装结构的剖面示意图;
图2是传统基板在晶片上封装结构的制造流程示意图;
图3是本发明的基板在晶片上封装方法的制造流程示意图。
具体实施方式
参阅图3所示,本发明的基板在晶片上(SOC)的封装方法依次包括如下步骤:
首先提供一基板110,该基板110具有一上表面111、一下表面112及连通上下表面111、112的通孔113,在本实施例中,基板110是一种印刷电路板,如玻璃纤维强化树脂,在基板110的下表面112形成有一电路图案层(circuit pattern)(图未示),如导接垫、焊球垫以及连接导接垫与焊球垫的金属线路;
之后,在基板110的上表面111网版印刷上一层两阶段特性(two stage)的具有溶剂的热固性混合物130(thermosetting mixture),该两阶段粘着的热固性混合物130是包含有热固性树脂,如聚亚酰胺(polyimide)、聚喹啉(polyquinolin)或苯环丁烯(benzocyclobutene),以及能够溶解上述热固性树脂的溶剂,如丁内脂(butyrolactone)与环戊酮(cyclopentanone)的混合溶剂或是1,3,5-三甲基苯(mesitylene),由于该两阶段的热固性混合物130在涂施时。是具有A阶段A的特性呈液态,使得易于涂施附着,故除了网版印刷方法之外,还可以印刷(painting)、喷涂(spraying)、旋涂(spinning)或浸染(dipping)等方式,形成于基板110的上表面111;然后,加热基板110至一适当温度,约90-150℃,以除去溶剂,使热固性混合物130形成无溶剂的粘着干膜131,较佳地,另执行一真空干燥加热,以完全去除溶剂,此时,在基板110的粘着干膜131是具有B阶段的特性,即在室温下成为不具有粘性(Tg为40℃)的胶膜,可供堆叠搬运或储放,有利于后续SOC封装的加工;
接着,提供至少一晶片120,该晶片120具有一主动面121(active surface)及多数个在主动面121的焊垫122,其中晶片120的主动面121是接触基板110的上表面111的粘着干膜131,且晶片120的焊垫122的位置对应于基板110的通孔113,在本实施例中,焊垫122是位于晶片120主动面121的中间部位;
再后,施压加热基板110与晶片120,约在180℃,并在适当压力下维持数秒钟之久,使得上述无溶剂的粘着干膜131能机械性粘合晶片120与基板110,但不需要完全固化,由于在热粘合晶片120与基板110的步骤时,粘着干膜131并不具有高流动性,不会有受挤压流至晶片120的焊垫122的现象;
尔后,经由通孔113以金属焊线140打线电性连接晶片120的焊垫122至基板110;
最后,形成一热固性封胶材150于该基板110的通孔113处,在本实施例中,其是以压模(molding)方式形成该封胶材150,该封胶材150并密封晶片120,较佳地,在压模过程后随同封胶材150的加热固化约要200℃维持数小时,而固化该粘着干膜131,由于压模压力可排除原本可能潜藏在未固化前粘着干膜131的空隙,以增进封装的优良率,如有需要,并接植多数个焊球160于基板110的下表面120,并在切割分离后,构成多数个SOC封装结构100。
因此,本发明是运用两阶段特性的具有溶剂的热固性混合物130,于基板在晶片上(SOC)的封装方法中,作为基板110对晶片120的粘合材料,避免了液态粘胶覆盖晶片120的焊垫122的缺点,以增加SOC封装的优良率,同时已形成热固性粘着干膜131的基板110,可供堆叠搬运或储放,有利于后续SOC封装的加工。
以上所述为较佳的实施例,任何熟知此项技艺者,在不脱离本发明的精神和范围内所作的任何变化与修改,均属于本发明的保护范围。

Claims (7)

1、一种基板在晶片上的封装方法,其特征是:它依次包括如下步骤:
(a)提供一基板,该基板具有一上表面、一下表面及连通上下表面的通孔;
(b)在基板的上表面形成一层两阶段特性的具有溶剂的热固性混合物;
(c)去除溶剂,使热固性混合物形成无溶剂的粘着干膜;
(d)提供至少一晶片,该晶片具有一主动面及多数个在主动面的焊垫,该晶片的主动面是接触该基板的上表面的粘着干膜,该晶片的焊垫的位置对应于基板的通孔;
(e)施压加热基板与晶片,使所述无溶剂的粘着干膜粘合晶片与基板;
(f)经由通孔打线电性连接晶片的焊垫至基板;
(g)压模形成一封胶层于该基板的通孔处,同时加热固化该封胶层与无溶剂的粘着干膜。
2、根据权利要求1所述的基板在晶片上的封装方法,其特征是:该步骤(b)是以网版印刷方法形成一层热固性混合物。
3、根据权利要求1所述的基板在晶片上的封装方法,其特征是:该步骤(b)是以印刷、喷涂、旋涂或浸染方法形成一层热固性混合物。
4、根据权利要求1所述的基板在晶片上的封装方法,其特征是:该步骤(h)之后,另包含有接植多数个焊球于基板的下表面。
5、根据权利要求1所述的基板在晶片上的封装方法,其特征是:该封胶层是密封晶片。
6、根据权利要求1所述的基板在晶片上的封装方法,其特征是:该步骤(c)是以加热或真空干燥方式去除溶剂。
7、根据权利要求1所述的基板在晶片上的封装方法,其特征是:该步骤(h)的加热固化的温度是高于步骤(c)去除溶剂的温度。
CNB011422440A 2001-09-18 2001-09-18 基板在晶片上的封装方法 Expired - Fee Related CN1179404C (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB011422440A CN1179404C (zh) 2001-09-18 2001-09-18 基板在晶片上的封装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB011422440A CN1179404C (zh) 2001-09-18 2001-09-18 基板在晶片上的封装方法

Publications (2)

Publication Number Publication Date
CN1405869A CN1405869A (zh) 2003-03-26
CN1179404C true CN1179404C (zh) 2004-12-08

Family

ID=4676717

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB011422440A Expired - Fee Related CN1179404C (zh) 2001-09-18 2001-09-18 基板在晶片上的封装方法

Country Status (1)

Country Link
CN (1) CN1179404C (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101546735B (zh) * 2005-08-17 2011-08-17 南茂科技股份有限公司 晶穴朝下晶片封装构造及其制造方法
CN100463132C (zh) * 2006-07-31 2009-02-18 南茂科技股份有限公司 晶片封装结构及其制造方法
CN101477956B (zh) * 2008-01-04 2012-05-16 南茂科技股份有限公司 小片重新配置的封装结构及封装方法
CN101609824B (zh) * 2008-06-18 2011-01-12 力成科技股份有限公司 半导体封装的通用型基板及半导体封装构造

Also Published As

Publication number Publication date
CN1405869A (zh) 2003-03-26

Similar Documents

Publication Publication Date Title
TW497236B (en) A soc packaging process
US7037756B1 (en) Stacked microelectronic devices and methods of fabricating same
JP2662190B2 (ja) 電子素子アセンブリおよび再加工方法
CN1918702A (zh) 采用多孔载体的管芯包封
US20020008316A1 (en) Semiconductor device having heat spreader attached thereto and method of manufacturing the same
CN1575096A (zh) 电子电路装置及其制造方法
TW582078B (en) Packaging process for improving effective die-bonding area
CN1945805A (zh) 半导体封装方法以及用于半导体封装的载体
CN1774801A (zh) 局部放电减少的绝缘功率半导体模块及制造方法
CN101030546A (zh) 电容安装方法
JP2000340712A (ja) ポリマ補強カラム・グリッド・アレイ
CN1179404C (zh) 基板在晶片上的封装方法
JP2617402B2 (ja) 半導体装置、電子回路装置、およびそれらの製造方法
CN1191628A (zh) 载体、半导体器件及其安装方法
JP2011060892A (ja) 電子装置、電子装置の製造方法
CN101043010A (zh) 无胶带黏晶方式的集成电路封装方法
JPH0425142A (ja) 半導体素子の実装方法
JPH05166879A (ja) Ic実装方法
JPS6244851B2 (zh)
TW511258B (en) Substrate-on-chip packaging process
CN1617316A (zh) 增进有效黏晶面积的封装制程及实施该封装制程的b阶膜层
CN1298031C (zh) 增进有效黏晶面积的封装制程
KR20080105636A (ko) 반도체 패키징 구조 및 패키징 방법
TW541671B (en) Semiconductor chip package method
JP2001110847A (ja) 電子部品の保持治具、保持方法および電子部品の製造方法

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20041208

Termination date: 20200918