TW511258B - Substrate-on-chip packaging process - Google Patents

Substrate-on-chip packaging process Download PDF

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Publication number
TW511258B
TW511258B TW90123399A TW90123399A TW511258B TW 511258 B TW511258 B TW 511258B TW 90123399 A TW90123399 A TW 90123399A TW 90123399 A TW90123399 A TW 90123399A TW 511258 B TW511258 B TW 511258B
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Taiwan
Prior art keywords
substrate
wafer
solvent
patent application
scope
Prior art date
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TW90123399A
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Chinese (zh)
Inventor
Chung-Hung Lin
Juo-Liang Jung
Jesse Huang
Yau-Rung Li
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Chipmos Technologies Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A SOC (substrate-on-chip) packaging process is disclosed. A layer of two stage thermosetting mixture with solvent is coating on an upside of a substrate. Thereafter, the substrate is heated for removing solvent so that the two stage thermosetting mixture becomes a dry adhesive film without solvent. Thus, the bonding pads of the chip are not covered by the dry adhesive film and a better operating flexibility is obtained in the SOC packaging process. Preferably, the dry adhesive film is cured during molding.

Description

511258511258

【發明領域】 本發明係有關於一種基板在晶片上 (sUbStrate-0n-chiP,soc)之封裝過程,特別係有關於 種基板在晶片上之封裝過程中黏晶步驟。 【先前技術】 所謂的「SOC封裝」即為Substrate—0n〜Chii)封裝〔美 板在晶片上〕t簡稱,屬於一種常用之半導體封裝結構; 其係以一具有窗口之電路基板黏貼於一晶片,並以複數個 金屬焊線穿過該窗口連接電路基板與晶片,該電路基板並 形成有複數個矩陣排列之焊球,在美國專利孝第 6, 1 90, 943號「晶片尺寸封裝方法」中揭示一種s〇c封裝結 構及其封裝方法,如第1圖所示,該s〇c封裝結構2〇係包含 有一基板22、一晶片24及複數個焊球44,該基板22係具有 一用以黏固晶片24之上表面30、一用以焊接焊球44之下表 面38以及貫穿上表面3〇與下表面38之通孔34,其中晶片24 係以熱塑性黏著層28黏固於基板22之上表面3〇,由於基板 22之通孔34係裸露在晶片24之主動面26〔active surf ace〕中間之焊墊36,使得金屬焊線32可穿過通孔 34 ’以電性連接晶片24之焊墊36與基板22之導接墊41,該 導接墊41係由在基板22下表面38之導電層40所構成,並在 通孔34處以及晶片24之周邊形成有封膠材42,其係為一種 絕緣性及熱固性之環氧樹脂矽氧填充材料。 在美國專利案第6, 1 90, 943號「晶片尺寸封裝方法」 中:關於上述SOC封裝結構20之封裝方法係如第2圖所示, & f α T步驟:a)提供一基板22,在該基板22之上表面30[Field of the Invention] The present invention relates to a packaging process of a substrate on a wafer (sUbStrate-0n-chiP, soc), and particularly relates to a die bonding step in the packaging process of a substrate on a wafer. [Previous technology] The so-called "SOC package" is Substrate-0n ~ Chii) package [US board on the chip] t for short, belongs to a commonly used semiconductor packaging structure; it is a circuit substrate with a window attached to a chip And a plurality of metal bonding wires are passed through the window to connect the circuit substrate and the wafer, and the circuit substrate is formed with a plurality of matrix-arranged solder balls. In the US Patent No. 6, 1 90, 943 "wafer size packaging method" A SOC packaging structure and a packaging method are disclosed therein. As shown in FIG. 1, the SOC packaging structure 20 includes a substrate 22, a wafer 24, and a plurality of solder balls 44. The substrate 22 has a It is used to fix the upper surface 30 of the wafer 24, a lower surface 38 for solder balls 44 and a through hole 34 penetrating the upper surface 30 and the lower surface 38. The wafer 24 is adhered to the substrate with a thermoplastic adhesive layer 28 The upper surface 30 of 22, because the through hole 34 of the substrate 22 is the pad 36 exposed in the middle of the active surface 26 (active surf ace) of the wafer 24, so that the metal bonding wire 32 can pass through the through hole 34 'to be electrically connected The bonding pad 36 of the wafer 24 and the guide of the substrate 22 The contact pad 41 is composed of a conductive layer 40 on the lower surface 38 of the substrate 22, and a sealing material 42 is formed at the through hole 34 and the periphery of the wafer 24, which is an insulation and thermosetting property. Epoxy epoxy silicone filling material. In U.S. Patent No. 6, 1 90, 943 "Chip Size Packaging Method": The packaging method for the above-mentioned SOC package structure 20 is shown in Fig. 2, & f α T step: a) Provide a substrate 22 , 上 30 30 on the substrate 22

511258511258

具有至少一黏晶區域3 Ο 2,其包含上述之通孔3 4 ; b )將液 態之熱塑性黏著層28網版印刷〔s t enc i 1 i ng〕於黏晶區域 302 ; c)黏貼晶片24至黏晶區域302,使得晶片24之主動面 26接觸熱塑性黏著層28,且在主動面26之焊墊36係位置對 應於通孔34 ; d)在預定之溫度、壓力及時間之下,施壓加 熱基板22與晶片24 ; e)以打線〔wi re-bonding〕將金屬焊 線32經由通孔34連接基板22之導接墊41與晶片24之焊墊 36 ;f)提供一封膠材42於該通孔34及晶片24之周邊;g)在 基板22之下表面38接植複數個呈矩陣排列之焊球44。藉由 上述之步驟以製備S0C封裝結構20,其中在b)步驟中之9熱 塑性黏著層28係為一種無溶劑、彈性且半透明之矽橡膠 〔silicone rubber〕,由於未黏合前的熱塑性黏著層μ 係呈液態,在d)步驟中的施壓加熱容易使得液態熱塑性黏 著層28溢流並覆蓋晶片24之焊墊36,而導致封裝失敗,故 這種基板在晶片上(S0C)之封裝方法良率較低,此外,另 一不便之處為在b)步驟印刷上液態熱塑性黏著層28之後, 無法將多個基板2 2堆疊以供搬運或儲放,必須儘速黏固上 晶片24,否則基板22會受到污染以及基板22間會不當黏 著,造成加工之困難。 【發明目的及概要】 本發明之主要目的在於提供一種基板在晶片上之封裝 過程’利用一種兩階段特性〔t w 〇 s t a g e〕具有溶劑之熱 固性混合物,以黏貼晶片,在印刷於基板及乾燥後在基板 表面形成一不具黏性之熱固性黏著乾膜,使得在加熱施壓 時熱固性黏著乾膜不易覆蓋晶片之焊墊,以增加S0C封裝 MM 9012^00 五、發明說明(3) 良率。 曰 修正 本發 過程,利 固性混合 面形成一 著乾膜之 加工。 本發 過程,利 固性混合 兩流動性 壓模之壓 封裝良率 為了 裝過程, 一下表面 網版印刷 性混合物 之黏者乾 及複數個 之上表面 施壓加熱 合晶片與 至基板; 處,如有 明之次一目 用一種兩階 物以黏貼晶 不具黏性之 基板可堆叠 明之再一目 用一種兩階 物’在乾燥 ’在壓模之 力排除原本 〇 達到上述之 其步驟為: 及連通上下 一層兩階段 ;然後,去 膜;接著, 在主動面之 且晶片之焊 基板與晶片 基板;之後 最後,以壓 需要,並接 的在於提供一種基板在晶片上之封裝 段特性〔two stage〕具有溶劑之熱 片’在印刷於基板及乾燥後在基板表-熱固性黏著乾膜,使得具有熱固性黏 搬運或儲放,有利於後續S0C封裝之 的在於提供一種基板在晶片上之封裝 段特性〔two stage〕具有溶劑之熱 後形成黏著乾膜,以黏固晶片並避免省 過程同時固化該熱固性混合物,利用 可能潛藏在黏著乾膜之空隙,以增進 S 提 表 特 除 提 焊 墊 的, 供一 面之 性〔 溶劑 供至 墊, 係位 使上 經由 方法 複數 依本發明之基板在晶片上之封 基板’该基板具有一上表面、 通孔;之後,在基板之上表面 two stage〕具有溶劑之熱固 ,使熱固性混合物形成無溶劑 少一晶片,晶片具有一主動面 其中晶片之主動面係接觸基板 置對應於基板之通孔;爾後, 述無溶劑之黏著乾膜固化並結 通孔打線電性連接晶片之焊墊 形成一封膠材於該基板之通孔 個焊球於基te夕丁急品,丨、,德Has at least one sticky crystal region 3 02, which includes the above-mentioned through holes 3 4; b) a liquid thermoplastic adhesive layer 28 is screen-printed [st enc i 1 i ng] on the sticky crystal region 302; c) the wafer 24 is stuck To the die attach area 302, so that the active surface 26 of the wafer 24 contacts the thermoplastic adhesive layer 28, and the position of the pad 36 on the active surface 26 corresponds to the through hole 34; d) at a predetermined temperature, pressure and time, apply Press and heat the substrate 22 and the wafer 24; e) Wi-bonding the metal bonding wire 32 through the through hole 34 to connect the lead pad 41 of the substrate 22 and the pad 36 of the wafer 24; f) provide an adhesive material 42 around the through hole 34 and the wafer 24; g) a plurality of solder balls 44 arranged in a matrix are planted on the lower surface 38 of the substrate 22. Through the above steps to prepare the SOC package structure 20, the 9 thermoplastic adhesive layer 28 in the step b) is a solvent-free, elastic and translucent silicone rubber. Because the thermoplastic adhesive layer is not bonded before, μ is in a liquid state, and the pressure heating in step d) can easily cause the liquid thermoplastic adhesive layer 28 to overflow and cover the pads 36 of the wafer 24, resulting in packaging failure. Therefore, this substrate packaging method on a wafer (S0C) The yield is low. In addition, another inconvenience is that after the liquid thermoplastic adhesive layer 28 is printed on step b), multiple substrates 2 cannot be stacked for transportation or storage. The upper wafer 24 must be adhered as soon as possible. Otherwise, the substrates 22 will be contaminated and the substrates 22 will be improperly adhered to each other, causing processing difficulties. [Objective and Summary of the Invention] The main object of the present invention is to provide a packaging process of a substrate on a wafer, which utilizes a two-stage characteristic [tw stage] thermosetting mixture with a solvent to adhere the wafer, and is printed on the substrate and dried. A non-adhesive thermosetting adhesive dry film is formed on the surface of the substrate, which makes it difficult for the thermosetting adhesive dry film to cover the pads of the wafer when heating and pressure is applied, so as to increase the S0C package MM 9012 ^ 00 5. Description of the invention (3) Yield. The process of amending the hair, forming a dry film on the solid mixing surface. In this process, the yield of the compression package of the solid mixed two fluidity stamper is the assembly process. The lower surface of the screen printing mixture and the upper surface are pressed to heat the wafer and the substrate; If there is a second order, use a two-stage object to stick the crystals with non-sticky substrates. You can stack it again. Use a two-stage object to 'dry' in the mold to eliminate the original one. The steps to achieve the above are: One layer and two stages; then, removing the film; then, the solder substrate and the wafer substrate of the wafer on the active side; and finally, in order to meet the demand, the connection is to provide a package stage characteristic of the substrate on the wafer. Solvent hot sheet 'is printed on the substrate and dried on the surface of the substrate-thermosetting adhesive dry film, so that it has thermosetting adhesive handling or storage, which is beneficial to the subsequent S0C packaging is to provide a package segment characteristics of the substrate on the wafer (two stage] After the heat of the solvent is formed, an adhesive dry film is formed to fix the wafer and avoid the process of curing the thermosetting mixture at the same time. Use the gap that may be hidden in the dry film to improve the performance of the S pad and remove the pad. The solvent is supplied to the pad. The mounting method is to seal the substrate on the wafer according to the method of the present invention. 'The substrate has an upper surface and a through hole; then, two stages on the upper surface of the substrate] have a thermosetting solvent, so that the thermosetting mixture forms a solvent-free wafer, and the wafer has an active surface, wherein the active surface of the wafer contacts the substrate The through hole corresponding to the substrate is set; thereafter, the solvent-free adhesive dry film is cured and the through-holes are wired to electrically connect the solder pads of the wafer to form an adhesive material in the through holes of the substrate. A solder ball is formed on the substrate. Quality

成SOC封裝結構。 【發明詳細說明】 =f閱所附圖式,本發明將列舉以下之實施例說明: 片上(snr、發明i之一具體實施例’如第3圖所示,基板在晶 柘 、^)之/裝過裎之步驟主要包含有:「提供基 「i ^,形成兩階段特性具有溶劑之熱固性混合物」、Into SOC package structure. [Detailed description of the invention] = f. As shown in the attached drawings, the present invention will enumerate the following embodiment descriptions: On-chip (snr, one of the specific embodiments of the invention i 'as shown in Figure 3, the substrate in the crystal, ^) The step of loading / packing mainly includes: "providing the base" i ^, forming a two-stage characteristic thermosetting mixture with a solvent ",

’于、’合劑」、「提供晶片於基板」、「電性連接晶片I =^「形成封膠材」及「固化該封膠材與無溶劑之卖 固性混合物」,其詳述如下:"Yu," Mixture "," Providing wafers to substrates "," Electrically connecting wafers I = ^ "Forming sealing compound" and "Curing the sealing compound and the solvent-free sales solid mixture", the details are as follows:

一如第3圖所示,首先提供一基板no,該基板110具有 一上表面111、一下表面112及連通上下表面m、112之通 孔113 ’在本實施例中,基板丨丨〇係為一種印刷電路板〔如 FR-4、FR-5或BT等玻璃纖維強化樹脂〕,在基板丨1()之下 表面112形成有一電路圖案層〔circuU pattern〕〔圖未As shown in FIG. 3, a substrate no is first provided, and the substrate 110 has an upper surface 111, a lower surface 112, and a through hole 113 'that communicates with the upper and lower surfaces m and 112. In this embodiment, the substrate is A printed circuit board (such as glass fiber-reinforced resin such as FR-4, FR-5, or BT). A circuit pattern layer [circuU pattern] is formed on the lower surface 112 of the substrate 1 ().

繪出〕,如導接墊、焊球墊以及連接導接墊與焊球墊之金 屬線路;之後,在基板11 0之上表面1 1 1網版印刷上一層兩 階段特性〔two stage〕具有溶劑〔solvent〕之熱固性混 合物130〔thermosetting mixture〕,該兩階段黏著之熱 固性混合物1 3 0係包含有熱固性樹脂,如聚亞醯胺 〔polyimide〕、聚喳啉〔polyquinolin〕或苯環丁烯 〔benzocyc 1 obutene〕,以及能夠溶解上述熱固性樹脂之 溶劑,如丁内脂〔bu tyro lactone〕與環戊酮 〔cyclopentanone〕之混合溶劑或是1,3,5-三甲基笨 〔m e s i t y 1 e n e〕,由該兩階段之熱固性混合物1 3 0在塗施 時係具有A階段〔A-stage〕之特性,其呈液態,使得易於[Drawing], such as lead pads, solder ball pads, and metal circuits connecting the lead pads and the solder ball pads; after that, a two-stage characteristic is printed on the top surface of the substrate 1 1 1 1 screen printing. Solvent [thermosetting mixture] 130 [thermosetting mixture], the two-stage adhesive thermosetting mixture 130 contains a thermosetting resin, such as polyimide, polyquinolin or phenylcyclobutene [ benzocyc 1 obutene], and solvents capable of dissolving the above thermosetting resins, such as a mixed solvent of butyrolactone (butyro lactone) and cyclopentanone (cyclopentanone) or 1,3,5-trimethylbenzyl [mesity 1 ene] The two-stage thermosetting mixture 130 has the characteristics of A-stage [A-stage] at the time of application, which is liquid, which makes it easy

第8頁 511258 修正 案號 90123399 五、發明說明(5) 塗施附著,故除了網版印刷方法之外,更可以印刷 · 〔painting〕、噴塗〔spraying〕、旋塗〔spinning〕或 浸染〔dipping〕等方式形成於基板11〇之上表面^!;然 後’加熱基板11 0至一適當溫度〔約攝氏9 0〜丨5 〇 t〕,以 除去溶劑’使熱固性混合物1 30形成無溶劑之黏著乾膜 131,較佳地,另執行一真空乾燥加熱,以完全去除溶 劑’此時’在基板1 1 〇之黏著乾膜1 3 1係具有β階段 〔B-stage〕之特性,即在室溫下成為不具有黏性〔Tg ^ 4 0 °C〕之膠膜,Tg係為玻璃態轉化溫度〔glass transition temperature〕,當該黏著乾膜131高於其玻 璃態轉化溫度,將由剛性變得柔軟且具有黏著性,故該具 有黏著乾膜131之基板11〇在常溫下係可供堆疊搬運咬儲 放,有利於後續S0C封裝之加工;接著,提/至;Page 8 511258 Amendment No. 90123399 V. Description of the invention (5) In addition to the screen printing method, it can be printed · [painting], spraying [spinning], or spinning [dipping] ] And other methods are formed on the top surface of the substrate 11! ^; Then 'heat the substrate 110 to an appropriate temperature [approximately 90 ° C ~ 5 ° C] to remove the solvent' to make the thermosetting mixture 1 30 form a solvent-free adhesion The dry film 131 is preferably subjected to another vacuum drying heating to completely remove the solvent 'at this time'. The adhesive dry film 1 31 on the substrate 1 1 1 has the characteristics of β-stage [B-stage]. At temperature, it becomes a non-sticky film [Tg ^ 40 ° C]. Tg is the glass transition temperature. When the adhesive dry film 131 is higher than its glass transition temperature, it will change from rigid to Soft and adhesive, so the substrate 11 with the adhesive dry film 131 can be stacked and stored at room temperature, which is beneficial to the subsequent processing of the SOC package;

120,該晶片120具有一主動面121 〔 active surface〕及 複數個在主動面121之焊墊122,其中晶片120之主動面121 係接觸基板11〇之上表面U1且晶片12〇之焊墊122係位置對 應於基板110之通孔113,在本實施例中,焊墊122係位於 晶片120主動面121之中間部位;爾後,施壓加熱基板11〇 與晶片120,約在攝氏180度並在適當壓力下維持數秒鐘之 久,使得上述無溶劑之黏著乾膜131能機械性黏合晶片12〇 與基板110,但不需要完全固化,由於在熱黏合晶片與 基板110之步驟時,黏著乾膜131並不具有高流動性,不^ 有受擠壓流至晶片120之焊墊122的現象;爾後,經由通?曰匕 113以金屬焊線140打線電性連接晶片12〇之焊墊 U0 ;最後’形成一熱固性封膠材150於該基板11()之通\ 511258120, the wafer 120 has an active surface 121 [active surface] and a plurality of pads 122 on the active surface 121, wherein the active surface 121 of the wafer 120 is in contact with the upper surface U1 of the substrate 11 and the pad 122 of the wafer 120 The position corresponds to the through hole 113 of the substrate 110. In this embodiment, the bonding pad 122 is located in the middle of the active surface 121 of the wafer 120; thereafter, the substrate 11 and the wafer 120 are heated under pressure, at about 180 ° C and at It is maintained under appropriate pressure for several seconds, so that the solvent-free adhesive dry film 131 can mechanically bond the wafer 120 and the substrate 110, but it does not need to be completely cured. 131 does not have high fluidity, and does not have the phenomenon of being squeezed to the pads 122 of the wafer 120; The dagger 113 is electrically connected to the solder pad U0 of the wafer 12 with a metal bonding wire 140; finally, a thermosetting sealing material 150 is formed on the substrate 11 () \ 511258

U 3處’在本實施例中,其係以壓模〔_丨d丨叩〕方式形成 ,封膠材150 ’該封膠材150並密封晶片120,較佳地,在 壓模過程後隨同封膠材丨5 〇之加熱固化〔約要攝氏兩百多 度並維持數小時〕而固化該黏著乾膜1 3 1 ,由於壓模壓力 可排除原本可能潛藏在未固化前黏著乾膜丨3 1之空隙,以 1進封裝良率,如有需要,並接植複數個焊球丨6〇於基板 下表面112,並在切割分離後,構成複數個soc封裝 結構1 0 0。 〜因=,本發明係運用兩階段特性〔two stage〕具有 合物130於基板在晶片上⑽)之封裝過程 覆蓋晶片12〇之焊塾122的缺J1“材料’避免了液態黏膠 時已形成熱固性黏著乾膜i 3 i美 (义率,同 放’有利於後續SOC封裝之加工基板110可供堆疊搬運或儲 故本發明之保護範圍當視後附之 者為準,任何熟知此項技藝者」範圍所界定 範圍内所作之任何變化與修 =明之精神和 圍。 Θ屬於本發明之保護範 511258 --—-90123399 年月日 圖式簡單說明 ' — " 【圖式說明】 第1圖:在美國專利案第6, 19〇, 943號 法」中,一SOC封裝結構之截 修正 第2圖 第3圖 【圖號說明 2 0 SOC封裝結構 基板 「晶片尺寸封裝方 面圖; 在美國專利案第6, 190, 943號「晶片尺寸封裝方 法」中,該SOC封裝結構之製造流程圖;及 依本發明之一具體實施例,/基板在晶片上 (s〇c)封裝過程之製造流程圖。 2228 34 4044 通孔 導電層 焊球 1 00 SOC封裝結構 110基板 111上表面 120晶片 130兩階段熱固士 1 4 0金屬焊線 3 0 2黏晶區域 24 晶片 26 主動面 30 上表面 32 金屬焊線 36 焊墊 38 下表面 41 導接墊 42 封膠材 .1 I', 1;; 112 下表面 113 通孔 121 主動面 122 焊墊 混合物 131 黏著乾膜 150 封膠材 160 焊球 1U 3 places' In this embodiment, it is formed in the form of a stamper [_ 丨 d 丨 ,], and the sealant 150 is sealed. The sealant 150 is sealed and the wafer 120 is sealed. The same sealant 丨 50 ° C is cured by heating (about 200 degrees Celsius and maintained for several hours) to cure the adhesive dry film 1 3 1, due to the pressure of the die, it may be excluded that the dry film may be latently adhered before being cured 丨 3 The gap of 1 is entered into the package with a yield of 1. If necessary, a plurality of solder balls are implanted on the lower surface 112 of the substrate, and after cutting and separation, a plurality of soc packaging structures 100 are formed. ~ Because =, the present invention uses a two-stage package (two stages) with a compound 130 on the substrate on the wafer.) The packaging process covers the lack of J1 "materials" on the wafer 120 and the soldering material 122 to avoid the liquid adhesive. Forming a thermosetting adhesive dry film i 3 i beauty (meaning, put together) is conducive to subsequent processing of the SOC package 110 substrate can be stacked for transportation or storage. Therefore, the scope of protection of the present invention is subject to the attached one, any familiar with this Any changes and modifications made within the scope defined by the "artist" range are the spirit and scope of the Ming. Θ belongs to the protection scope of the present invention 511258 ----90123399 Schematic description of the month, day and day '— " [Schematic description] The Figure 1: In the US Patent No. 6,19,943, a section of the SOC package structure is revised, Figure 2 and Figure 3 [Figure No. Description 20 SOC package structure substrate "chip size packaging aspects; In the US Pat. No. 6,190,943 "wafer size packaging method", the manufacturing flow chart of the SOC package structure; and according to a specific embodiment of the present invention, the process of packaging the substrate on the wafer (soc) Manufacturing flow chart. 2228 34 40 44 through-hole conductive layer solder ball 1 00 SOC package structure 110 substrate 111 upper surface 120 wafer 130 two-stage thermoset 1 4 0 metal bonding wire 3 0 2 die bonding area 24 chip 26 active surface 30 upper surface 32 metal bonding wire 36 Pad 38 lower surface 41 lead pad 42 sealing material. 1 I ', 1; 112 lower surface 113 through hole 121 active surface 122 pad mixture 131 adhesive dry film 150 sealing material 160 solder ball 1

第11頁Page 11

Claims (1)

?/年义,雙、 MM 9012339a 六、申請專利範圍 【申請專利範圍 ,、 程,其步驟包含 種基板在晶片上 a) 提供一基板,該基板具 通上下表面之通孔; 上表面、一下表面及連 b) 在基板之上表而游士 —庶 stage Ί JL ^ 形成層兩階段特性〔two stage〕具有浴劑之熱固性混合物; 膜c;)去除洛劑’使熱固性混合物形成無溶劑之黏著乾 叙曰曰片,晶片具有-主動面及複數個在主 動面之焊墊,並中a y々+仏 Q u t ^ /、〒曰曰片之主動面係接觸基板之上表面且 _ 曰曰片f焊墊係位置對應於基板之通孔; e) 》e壓加熱基板與晶片,使上述無溶劑之黏著乾膜祕 合晶片與基板; f) 經由通孔打線電性連接晶片之焊墊至基板; g) 壓模形成一封膠材於該基板之通孔處;及 h) 加熱固化該封膠材與無溶劑之黏著乾膜。 :、如申請專利範圍第1項中所述之基板在晶片上 〔S0C〕之封裝過程,其係以網版印刷方法形成一層熱 固性混合物。 3、如申請專利範圍第ί項中所述之基板在晶片上 〔S0C〕之封裝過程,其係以印刷〔paint ing〕、喷塗 〔spraying〕、旋塗〔Spinning〕或浸染〔dipping〕 方法形成一層熱固性混合物。? / Nianyi, double, MM 9012339a VI. Patent application scope [Patent application scope, process, the steps include a substrate on the wafer a) Provide a substrate with through holes through the upper and lower surfaces; The surface and the b) on the substrate-士 stage Ί JL ^ formation of the two-stage characteristics [two stage] thermosetting mixture with a bath agent; film c;) remove the agent 'to make the thermosetting mixture into a solvent-free Adhesive dry film, the chip has an active surface and a plurality of pads on the active surface, and ay々 + 仏 Q ut ^ /, the active surface of the film is in contact with the upper surface of the substrate and _ The position of the f pad is corresponding to the through hole of the substrate; e)》 e pressure heats the substrate and the wafer, so that the above solvent-free adhesive dry film is combined with the wafer and the substrate; f) the pad is electrically connected to the wafer through the through hole. To the substrate; g) forming a sealant at the through hole of the substrate by compression molding; and h) heating and curing the adhesive sealant and the solvent-free dry film. : The packaging process of the substrate [S0C] on the wafer as described in item 1 of the scope of patent application is to form a layer of thermosetting mixture by screen printing. 3. The packaging process of the substrate [S0C] on the wafer as described in item ί of the scope of the patent application, which is performed by printing [painting], spraying (spraying), spin coating (spinning) or dipping (dipping). A layer of thermosetting mixture is formed. 第12頁 、如申請專利範圍第丨項中所述之基板在晶片上 〔S〇t〕之封裝過程,其在「加熱固化該封膠材」之h) 步驟後」另包含有··接植複數個焊球於基板之下表面。 如申清專利範圍第1項中所述之基板在晶片上 Γ Q Π P ^ ^封裝過程,其中該封膠材係密封晶片。 、如申請專利範圍第1項中所述之基板在晶片上 〔SOC〕之封裝過程,其中係以加熱或真空 除溶劑。忒云 、如申請專利範圍第1項中所述之基板在晶片上 丄SOC〕之封裝過程,其中在h)加熱固化步驟之严 高於C)去除溶劑步驟之溫度。 皿又On page 12, the packaging process of the substrate on the wafer [S〇t] as described in item 丨 of the scope of the patent application, which includes the following steps after the "h) step of" heat curing the sealing material " A plurality of solder balls are planted on the lower surface of the substrate. The substrate is encapsulated on the wafer as described in item 1 of the scope of patent application, wherein the sealing material is a sealed wafer. The packaging process of the substrate [SOC] on the wafer as described in item 1 of the scope of the patent application, wherein the solvent is removed by heating or vacuum. Jin Yun, the packaging process of the substrate on the wafer (SOC) as described in item 1 of the scope of patent application, where the temperature of the heat curing step in h) is higher than the temperature in the step of removing the solvent. Dish
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