CN116721970A - 半导体器件的接触孔制备及金属填充方法 - Google Patents
半导体器件的接触孔制备及金属填充方法 Download PDFInfo
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract
本申请提供一种半导体器件的接触孔制备及金属填充方法,包括:提供晶圆,晶圆包括依次层叠的基底、外延片、层间介质层;在层间介质层背离基底的表面形成一层光刻胶,对光刻胶进行曝光、显影,去除部分的光刻胶以使接触孔区域露出;湿法蚀刻层间介质层;干法蚀刻层间介质层直到贯穿层间介质层达到外延片,该干法蚀刻步骤中,沿逐渐靠近基底的方向,接触孔的开口逐渐减小;在接触孔的孔壁上沉积金属钨层;在接触孔中沉积导电金属直到填满接触孔。本申请通过湿法蚀刻和干法蚀刻结合的方式形成接触孔,并在接触孔中预先设置金属钨层,有效避免后续沉积导电金属于接触孔中出现顶部闭合而导致填充不满出现空洞的问题。
Description
技术领域
本申请涉及半导体技术领域,具体而言,涉及半导体器件的接触孔制备及金属填充方法。
背景技术
绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor,IGBT)和金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)是半导体功率器件的典型代表,二者的器件结构既有相似的地方也存在差异。例如,IGBT元胞的发射极和MOSFET元胞的源极需要通过相同金属串联起来,在器件的制备过程中,通常通过光刻胶掩膜的方式曝光显影形成接触孔,随后在接触孔中沉积铝(Al)金属电极使IGBT元胞或MOSFET元胞电性连接。然而,在制备半导体器件的接触孔时,若两器件元胞之间的距离太近,在Al金属沉积接触孔的过程中易造成填孔不满,形成空洞的现象,甚至严重导致金属连接存在问题导致器件漏电严重。若元胞之间的距离较远,会导致单颗芯片的尺寸变大,不利于集成化,造成晶圆的利用率降低。
发明内容
鉴于此,本申请提供一种半导体器件的接触孔制备及金属填充方法,包括:
提供晶圆,所述晶圆包括依次层叠的基底、外延片、层间介质层;
在所述层间介质层背离所述基底的表面形成一层光刻胶,对所述光刻胶进行曝光、显影,去除部分的所述光刻胶以使接触孔区域露出;
湿法蚀刻所述层间介质层;
干法蚀刻所述层间介质层直到贯穿所述层间介质层达到所述外延片,该干法蚀刻步骤中,沿逐渐靠近所述基底的方向,所述接触孔的开口逐渐减小;
在所述接触孔的孔壁上沉积金属钨层;
在所述接触孔中沉积导电金属直到填满所述接触孔。
本申请通过湿法蚀刻和干法蚀刻结合的方式形成接触孔,并在接触孔中预先设置金属钨层,由于钨具有较低的电阻,较强的阶梯覆盖能力等优异的物理性质,应用于接触孔的表层填充,能有效避免后续沉积导电金属于接触孔中出现顶部闭合而出现填充不满导致的空洞问题。如此,该接触孔工艺可有效实现两器件元胞近距离而不发生接触孔空洞问题,利于芯片的集成化,提升晶圆的利用率。
附图说明
图1为本申请一实施例的接触孔制备及金属填充方法的流程图。
图2为步骤S1的剖面示意图。
图3为步骤S2的剖面示意图。
图4为步骤S3的剖面示意图。
图5为步骤S4的剖面示意图。
图6为步骤S5的剖面示意图。
图7为步骤S6的剖面示意图。
图8为采用本申请接触孔制备及金属填充方法制得的器件的局部扫描电镜(Scanning Electron Microscope,SEM)图。
主要元件符号说明:
SiC晶圆100,SiC基底10,SiC外延片20,栅氧化层30,多晶硅层40,
层间介质层50,P阱区21,P+区23,N+区25,光刻胶60,接触孔51,
过渡层55,金属W层57,导电金属70。
具体实施方式
本申请提供一种半导体器件的接触孔制备及金属填充方法。本申请实施例以碳化硅(SiC)基MOSFET器件作为示例,在SiC基MOSFET器件中形成接触孔用以连接相邻元胞的源极,然后再在接触孔中填充金属。当然,本申请的半导体器件的接触孔制备及金属填充方法,不限于应用在SiC基MOSFET器件的制备中。
SiC作为第三代半导体中的典型代表,由于其热导率高、击穿场强高 、载流子饱和迁移率高等优良的物理特性,使其能够替代硅(Si)材料制备高温、高压等功率电子器件,并在新能源汽车、光伏发电等领域具有广阔的应用前景。
如图1所示,本申请实施例的半导体器件的接触孔的制备及金属填充方法,包括步骤S1至S6。
请参阅图2,步骤S1:提供待蚀刻接触孔的SiC晶圆100,所述SiC晶圆100包括依次层叠的SiC基底10、SiC外延片20、层间介质层50。
本实施例中,所述SiC晶圆100包括从下至上依次层叠的SiC基底10、SiC外延片20、栅氧化层30、多晶硅层40和层间介质层50。所述SiC外延片20通过离子注入形成有P阱区21、P+区23和N+区25。所述MOSFET器件的形成包括:在SiC基底10上形成SiC外延片20;对SiC外延片20进行离子注入使SiC外延片20中形成P阱区21、P+区23和N+区25;高温退火激活;在SiC外延片20上形成栅氧化层30;在栅氧化层30上形成多晶硅层40;以及在多晶硅层40上形成层间介质层50。
离子注入形成P阱区21、P+区23和N+区25后,通常需进行高温退火激活处理,此时需要在产品的表面覆盖一层碳膜(厚度约为30nm)进行保护,以避免高温退火过程中SiC表面Si析出,或在高温下SiC表面发生原子迁移从而导致SiC表面恶化出现表面石墨化以及严重粗糙化的问题。一实施例中,高温退火激活的温度可为1750℃。此外离子注入形成N+区25形成沟道时可采用自对准工艺完成。
本实施例中,N+区25和P+区23均被P阱区21所围绕,P+区23位于P阱区21和N+区25的中央并将P阱区21和N+区25分别分隔成相互独立的两部分。如此,两个P阱区21和两个N+区25分别属于不同的元胞,构成两个独立元胞的P阱区21和N+区25。此外,SiC的一个独特优势为可以通过热氧化的方式得到高质量的SiO2,因此可以通过干氧氧化并通过N2退火钝化的方式形成高质量的栅氧化层30设置在多晶硅层40(充当栅极)与SiC外延片20之间。另外,栅氧化层30和多晶硅层40均未覆盖SiC外延片20中的P+区23和N+区25,即所述栅氧化层30和多晶硅层40中开设有贯穿孔以使P+区23和N+区25相对露出。所述层间介质层50不仅覆盖所述多晶硅层40背离所述SiC基底10的表面且填满所述贯穿孔,即所述层间介质层50贯穿所述多晶硅层40和所述栅氧化层30而达到所述N+区25和P+区23。
本实施例中,所述层间介质层50包括两层,一层为掺杂B和P的二氧化硅层(Boro-Phospho Silicate Glass,BPSG),厚度为6000~8000Å,另一层为本征二氧化硅层(UndopedSilicate Glass,USG),厚度为2000~4000Å,其中掺杂的二氧化硅层位于本征二氧化硅层上方,即掺杂B和P的二氧化硅层相对本征二氧化硅层更远离所述SiC基底10。栅氧化层30的材料为二氧化硅。
一实施例中,多晶硅层40的厚度为4000Å,层间介质层50包括厚度为8000Å的掺杂二氧化硅层和厚度为2000Å的本征二氧化硅层。
可以理解的,本次以SiC基MOSFET器件作为示例,因此基底和外延片均为SiC材料,但不以此为限。
请参阅图3,步骤S2:在所述SiC晶圆100的外表面形成一层光刻胶60,对所述光刻胶60进行曝光、显影以去除部分的光刻胶60,露出后续需蚀刻的部位(接触孔区域)。
该步骤可使用涂胶显影机,将光刻胶60旋涂到SiC晶圆100的正面,即光刻胶60附着在层间介质层50的表面,然后将光刻胶60进行局部曝光,接着使用显影液下对曝光后的光刻胶60进行显影。当所述光刻胶60为正性光刻胶60时,曝光后的光刻胶60被显影液溶解,而其他未曝光的光刻胶60则保留下来成为后续蚀刻接触孔的遮蔽层。当所述光刻胶60为负性光刻胶60时,未曝光后的光刻胶60被显影液溶解,而其他曝光的光刻胶60则保留下来成为后续蚀刻接触孔的遮蔽层。
一实施例中,通过使用芯源微型号为KS-S150-2C2D的涂胶显影机,将型号为AZ5214的正性光刻胶旋涂至SiC晶圆100的正面,光刻胶60旋涂的厚度为1.5μm,随后使用型号为AZ300MIF的正性光刻胶显影液下显影1min,如此,接触孔位置的光刻胶60被溶解去除使接触孔位置露出,而其他地方覆盖有光刻胶60。
请参阅图4,步骤S3:湿法蚀刻所述SiC晶圆100的外表的层间介质层50。
该步骤蚀刻的是所述层间介质层50中的BPSG,而不会蚀刻所述层间介质层50中的USG。
一实施例中,该步骤通过使用吉姆西型号为JZX-06JB-W03的前道腐蚀机台对有光刻胶60保护下的层间介质层50进行刻蚀,该步骤使用的湿法药液为缓冲氧化物刻蚀液(Buffered Oxide Etch,BOE),含有氢氟酸(HF)与氟化铵(NHF4)。一实施例中,湿法药液为浓度为49% HF 和浓度为40% NHF4按照1:6的比例配制。由于湿法蚀刻具有横向刻蚀的特性,该步骤的蚀刻量会在横向方向上超出暴露的掺杂二氧化硅层区域,即在光刻胶60层的下方(朝向所述SiC基底的一侧)横向上有一定的过量蚀刻,形状类似水滴状;而纵向方向上蚀刻较浅,纵向上蚀刻深度为层间介质层50的厚度的20%~30%。该湿法蚀刻的步骤的目的是为了使接触孔的上方得到扩展。
请参阅图5,步骤S4:干法蚀刻所述层间介质层50直到贯穿所述层间介质层50到达所述SiC外延片20。
通过干法刻蚀将SiC外延片20上方的接触孔51完全打开,直至露出SiC外延片20中的P+区23和N+区25停止。一实施例中,由于后续应用磁控溅射沉积导电材料于接触孔中,例如型号为AMAT Endura550的磁控溅射设备对于横向宽度为1μm的接触孔时接近于设备工艺极限,再小已经无法实现金属沉积;因此,该步骤中接触孔51的横向宽度控制大于1μm且小于等于2μm。
另外一方面,该干法刻蚀的刻蚀角度,控制接触孔51的截面形状整体呈现为倒梯形,上宽下窄,即沿逐渐靠近SiC基底10的方向,所述接触孔51的开口是逐渐减小的。所述接触孔51的侧壁与底壁的之间的角度可控制为70°~85°。一实施例中,该步骤中干法刻蚀应用型号为AMAT P5000的干法蚀刻设备。
该步骤后完成后得到接触孔51,该接触孔51的孔侧壁由所述层间介质层50所限定形成,孔底壁由P+区23和N+区25共同限定形成,即接触孔51暴露所述P+区23和N+区25。该接触孔51贯穿所述层间介质层50。
请参阅图6,步骤S5:在所述接触孔51的孔壁上沉积过渡层55,然后再在过渡层55上沉积金属钨(W)层57。过渡层55和金属W层57厚度均较薄,不会导致接触孔51的上方出现闭合的情况,从而不会影响后续金属沉积到接触孔中。
本实施例中,所述过渡层55包括依次层叠在接触孔51的孔壁上的镍(Ni)层、钛(Ti)层、氮化钛(TiN)层。Ni层的厚度为800~1200Å,Ti层的厚度为800~1200Å,TiN层的厚度为400~600Å。该过渡层55中的Ni层作为良好的欧姆接触金属,减小金属与半导体SiC之间的接触势垒,从而降低接触电阻,Ti/TiN层的作用依然为增强后续沉积的金属与所述接触孔51的孔壁的粘附性以及作为扩散阻挡层的作用。本实施例中,所述过渡层55采用磁控溅射的方式形成,但不以此为限。
由于金属W具有很好的填孔能力,通过在过渡层55上设置一金属W层57,可使接触孔51的孔壁更加光滑,如此后续沉积金属Al的过程中铝原子不会堆积在接触孔51上方而会直接滑落至接触孔51的底部,避免金属Al填孔的过程中形成空洞填不满,除此之外,W具有较低的电阻,作为过渡层与后续沉积金属Al的接触层并不会增加整个器件的电阻。本实施例中,所述金属W层57采用化学气相沉积的方式形成,但不以此为限,例如也可使用低压化学气相沉积(Low Pressure Chemical Vapor Deposition,LPCVD)沉积高质量W金属。
一实施例中,使用机型为AMAT Endura550 的磁控溅射设备依次溅射厚度为1000Å的Ni,厚度为1000Å的Ti和厚度为500Å的TiN,随后使用化学气相沉积的方法,采用WF6/SiH4约4:1,生成厚度约500Å的W沉积于Ti/TiN上。
请参阅图7,步骤S6:在所述接触孔51中沉积导电金属70直到填满所述接触孔51。
本实施例中,该步骤沉积的导电金属70为金属铝。金属铝的厚度要远大于过渡层55和金属W层57的厚度。金属铝的厚度为4~5μm。该步骤沉积导电金属70可采用磁控溅射法、化学气相沉积法、电子束蒸发等方法。一实施例中,该步骤采用机型为AMAT Endura550 的磁控溅射设备溅射金属Al于步骤S5的金属W之上。
结合参阅图8,通过该方法制备的器件SEM结构图,从图中明显看出溅射形成的金属Al填满接触孔,无空洞产生。
本方案中导电金属70的沉积方法不限于磁控溅射,也可使用高密度电浆化学气相沉积(HDP-CVD),电子束蒸发等方法,其他金属沉积也可使用比磁控溅射机台更好的成膜质量设备淀积。
可以理解的,所述接触孔51中的导电金属70用于连接相邻元胞的源极(图未示),以使元胞之间实现电性连接。所述源极大致形成在所述层间介质层50背离所述SiC基底10的一侧。
本申请通过湿法蚀刻和干法蚀刻结合的方式形成接触孔,并在接触孔中预先设置金属W层57,有效避免后续沉积导电金属70于接触孔中出现顶部闭合而出现填充不满出现空洞的问题。如此,该接触孔制备及金属填充方法可有效实现两器件元胞近距离而不发生接触孔空洞问题,利于芯片的集成化,提升晶圆的利用率。
以上实施方式仅用以说明本申请的技术方案而非限制,尽管参照以上较佳实施方式对本申请进行了详细说明,本领域的普通技术人员应当理解,可以对本申请的技术方案进行修改或等同替换都不应脱离本申请技术方案的精神和范围。
Claims (10)
1.一种半导体器件的接触孔制备及金属填充方法,其特征在于,包括:
提供晶圆,所述晶圆包括依次层叠的基底、外延片、层间介质层;
在所述层间介质层背离所述基底的表面形成一层光刻胶,对所述光刻胶进行曝光、显影,去除部分的所述光刻胶以使接触孔区域露出;
湿法蚀刻所述层间介质层;
干法蚀刻所述层间介质层直到贯穿所述层间介质层达到所述外延片,该干法蚀刻步骤中,沿逐渐靠近所述基底的方向,所述接触孔的开口逐渐减小;
在所述接触孔的孔壁上沉积金属钨层;
在所述接触孔中沉积导电金属直到填满所述接触孔。
2.根据权利要求1所述的接触孔制备及金属填充方法,其特征在于,所述层间介质层包括层叠设置的掺杂B和P的二氧化硅层和本征二氧化硅层,其中所述掺杂B和P的二氧化硅层相对所述本征二氧化硅层更远离所述基底。
3.根据权利要求2所述的接触孔制备及金属填充方法,其特征在于,所述湿法蚀刻步骤使用的湿法药液为缓冲氧化物刻蚀液。
4.根据权利要求2所述的接触孔制备及金属填充方法,其特征在于,所述湿法蚀刻的步骤中蚀刻的是所述掺杂B和P的二氧化硅层,所述掺杂B和P的二氧化硅层的厚度为6000~8000Å;所述干法蚀刻的步骤中蚀刻的是所述掺杂B和P的二氧化硅层和所述本征二氧化硅层,所述本征二氧化硅层的厚度为2000~4000Å。
5.根据权利要求1所述的接触孔制备及金属填充方法,其特征在于,所述金属钨层沉积的厚度为300~600Å。
6.根据权利要求1所述的接触孔制备及金属填充方法,其特征在于,所述接触孔工艺还包括在所述接触孔的孔壁上沉积金属W层之前,在所述接触孔的孔壁上沉积过渡层,所述过渡层包括依次层叠在所述接触孔的孔壁上的厚度为800~1200Å的Ni层、厚度为800~1200Å的Ti层、厚度为400~600Å的TiN层。
7.根据权利要求1所述的接触孔制备及金属填充方法,其特征在于,所述湿法蚀刻所述层间介质层的步骤中,蚀刻深度为所述层间介质层的厚度的20%~33%。
8.根据权利要求1所述的接触孔制备及金属填充方法,其特征在于,所述接触孔的侧壁与底壁的之间的角度大于等于70°且小于等于85°。
9.根据权利要求1所述的接触孔制备及金属填充方法,其特征在于,所述干法蚀刻所述层间介质层的步骤中,所述接触孔的横向宽度控制大于1μm且小于等于2μm。
10.根据权利要求1所述的接触孔制备及金属填充方法,其特征在于,在所述接触孔中沉积导电金属的步骤中,沉积的导电金属为金属铝,所述导电金属的厚度为4~5μm。
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