CN1165401A - Testing apparatus for non-packaged semiconductor chip - Google Patents

Testing apparatus for non-packaged semiconductor chip Download PDF

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Publication number
CN1165401A
CN1165401A CN97104304A CN97104304A CN1165401A CN 1165401 A CN1165401 A CN 1165401A CN 97104304 A CN97104304 A CN 97104304A CN 97104304 A CN97104304 A CN 97104304A CN 1165401 A CN1165401 A CN 1165401A
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CN
China
Prior art keywords
lead
lead frame
testing apparatus
wire
gland
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Granted
Application number
CN97104304A
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Chinese (zh)
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CN1103495C (en
Inventor
郑和晋
金英浩
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN1165401A publication Critical patent/CN1165401A/en
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Publication of CN1103495C publication Critical patent/CN1103495C/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The invention discloses a non-packaging semiconductor chip testing device, including a lead frame with a chip which separates other leads supported by adhesive tapes and is bonded to a lead through line connection. The lead frame is arranged on a supporting board with a window, so as to expose the lead of the lead frame through the window to make the lead contact with a testing probe arranged below the board. A substrate is contained by a base. A cable on the substrate passes through an opening of the base and is connected with a testing board. When the lead frame is pressed by a gland, the lead frame on the supporting board moves downward to make the lead and the testing probe contacted. After the test, the gland is reset with the help of a drive device, and the lead frame is reset with the help of elasticity.

Description

The testing apparatus of non-packaged semiconductor chip
The present invention relates generally to a kind of testing apparatus of semiconductor device, particularly a kind ofly be used for not encapsulating or interchange (AC) test of bare chip and the device of ageing test.
Semi-conductor industry has entered a brand-new developing stage.Proposed a kind of multi-chip module (MCM) that the several piece semiconductor chip is installed and replaced single-chip package on a circuit board.This multi-chip module (MCM) has than operating rate, bigger capacitance and the integrated level of Geng Gao faster before.Except that these advantages, there is the problem that will solve in MCM, that is, compare with the single-chip package technology, and the integrated scale of MCM increases, but productivity ratio greatly reduces.A kind of like this poor efficiency can produce undesirable a large amount of waste material, thereby the processing again that need spend and require great effort.Therefore, require to have passed through chip test such in the conventional encapsulation technology, that be known as (KGD) and produce MCM, these chip un-encapsulated but confirmed it is reliable with those.The validity of KGD is depended in the exploitation of the success of MCM.
In order to ensure the reliability of semiconductor chip, generally to carry out a series of test to semiconductor chip.One of them test is the AC test, and in the test, all input and output sides all are connected on the test signal generation circuit, in order to the transmission characteristic between the signal of checking input and output terminal.Another test is higher than under the excessive condition of normal working temperature and voltage for making given chip be in, in order to verify its life-span.These tests can detect defective chip, and eliminate assembling or handle the contingent inefficacy in back.
Yet it is very difficult to be electrically connected not encapsulation or bare chip and test signal generation circuit, unless chip encapsulates.So, generally to come packaged chip, and, can test in the test jack that is installed to again after the outer lead insertion wherein on the test board with the outer lead that is connected with chip bonding pad.But the shortcoming of this measuring technology is to encapsulate possible bad chips and can cause waste, and limited the increase of once testing bare chip quantity.
Proposed the method that addresses these problems in the United States Patent (USP) 5006792, that is, provide a kind of flip-chip test jack adapter, the bare chip that is formed with a plurality of solder bumps on its chip bond pads has been carried out ageing test.Flip-chip inserts in the test jack adapter, carries out ageing test.This test jack adapter comprises the substrate with the cantilever beam that matches with shell.This technology with this socket adapter can be at encapsulation Pretesting bare chip.
Yet, by this prior art, because spacing is thin between bonding welding pad, so the apparatus for testing chip that can accurately form solder bump on the bonding welding pad of chip must be provided.Another problem is in order to ensure the reliability of test, once can only survey chip piece.So the cost of a KGD can increase, and this test is unhelpful to producing a large amount of KGD.And, in the test period of this intractable chip process chip individually.In addition, when the chip that will test changes, must change the structure of above-mentioned socket adapter, make it to adapt with the bonding welding pad of another kind of configuration.
Another technology of test bare chip is disclosed in United States Patent (USP) 5479105, and this patent provides a kind of die testing device, comprising having the lead frame that is installed in the bare chip on the pipe core welding disc.Pipe core welding disc is supported by pull bar, and lead-in wire is supported by adhesive tape.Bare chip links to each other with lead-in wire by line.The test jack of socket and last socket under this lead frame places and comprises.Following socket has slit, and the last socket that is suspended from down socket has groove hole and the test probe that contacts with the lead-in wire of lead frame.Pin passes the groove hole, and imports the hole place the lead frame periphery, inserts then in the slit, and in up and down between the socket, a side of lead frame is held on up and down between the socket by anchor clamps lead frame by means of this dowel fixes.Test jack has the plunger part of a live contact on it, and this part is arranged at the edge of socket, so that can insert in the test board.
Although this measuring technology has overcome the problem in the above-mentioned technology, but still there are some defectives.At first, because the plunger of this test jack part must vertically be inserted in the test board, lead frame has the bare chip that links to each other with its lead-in wire by line, and lead frame is in erectility.Thereby line is frangibility in the rigidity environment.The second, when test jack is closed, the necessary break-through groove hole of pin, pilot hole and slit, this can cause productivity ratio to reduce.
Therefore, the modifying device that the purpose of this invention is to provide a kind of low cost test non-packaged semiconductor chip.
Another object of the present invention provides a kind of modifying device of testing various non-packaged semiconductor chips, can not consider number of chips what or chip bond pads configuration how.
A further object of the invention provides a kind of device of steady testing non-packaged semiconductor chip.
The testing apparatus that can realize these and other objects of the present invention comprises: the lead frame that chip is housed; The plate of supporting wire frame; The substrate that has test probe; The base that holds substrate; And push the lid of lead frame.Described lead frame has many lead-in wires electrically isolated from one, and these lead-in wires are actual to be supported by adhesive tape.At least one semiconductor chip that will test is by line and described lead-in wire bonding.This lead frame comprises one group of lead-in wire at least.Every group of lead-in wire belongs to the chip piece with described lead-in wire bonding respectively, and each group lead-in wire separates each other.Every group of lead-in wire also comprises installs bonding pads thereon.
Supporting bracket has a plurality of windows, forms these windows in order that pass through the lead-in wire of their exposed leads frames.Test probe on the substrate contacts with the lead-in wire that window by supporting bracket exposes.Can form the protective layer of band probe aperture on the substrate.Test probe can be spring stilt pin (resilient pogopin) or elastic bending lead-in wire.Substrate also comprises with the cable that connects test probe and test signal generation circuit.
Base comprises the under shed that is used to hold the upper shed of substrate and is used to pass cable.Upper shed is greater than under shed, and substrate just can be inserted in the upper shed like this, and is mounted thereon.Base can comprise the spring of resilient connection supporting bracket.Gland places on the lead frame, so that push lead frame.The cavity that the protection line is arranged on the gland.
Testing apparatus of the present invention also comprises drive unit, and this device is fixed on the gland, is used to move up and down gland.The base of testing apparatus comprises a guide that extends vertically up to gland at least, and guide has an oblique slit at least.Gland can be fixed on the drive unit by slit oblique in the guide.Therefore, gland can move up and down obliquely.
Testing apparatus of the present invention also comprises a guide pin outside the upper shed of base at least.Guide pin on the base passes the through hole of supporting bracket and the pilot hole of toe-in frame, then, is inserted in the groove of gland.
Fig. 1 is a decomposition diagram of showing the spatial relation between the critical piece of non-packaged semiconductor chip testing apparatus of the present invention.
Fig. 2 is an enlarged perspective of showing the lead frame of the testing apparatus that is used for Fig. 1.
Fig. 3 is whole generalized section of showing testing apparatus of the present invention.
Fig. 4 A and 4B are that explanation utilizes the testing apparatus of Fig. 3 to test the amplification profile of the technical process of non-packaged semiconductor chip.
Fig. 5 is a plane graph of showing the substrate bottom surface in the testing apparatus of the present invention.
Fig. 6 A and 6B are the perspective views of running of the gland of explanation testing apparatus of the present invention.
Fig. 7 is that the part of showing the spatial relation between each critical piece of another non-packaged semiconductor chip testing apparatus of the present invention splits decomposition diagram.
Fig. 8 is the generalized section of main parts size of the testing apparatus of exploded view 7.
Below with reference to each accompanying drawing of showing the preferred embodiments of the present invention the present invention is described more fully.Yet the present invention can have many multi-form imbodies, is not limited to embodiment described here; It only is for openly the present invention fully fully that these embodiment are provided, and shows scope of the present invention to those skilled in the art.In each accompanying drawing, identical numeral is represented identical parts all the time.
Fig. 1 shows the spatial relation between the critical piece of testing apparatus 100 of non-packaged semiconductor chip 1 of the present invention, and Fig. 2 shows the lead frame 10 of the testing apparatus 100 that is used for Fig. 1.Referring to Fig. 1, testing apparatus 100 comprises and has at least one lead frame of wanting the measuring semiconductor chip 10.As shown in Figure 2, lead frame 10 has many lead-in wires 12 and nonconducting adhesive tape 18.The every group of lead-in wire 12 that belongs to chip piece 1 isolated with other lead-in wire and lead frame 10 electricity, and in fact supported by adhesive tape 18.Lead-in wire 12 surrounds semiconductor chip 1, particularly unpackaged chip or bare chip, then, utilizes line 14 with they bondings.Pilot hole 16 can make lead frame 10 in place.Lead frame 10 can not have pad, as shown in Figure 2.On the other hand, lead frame 10 also can comprise pad, makes as the United States Patent (USP) 5548884 of the II U.Kim that quotes as proof here as described in the method for KGD arrays.Although bonding pads is not installed, chip can be by means of line with lead-in wire machinery and be electrically connected.
Lead frame 10 is placed on the supporting bracket 20.For supporting wire frame 10, the pilot hole 16 corresponding through holes 26 with lead frame 10 are set on supporting bracket 20.The lead-in wire 12 of lead frame 10 comes out by the window 22 that is formed on the supporting bracket 20,12 can be connected with the substrate 30 under placing it so that go between.
Substrate 30 comprises a plurality of test probes 33 that will contact with the lead-in wire 12 of lead frame 10 by the window of supporting bracket 20.Test probe 33 extends upward from substrate 30, and each probe 33 is all linked on the corresponding cable 34 that extends downwards.These many cables 34 link to each other with unshowned test signal generation circuit again, be used for to from chip 1 transmission of electric signals.Spring stilt pin or elastic bending lead-in wire can be used as test probe 33.Although used spring stilt pin in the present embodiment, also can use bending lead, shown in Fig. 7 and 8.Protective layer 32 can be set, with protection test probe 33 on substrate 30.In this case, in the probe aperture that test probe 33 inserts in the protective layer 32.In order to prevent that protective layer 32 is preferably by constituting as materials such as polyamide owing to the heat that produces in the test is out of shape.
Substrate 30 inserts in the opening of base 40.Each opening is separated into two parts all, that is, and and upper shed 42 and under shed 44.So because the size of each upper shed 42 can be installed on the upper surface 43 of contiguous under shed 44 greater than under shed 44 every substrates 30.Substrate 30 is contained in the upper shed 42, and cable 34 passes under shed 44.Guide pin 46 or spring 48 can be set on zone outside the upper shed 42 of base 40.Each guide pin 46 is inserted in the pilot hole 16 of the through hole 26 of supporting bracket 20 and lead frame 10 simultaneously.Spring 48 resilient connection supporting brackets 30 and base 40, so just supporting bracket 20 can move up and down.The hole 28 that connects spring 48 can be set on supporting bracket 20 in addition.And, fastener 45 and corresponding hole 35 can be set, so that substrate 30 is installed in the upper shed 42 of base 40 securely respectively on base 40 and substrate 30.Base 40 is preferably by constituting as the material of low thermal coefficient of expansion such as glass fibre (TEC), thereby making it to avoid testing time produces hot influence.
And labour has the lid 50 of pushing lead frame 10 downwards on lead frame 10.On the lower surface of gland 50, be formed with cavity 52 and groove 56, shown in Fig. 3 to 4B.When gland 50 is pushed lead frame 10, can connect the line 14 of the lead-in wire 12 of chip 1 and lead frame 10 by cavity 52 protections.Each groove 56 matches with each guide pin 46 that passes pilot hole 16 and through hole 26.Gland 50 is made of electrically non-conductive material.
Groove 56 shown in Figure 3, the guide pin 46 on the base 40, the pilot hole 16 in the lead frame 10 and the through hole 26 in the supporting bracket 20 are aimed at.In addition, critical piece shown in Figure 1 is that base 40, substrate 30, supporting bracket 20, lead frame 10 and gland 50 flatly are installed together.Particularly, because the lead-in wire 12 of unpackaged chip 1 and lead frame 10 places on the same horizontal plane, and carried out the lead-in wire bonding, so can very stably carry out test of the present invention.
Fig. 3 schematically shows whole testing device 100 of the present invention, and Fig. 4 A and 4B show the technical process of the testing apparatus 100 test non-packaged semiconductor chips 1 that utilize Fig. 3.The critical piece of the testing apparatus shown in Fig. 1 combines, as shown in Figure 3.Among Fig. 3, testing apparatus 100 also comprises the device 60 that drives gland 50.Drive unit 60 is fixed on the gland 50. Reference number 60,62,64 among Fig. 3 is drive unit and relevant parts with 66 expressions.Be detailed description below to this.
Shown in Fig. 3 to 4B, comprise protective layer 32, be inserted in the upper shed 42 of base 40 as shown in Figure 1 as the test probe 33 of spring stilt pin and the substrate 30 of cable 34.Lead frame 10 on the supporting bracket 20 places between substrate 30 and the gland 50.Spring 48 is flexibly supporting supporting bracket 20, and gland 50 is to support movably.It below is explanation to gland 50.
Lead-in wire 12 and chip 1 come out by the window 22 of supporting bracket 20.Because the size of window 22 is greater than the protective layer on the substrate 30 32, so when lead frame 10 moved down, test probe 33 can contact with the lead-in wire 12 in the window 22.When gland 50 was pushed lead frame 10, the size of the cavity 52 of gland 50 was enough to and wherein chip 1, line 14 and adhesive tape 8 match.And, in order to distribute the heat that chip 1 produces effectively,, can be formed with opening on substrate 30 and the protective layer 32 although not shown.As mentioned above, the guide pin 46 on the base 40 passes supporting bracket 20 and lead frame 10, and is inserted in the groove 56 of gland 50.
During drive unit 60 work, gland 50 moves down, and pushes lead frame 10.Therefore, in spring shown in Figure 3 48 compression, the lead frame 10 on the supporting bracket 20 also moves down, and contacts with test probe 33 on the substrate 30 then, thereby can carry out suitable test process.After the test, drive unit 60 moves in the opposite direction, and gland 50 recovers original position.Lead frame 10 also resets by the spring 48 that connects with supporting bracket 20.
Fig. 5 shows the basal surface of the substrate 30 of testing apparatus.As shown in Figure 5, substrate 30 has a plurality of test probes hole 33a, cable aperture 34a and the hole 35 of fixing base 30 on base.Be formed with two cable aperture 34a corresponding to each probe aperture 33a.Two cable aperture 34a insert the input and output cable respectively.Reference number 37 expressions connect the line of test probe and cable.
Fig. 6 A and 6B show the running of the gland 50 of testing apparatus.Referring to Fig. 6 A and 6B, drive unit 60 can be by cylinder operated connecting rod.Guiding parts 66 extends vertically up to gland 50, and skewed slot 68 is wherein arranged.Gland 50 is fixed on the drive unit 60 by skewed slot 68 by link 62,64.Therefore, when drive unit 60 is mobile vertically, gland 50 along the inclination angle of groove 68 with respect to lopsidedness move up and down, be convenient to the load or the unloading of lead frame 10.
After this, will describe another embodiment of the present invention in detail.Fig. 7 is that the part of the critical piece of another non-packaged semiconductor chip testing apparatus of the present invention splits decomposition diagram, and Fig. 8 shows the main parts size of the testing apparatus 200 of Fig. 7.Among Fig. 7 and 8, the parts that present embodiment is identical with previous embodiment are represented with identical reference number.Therefore, no longer describe these identical parts in detail, the below main difference that is noted that between the two.
Among Fig. 7 and 8, comprise that the lead frame 110 of a unpackaged chip 1 can be placed on the supporting bracket 20.In addition, the opening number of base 50 is greater than the quantity that will survey chip 1.Therefore, can be with independent lead frame 110 independent test chips 1.Elastic bending lead-in wire 133 also is the characteristics of present embodiment.Bending lead 133 replaces the spring stilt pin in the previous embodiment as test probe.In this case, do not form parts such as protective layer in the previous embodiment for example.Because bending lead 133 has elastic force, institute can be through reducing through its length.Therefore, because the signal path shortening, so can improve electrical property.
Each drawing and description discloses typical preferred embodiment of the present invention, although above-mentionedly used particular term in open, they are just general and illustrative, is not in order to limit, and following claims have been set forth scope of the present invention.

Claims (13)

1. device of testing non-packaged semiconductor chip comprises:
The lead frame that has many lead-in wires electrically isolated from one, described lead-in wire reality is supported by nonconducting adhesive tape, wherein has the semiconductor chip that will test at least by many lines and described every lead-in wire bonding;
Support the plate of described lead frame, described supporting bracket is formed with a plurality of windows, in order to expose the described lead-in wire of described lead frame by them;
At least one substrate, described substrate has a plurality of test probes, test probe contacts with every described lead-in wire of described lead frame respectively by the window of described supporting bracket, and described substrate also has the many cables that connect described test probe and test signal generation circuit;
Have a plurality of bases that hold the upper shed of described substrate, described base also has a plurality of under sheds that described cable passes that are used for, and wherein said upper shed is greater than described under shed, so that described substrate can insert described upper shed, and is loaded on wherein; And
Push the lid that described lead-in wire that described lead frame makes described lead frame can contact with the described probe of described substrate, described gland has the cavity of a described line of protection at least.
2. according to the testing apparatus of claim 1, also comprise:
Drive the device of described gland, described drive unit is fixed on the described gland, thereby described gland can move up and down.
3. according to the testing apparatus of claim 2, it is characterized in that, described base comprises a guide at least, this guide extends to described gland, and wherein has a skewed slot at least, described gland is fixed on the described drive unit by the skewed slot in the described guide, thereby described gland can move up and down obliquely.
4. according to the testing apparatus of claim 1, also comprise:
At least one guide pin outside the above upper shed of described base has a pilot hole that inserts described guide pin at least in the wherein said lead frame.
5. according to the testing apparatus of claim 4, it is characterized in that described gland comprises a groove that inserts the described guide pin on the described base at least.
6. according to the testing apparatus of claim 5, it is characterized in that, comprise a through hole that inserts the described guide pin on the described base in the described supporting bracket at least.
7. according to the testing apparatus of claim 6, it is characterized in that the groove of the described guide pin on the described base, the pilot hole in the described lead frame, described gland and the through hole in the described supporting bracket are aimed at.
8. according to the testing apparatus of claim 1, it is characterized in that described lead frame comprises one group of lead-in wire at least, every group of lead-in wire belongs to a block semiconductor chip that is bonded on the described lead-in wire respectively.
9. testing apparatus according to Claim 8 is characterized in that, every group of lead-in wire separates each other.
10. testing apparatus according to Claim 8 is characterized in that, every group of lead-in wire comprises the pad that described semiconductor chip is installed thereon respectively.
11. the testing apparatus according to claim 1 is characterized in that, described substrate comprises the protective layer that has a plurality of probe aperture, can insert the described test probe of described substrate in the probe aperture respectively.
12. the testing apparatus according to claim 1 is characterized in that, described test probe is spring stilt pin or elastic bending lead-in wire.
13. the testing apparatus according to claim 1 is characterized in that, described base comprises the spring of a described supporting bracket of resilient connection at least.
CN97104304A 1996-05-10 1997-05-04 Testing apparatus for non-packaged semiconductor chip Expired - Lifetime CN1103495C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1019960015463A KR0175268B1 (en) 1996-05-10 1996-05-10 Bare chip test device with horizontal top-down connection
KR15463/1996 1996-05-10
KR15463/96 1996-05-10

Publications (2)

Publication Number Publication Date
CN1165401A true CN1165401A (en) 1997-11-19
CN1103495C CN1103495C (en) 2003-03-19

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CN97104304A Expired - Lifetime CN1103495C (en) 1996-05-10 1997-05-04 Testing apparatus for non-packaged semiconductor chip

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US (1) US5990692A (en)
JP (1) JP3014338B2 (en)
KR (1) KR0175268B1 (en)
CN (1) CN1103495C (en)
DE (1) DE19718870B4 (en)
TW (1) TW455977B (en)

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