CN116482494B - Chip type multilayer ceramic capacitor test fixture - Google Patents
Chip type multilayer ceramic capacitor test fixture Download PDFInfo
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- CN116482494B CN116482494B CN202310289898.8A CN202310289898A CN116482494B CN 116482494 B CN116482494 B CN 116482494B CN 202310289898 A CN202310289898 A CN 202310289898A CN 116482494 B CN116482494 B CN 116482494B
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- ceramic capacitor
- product fixing
- multilayer ceramic
- type multilayer
- motherboard
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- 239000003985 ceramic capacitor Substances 0.000 title claims abstract description 97
- 238000012360 testing method Methods 0.000 title claims abstract description 66
- 239000000523 sample Substances 0.000 claims abstract description 89
- 125000006850 spacer group Chemical group 0.000 claims description 11
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000004308 accommodation Effects 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 11
- 230000008569 process Effects 0.000 abstract description 8
- 238000003466 welding Methods 0.000 abstract description 5
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910001172 neodymium magnet Inorganic materials 0.000 description 2
- 229920000049 Carbon (fiber) Polymers 0.000 description 1
- QJVKUMXDEUEQLH-UHFFFAOYSA-N [B].[Fe].[Nd] Chemical compound [B].[Fe].[Nd] QJVKUMXDEUEQLH-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000004917 carbon fiber Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
- G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
The application provides a chip type multilayer ceramic capacitor test fixture, which comprises a mother board, a loading conductive plate, a product fixing gasket and a daughter board, wherein the mother board is provided with a plurality of mounting holes; the motherboard is provided with a plurality of first probes, two sides of the loading conductive plate are respectively provided with a plurality of first electrodes and second electrodes which are mutually corresponding, each first electrode is electrically connected with the corresponding second electrode, and each first electrode is respectively abutted with the corresponding first probe; the product fixing gasket is provided with a plurality of containing holes for containing the chip type multilayer ceramic capacitor to be tested; the product fixing gasket is arranged on one side where the second electrode of the loading conductive plate is located; the daughter board is provided with a plurality of second probes which respectively correspond to the containing holes on the product fixing gasket, and the tail ends of the second probes and the second electrodes are respectively abutted with the two poles of the chip type multilayer ceramic capacitor in the containing holes. Compared with the prior art, the chip type multilayer ceramic capacitor to be tested is electrically connected with the testing equipment through the probe, welding is not needed, and the testing process is more efficient.
Description
Technical Field
The application relates to the technical field of electronic component testing, in particular to a chip type multilayer ceramic capacitor testing jig.
Background
HALT (Highly Accelerated Life Test, high accelerated life test) is a method for rapidly finding out the design defects, operational margin, structural strength and other limit properties of a product by applying a step stress to the product, and improving the design defects, operational margin, structural strength and other limit properties of the product, thereby increasing the limit value of the product and improving the firmness and reliability of the product. Stresses applied to the product include vibration, high and low temperatures, temperature cycling, integrated stresses, and the like. In the prior art, the chip type multilayer ceramic capacitors (MLCC for short) are electrically connected with test equipment in a welding mode, and as the number of the chip type multilayer ceramic capacitors tested in each batch is large, the welding of the chip type multilayer ceramic capacitors needs to consume a long time, so that the HALT test efficiency of the chip type multilayer ceramic capacitors is seriously affected.
Disclosure of Invention
In order to solve the technical problems, the application provides a chip type multilayer ceramic capacitor test fixture for improving the efficiency of connecting a chip type multilayer ceramic capacitor to be tested with test equipment.
The application relates to a chip type multilayer ceramic capacitor test fixture, which comprises a mother board, a loading conductive plate, a product fixing gasket and a daughter board;
the motherboard is provided with a plurality of first probes, two sides of the loading conductive plate are respectively provided with a plurality of first electrodes and second electrodes which are mutually corresponding, each first electrode is electrically connected with the corresponding second electrode, and each first electrode is respectively abutted with the corresponding first probe;
the product fixing gasket is provided with a plurality of containing holes penetrating through two sides of the product fixing gasket, the containing holes are used for containing the chip type multilayer ceramic capacitor to be tested, and two ends of the chip type multilayer ceramic capacitor face two sides of the product fixing gasket respectively; the product fixing gasket is arranged on one side of the loading conductive plate where the second electrode is;
the daughter board is provided with a plurality of second probes, the positions of the second probes respectively correspond to the accommodating holes in the product fixing gasket, and the tail ends of the second probes and the second electrodes are respectively abutted against the two poles of the chip type multilayer ceramic capacitor in the accommodating holes.
Further, each of the second electrodes is abutted against the chip-type multilayer ceramic capacitor in the plurality of accommodation holes.
Further, a connector is further arranged on the motherboard, and each first probe is electrically connected with the connector respectively.
Further, the motherboard is further provided with a plurality of resistors corresponding to the first probes respectively, and each first probe is electrically connected with the connector through the corresponding resistor.
Further, the probe card further comprises a connecting piece for connecting the mother board and the daughter board, and each second probe is electrically connected with the connector through the connecting piece.
Further, the device also comprises a plurality of first limiting blocks and a plurality of second limiting blocks;
each first limiting block is arranged between the motherboard and the loading conducting plate, and each first limiting block is respectively abutted with the motherboard and the loading conducting plate;
each second limiting block is arranged between the product fixing gasket and the daughter board and is respectively abutted with the product fixing gasket and the daughter board.
Further, each connecting piece is a conductive bolt, and each connecting piece passes through the mother board, the first limiting block, the loading conductive plate, the product fixing gasket, the second limiting block and the daughter board.
Further, the packaging box further comprises a first support and a second support, wherein the first support is arranged on one side, far away from the loading conducting plate, of the motherboard, and the second support is arranged on one side, far away from the product fixing gasket, of the daughter board.
Further, the device also comprises a bearing gasket, wherein the bearing gasket is arranged on one side of the motherboard, which is close to the loading conductive plate; and through holes corresponding to the first probes are formed in the bearing gaskets, and the first probes penetrate through the corresponding through holes.
Further, the loading conductive plate and the product fixing spacer each include a plurality of pieces, and each loading conductive plate corresponds to each product fixing spacer in shape and position.
Compared with the prior art, the application has the following beneficial technical effects:
1. the chip type multilayer ceramic capacitor to be tested is electrically connected with the testing equipment through the probe, welding is not needed, and the testing process is more efficient;
2. each second electrode on the loading conductive plate is electrically connected with a plurality of chip type multilayer ceramic capacitors, thereby increasing the number of chip type multilayer ceramic capacitors tested at a time;
3. the motherboard is provided with a plurality of resistors respectively corresponding to the first probes, and the first probes are electrically connected with the connector through the corresponding resistors so as to prevent overlarge current caused when the chip type multilayer ceramic capacitor is subjected to breakdown short circuit.
Drawings
FIG. 1 is a diagram showing an assembled state structure of a chip multi-layer ceramic capacitor test fixture according to the present application;
FIG. 2 is an exploded view of the chip multi-layer ceramic capacitor test fixture of the present application;
FIG. 3 is an exploded view of the chip multi-layer ceramic capacitor test fixture of the present application;
FIG. 4 is a cross-sectional view along a vertical plane of the chip multi-layer ceramic capacitor test fixture of the present application;
fig. 5 is a structural view of a loading conductive plate and a product fixing pad of the chip multi-layered ceramic capacitor test fixture of the present application.
In the figure:
10. a first bracket;
20. a motherboard; 21. a first probe; 22. a connector; 23. a resistor slot;
30. a bearing gasket;
40. loading a conductive plate; 41. a first electrode; 42. a second electrode;
50. a product fixing gasket;
60. a sub-board; 61. a second probe;
70. a second bracket;
80. a connecting piece;
91. a first limiting block; 92. a second limiting block;
A. chip type multilayer ceramic capacitor.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the following detailed description of the embodiments of the present application will be given with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the application, are intended to be within the scope of the embodiments of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application as detailed in the accompanying claims. In the description of the present application, it should be understood that the terms "first," "second," "third," and the like are used merely to distinguish between similar objects and are not necessarily used to describe a particular order or sequence, nor should they be construed to indicate or imply relative importance. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
Furthermore, in the description of the present application, unless otherwise indicated, "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
The application provides a chip type multi-layer ceramic capacitor test fixture, which comprises a mother board 20, a loading conductive board 40, a product fixing gasket 50 and a daughter board 60, as shown in fig. 1-4.
Specifically, the motherboard 20 is provided with a plurality of first probes 21, and the two surfaces of the loading conductive plate 40 are respectively provided with a plurality of first electrodes 41 and second electrodes 42 corresponding to each other, wherein each first electrode 41 is electrically connected with the corresponding second electrode 42, and each first electrode 41 is respectively abutted against the corresponding first probe 21.
The product fixing gasket 50 is provided with a plurality of containing holes penetrating through two sides of the product fixing gasket, the containing holes are used for containing the chip type multilayer ceramic capacitor A to be tested, two ends of the chip type multilayer ceramic capacitor A face two sides of the product fixing gasket 50 respectively, and two electrodes of the chip type multilayer ceramic capacitor A are arranged at two ends of the chip type multilayer ceramic capacitor A respectively, so that the two electrodes of the chip type multilayer ceramic capacitor A face two sides of the product fixing gasket 50 respectively; the product fixing spacer 50 is disposed at a side of the loading conductive plate 40 where the second electrode 42 is located.
The daughter board 60 is provided with a plurality of second probes 61, the positions of the second probes 61 respectively correspond to the accommodating holes in the product fixing pad 50, and the tail ends of the second probes 61 and the second electrodes 42 respectively abut against the two poles of the chip-type multilayer ceramic capacitor A in the accommodating holes.
In order to improve the high temperature resistance of the test fixture to accommodate the high temperature test environment, in a preferred embodiment, the motherboard 20 and the daughter board 60 are formed from a high temperature resistant TG-FR4 board.
In a specific embodiment, each first probe 21 is a positive electrode probe and each second probe 61 is a negative electrode probe; in other embodiments, each first probe 21 is a negative electrode probe and each second probe 61 is a positive electrode probe.
In order to increase the number of chip type multilayer ceramic capacitors a that can be simultaneously detected, the space on the test jig for the chip type multilayer ceramic capacitors a is fully utilized, and in a preferred embodiment, each of the second electrodes 42 corresponds to a plurality of receiving holes, whereby each of the second electrodes 42 abuts against the chip type multilayer ceramic capacitors a in the plurality of receiving holes when the chip type multilayer ceramic capacitors a are mounted.
The number of second probes 61 is greater than the number of first probes 21, and the current passing through each first probe 21 is greater than the current passing through each second probe 61. In a preferred embodiment, the diameter of the first probe 21 is greater than the diameter of the second probe 61 to provide a more uniform current carrying capacity of the probes.
In order to facilitate connection of each first probe 21 to external test equipment, in a preferred embodiment, a connector 22 is also provided on the motherboard 20, each first probe 21 being electrically connected to a connector 22, respectively. In a specific embodiment, the connector 22 includes a plurality of gold fingers formed at an edge of the motherboard 20, and each of the first probes 21 is electrically connected to a corresponding gold finger; in another specific embodiment, the connector 22 includes a plurality of pins disposed on the motherboard 20, and each of the first probes 21 is electrically connected to a corresponding pin.
Thus, a plurality of stations are respectively formed between each second electrode 42 and the corresponding second probe 61, and each station can accommodate a plurality of chip type multilayer ceramic capacitors A, and the second electrode 42 of each station is respectively connected with the connector 22, so that external testing equipment can respectively and independently detect and control the voltage output to each station.
Because the circuit connected between the external test equipment and each station can generate voltage loss, the test voltage output by the external test equipment is not equal to the voltage on each station, so that the voltage between two poles of the chip multilayer ceramic capacitor A on each station is lower than the test voltage output by the tester; in the technical scheme of the application, the second electrodes 42 of the stations are respectively and electrically connected with the connector 22, and the stations are mutually independent, so that the second electrodes 42 of the stations can be respectively and electrically connected with external testing equipment, the voltage output to the stations by the external testing equipment can be respectively adjusted according to the loss condition, and the voltage on the stations can be monitored in real time, thereby reducing the error of the output voltage and improving the accuracy of the testing result.
If the chip type multilayer ceramic capacitor A breaks down in the test process, two groups of polar plates in the chip type multilayer ceramic capacitor A are directly and electrically connected to generate short circuit, the current flowing through a circuit loop of the chip type multilayer ceramic capacitor A can be increased, and corresponding electronic elements on the circuit loop are easily damaged; in order to avoid breakdown of the chip-type multilayer ceramic capacitor a, which leads to damage of electronic components on a circuit in which the chip-type multilayer ceramic capacitor a is located, in a preferred embodiment, the motherboard 20 is further provided with a plurality of resistors corresponding to the respective first probes 21, and the respective first probes 21 are electrically connected to the connector 22 through the corresponding resistors; thus, even if the chip multilayer ceramic capacitor a breaks down, the resistor connected in series with it can prevent an excessive current flowing through the circuit loop, thereby preventing damage to the corresponding electronic component.
When the chip type multilayer ceramic capacitor A with different specifications is tested, the specifications of the resistors to be connected are also different; to facilitate the replacement of resistors of different specifications to accommodate different test requirements, in a preferred embodiment, the motherboard 20 is further provided with resistor sockets 23 for mounting resistors to facilitate the mounting and dismounting of the resistors.
To facilitate electrical connection of each second probe 61 to the test equipment, in a preferred embodiment, further comprising a connector 80 connecting motherboard 20 and daughterboard 60, each second probe 61 being electrically connected to connector 22 by connector 80; thus, each of the first probes 21 and each of the second probes 61 are connected to the testing apparatus through the connector 22, so that the testing process is more convenient. In other embodiments, connectors may also be provided on the daughter board 60, such that each second probe 61 on the daughter board 60 may be electrically connected to the test equipment through the connectors on the daughter board 60.
If the distance between the motherboard 20 and the loading conductive plate 40 is too large, the pressure applied by the first probe 21 to the first electrode 41 on the loading conductive plate 40 is too small, which may cause poor contact between the first probe 21 and the first electrode 41, affecting the test result; if the distance between the motherboard 20 and the loading conductive plate 40 is too small, the first probe 21 applies too much pressure to the first electrode 41 on the loading conductive plate 40, which may cause damage to the first probe 21 and the first electrode 41; thus, in order to prevent the first electrode 41 from being damaged due to excessive pressure even when good electrical contact is maintained, in a preferred embodiment, a plurality of first stoppers 91 are further provided, each of the first stoppers 91 being provided between the motherboard 20 and the loading conductive plate 40, and each of the first stoppers 91 being in contact with the motherboard 20 and the loading conductive plate 40, respectively, thereby maintaining a proper distance between the motherboard 20 and the loading conductive plate 40 and causing the first probe 21 to apply a proper pressure to the first electrode 41. Preferably, each first stopper 91 is disposed along the edges of the motherboard 20 and the loading conductive plate 40 to avoid occupying the space of each first probe 21.
If the distance between the product fixing pad 50 and the sub-board 60 is too large, the pressure applied by the second probe 61 to the chip type multilayer ceramic capacitor a is too small, which may cause poor contact between the second probe 61 and the chip type multilayer ceramic capacitor a, and between the chip type multilayer ceramic capacitor a and the second electrode 42 on the loading conductive board 40, affecting the test result; if the distance between the product fixing pad 50 and the sub-board 60 is too small, the second probe 61 applies too much pressure to the chip type multilayer ceramic capacitor a, possibly resulting in damage to the second probe 61, the chip type multilayer ceramic capacitor a, and the second electrode 42 on the loading conductive plate 40; thus, in order to prevent the chip multilayer ceramic capacitor a from being damaged due to excessive pressure even when good electrical contact is maintained, in a preferred embodiment, the chip multilayer ceramic capacitor a further includes second stoppers 92, each of which is provided between the product fixing pad 50 and the daughter board 60, and each of which second stoppers 92 abuts against the product fixing pad 50 and the daughter board 60, thereby maintaining a proper distance between the product fixing pad 50 and the daughter board 60 and causing the second probe 61 to apply a proper pressure to the chip multilayer ceramic capacitor a. Preferably, each second limiting block 92 is disposed along the edges of the product fixing pad 50 and the daughter board 60, so as to avoid occupying the space of each second probe 61.
In a preferred embodiment, each connector 80 is a conductive bolt, and each connector 80 passes through the motherboard 20, the first stopper 91, the load conductive plate 40, the product fixing spacer 50, the second stopper 92, and the daughter board 60; accordingly, the connector 80 can electrically connect the second probe 61 on the daughter board 60 with the connector 22 on the motherboard 20, and can fix the motherboard 20, the first stopper 91, the loading conductive plate 40, the product fixing spacer 50, the second stopper 92, and the daughter board 60, and one component can realize two functions, thereby making the structure of the chip-type multilayer ceramic capacitor a fixture of the present application more compact.
Each first probe 21 is provided on the motherboard 20, and if the motherboard 20 is deformed, the first probes 21 are displaced, so that poor contact between the first probes 21 and the first electrodes 41 is caused, and the test result is affected; accordingly, in order to solve the above technical problems, in a preferred embodiment, the first bracket 10 is further included, and the first bracket 10 is disposed at a side of the motherboard 20 remote from the loading conductive plate 40, thereby increasing the rigidity of the motherboard 20 and preventing the motherboard 20 from being deformed. In one particular embodiment, the first stent 10 is a carbon fiber composite diamond stent, which has the advantages of being lightweight, non-conductive, high temperature resistant, and non-deformable.
Each of the second probes 61 is provided on the sub-board 60, and if the sub-board 60 is deformed, the second probes 61 are displaced, so that poor contact occurs between the second probes 61 and the chip type multilayer ceramic capacitor a, and between the chip type multilayer ceramic capacitor a and the second electrode 42, thereby affecting the test result; accordingly, in order to solve the above technical problems, in a preferred embodiment, the second bracket 70 is further included, and the second bracket 70 is disposed at a side of the sub-board 60 remote from the product fixing spacer 50, thereby increasing the rigidity of the sub-board 60 and preventing the sub-board 60 from being deformed.
In the actual testing process, the motherboard 20 is disposed below, so that the motherboard 20 also needs to bear the gravity applied by the components above the motherboard, such as the loading conductive plate 40, the product fixing pad 50, the daughter board 60, and the like; in order to enhance the carrying capacity of the motherboard 20, in a preferred embodiment, the motherboard further comprises a carrying pad 30, wherein the carrying pad 30 is disposed on a side of the motherboard 20 near the carrying conductive plate 40, and the carrying pad 30 is provided with through holes corresponding to the first probes 21, and the first probes 21 pass through the corresponding through holes.
Before testing the chip type multilayer ceramic capacitor A, the chip type multilayer ceramic capacitor A is required to be arranged in the accommodating hole of the product fixing gasket, and the preparation flow before testing the chip type multilayer ceramic capacitor A is specifically as follows:
s1: the loading conductive plate 40 is horizontally arranged, the surface of the first electrode 41 is positioned below, and the surface of the second electrode 42 is positioned above;
s2: disposing the product fixing spacer 50 above the loading conductive plate 40;
s3: pouring a plurality of chip type multilayer ceramic capacitors A to be tested above the product fixing gasket 50, enabling the magnet to move below the loading conducting plate 40, and enabling the chip type multilayer ceramic capacitors A to fall into the accommodating holes of the product fixing gasket 50 under the action of magnetic attraction;
s4: combining the components in the order of the mother board 20, the first limiting block 91, the loading conductive plate 40, the product fixing spacer 50, the second limiting block 92 and the daughter board 60 from bottom to top, and fixing the components through the connecting piece 80;
s5: the chip multi-layer ceramic capacitor a starts to be tested by electrically connecting the connector 22 on the motherboard 20 with the test equipment.
In the prior art, the chip type multilayer ceramic capacitor A is generally dropped into the accommodating hole on the product fixing gasket 50 by a mechanical vibration method, and the mechanical vibration can apply a large force to the chip type multilayer ceramic capacitor A, so that the chip type multilayer ceramic capacitor A is easy to deform and damage, and the accuracy of a test result is influenced; in this embodiment, the chip type multilayer ceramic capacitor a is dropped into the accommodating hole on the product fixing pad 50 by the adsorption of magnetic force, so as to reduce the stress of the chip type multilayer ceramic capacitor a and prevent the chip type multilayer ceramic capacitor a from being deformed or damaged, so that the test result is more accurate. Preferably, the magnet in step S3 is a strong neodymium-iron-boron magnet.
In order to test a plurality of chip type multilayer ceramic capacitors A at the same time, the containing holes on the product fixing gasket 50 are very many, the chip type multilayer ceramic capacitors A to be tested are loaded into the containing holes on the product fixing gasket 50, so that the process of arranging the chip type multilayer ceramic capacitors A in each containing hole is complex, and the operation efficiency is low; thus, in a preferred embodiment, as shown in FIG. 5, the load conductive plates 40 and the product retention shims 50 each comprise a plurality of pieces, and each load conductive plate 40 corresponds to the shape and location of each product retention shim 50; thus, the process of mounting each product fixing pad 50 into the chip type multilayer ceramic capacitor A can be performed simultaneously, and the efficiency of mounting the chip type multilayer ceramic capacitor A on the product fixing pad 50 can be improved.
Compared with the prior art, the application has the following beneficial technical effects:
1. the chip type multilayer ceramic capacitor A to be tested is electrically connected with the testing equipment through the probe, welding is not needed, and the testing process is more efficient;
2. each second electrode on the loading conductive plate is electrically connected to the plurality of chip type multilayer ceramic capacitors a, thereby increasing the number of chip type multilayer ceramic capacitors a tested at a time;
3. the motherboard is provided with a plurality of resistors which respectively correspond to the first probes, and the first probes are electrically connected with the connector through the corresponding resistors so as to prevent overlarge current caused when the ceramic capacitor A breaks down and is in short circuit;
4. each station is electrically connected with the testing machine, the stations are mutually independent, the voltage output to each station by external testing equipment can be respectively adjusted according to the loss condition, and the voltage on each station can be monitored in real time, so that the error of the output voltage is reduced, and the accuracy of the testing result is improved.
5. The chip type multilayer ceramic capacitor is adsorbed by utilizing the magnetic force of the neodymium iron boron strong magnet, so that the chip type multilayer ceramic capacitor falls into the accommodating hole of the product fixing gasket, the stress of the chip type multilayer ceramic capacitor A is reduced, the chip type multilayer ceramic capacitor A is prevented from being deformed or damaged, and the test result is more accurate.
It is to be understood that the embodiments of the application are not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be made without departing from the scope thereof. The scope of embodiments of the application is limited only by the appended claims.
The above examples merely represent a few implementations of the present examples, which are described in more detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that various modifications and improvements can be made to the present application without departing from the spirit of the embodiments of the application.
Claims (9)
1. A chip type multilayer ceramic capacitor test fixture is characterized in that:
comprises a mother board (20), a loading conductive board (40), a product fixing gasket (50) and a daughter board (60);
a plurality of first probes (21) are arranged on the motherboard (20), a plurality of first electrodes (41) and second electrodes (42) which are mutually corresponding are respectively arranged on two sides of the loading conductive plate (40), each first electrode (41) is electrically connected with the corresponding second electrode (42), and each first electrode (41) is respectively abutted against the corresponding first probe (21);
the product fixing gasket (50) is provided with a plurality of containing holes penetrating through two sides of the product fixing gasket, the containing holes are used for containing the chip type multilayer ceramic capacitor (A) to be tested, and two ends of the chip type multilayer ceramic capacitor (A) face two sides of the product fixing gasket (50) respectively; the product fixing spacer (50) is disposed on a side of the loading conductive plate (40) where the second electrode (42) is located;
a plurality of second probes (61) are arranged on the daughter board (60), the positions of the second probes (61) respectively correspond to the accommodating holes on the product fixing gasket (50), and the tail end of each second probe (61) is abutted with the chip type multilayer ceramic capacitor (A) in each accommodating hole; each of the second electrodes (42) is in contact with the chip-type multilayer ceramic capacitor (A) in the plurality of accommodation holes.
2. The chip multi-layer ceramic capacitor test fixture according to claim 1, wherein:
the motherboard (20) is also provided with connectors (22), and each first probe (21) is electrically connected with the connector (22) respectively.
3. The chip multi-layer ceramic capacitor test fixture according to claim 2, wherein:
the motherboard (20) is also provided with a plurality of resistors corresponding to the first probes (21), and each first probe (21) is electrically connected with the connector (22) through the corresponding resistor.
4. The chip multi-layer ceramic capacitor test fixture according to claim 3, wherein:
and a connector (80) connecting the motherboard (20) and the daughter board (60), each of the second probes (61) being electrically connected to the connector (22) through the connector (80).
5. The chip multi-layer ceramic capacitor test fixture according to claim 4, wherein:
the device also comprises a plurality of first limiting blocks (91) and a plurality of second limiting blocks (92);
each first limiting block (91) is arranged between the motherboard (20) and the loading conductive plate (40), and each first limiting block (91) is respectively abutted with the motherboard (20) and the loading conductive plate (40);
each second limiting block (92) is arranged between the product fixing gasket (50) and the daughter board (60), and each second limiting block (92) is respectively abutted with the product fixing gasket (50) and the daughter board (60).
6. The chip multi-layer ceramic capacitor test fixture according to claim 5, wherein:
each connecting piece (80) is a conductive bolt, and each connecting piece (80) passes through the mother board (20), the first limiting block (91), the loading conductive plate (40), the product fixing gasket (50), the second limiting block (92) and the daughter board (60).
7. The chip multi-layer ceramic capacitor test fixture according to any one of claims 1 to 6, wherein:
the novel packaging box further comprises a first support (10) and a second support (70), wherein the first support (10) is arranged on one side, far away from the loading conducting plate (40), of the motherboard (20), and the second support (70) is arranged on one side, far away from the product fixing gasket (50), of the daughter board (60).
8. The chip multi-layer ceramic capacitor test fixture according to any one of claims 1 to 6, wherein:
the device further comprises a bearing gasket (30), wherein the bearing gasket (30) is arranged on one side of the motherboard (20) close to the loading conductive plate (40); the bearing pad (30) is provided with through holes corresponding to the first probes (21), and each first probe (21) passes through the corresponding through hole.
9. The chip multi-layer ceramic capacitor test fixture according to any one of claims 1 to 6, wherein:
the loading conductive plates (40) and the product fixing spacers (50) each include a plurality of pieces, and each loading conductive plate (40) corresponds to the shape and position of each product fixing spacer (50).
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310289898.8A CN116482494B (en) | 2023-03-22 | 2023-03-22 | Chip type multilayer ceramic capacitor test fixture |
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| CN202310289898.8A CN116482494B (en) | 2023-03-22 | 2023-03-22 | Chip type multilayer ceramic capacitor test fixture |
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| CN116482494B true CN116482494B (en) | 2023-11-21 |
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| Publication number | Publication date |
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| CN116482494A (en) | 2023-07-25 |
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