CN115267480A - Testing device - Google Patents
Testing device Download PDFInfo
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- CN115267480A CN115267480A CN202111619098.5A CN202111619098A CN115267480A CN 115267480 A CN115267480 A CN 115267480A CN 202111619098 A CN202111619098 A CN 202111619098A CN 115267480 A CN115267480 A CN 115267480A
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- circuit board
- chip
- main body
- test
- connecting pieces
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The application discloses testing arrangement, wherein, testing arrangement includes: the test device comprises a motherboard, a test device and a test system, wherein a plurality of test areas are arranged on the motherboard; the daughter boards respectively comprise a chip mounting circuit board and a peripheral circuit integrated circuit board which are detachably connected; each daughter board is correspondingly detachably connected with a test area on the motherboard through the chip mounting circuit board. Through the structure, the test device can flexibly replace the chip mounting circuit board and the peripheral circuit integrated circuit board to deal with different chip tests by utilizing the detachable connection of the chip mounting circuit board and the peripheral circuit integrated circuit board, so that the whole daughter board is prevented from being replaced to realize the tests of different chips, the compatibility of the test device is improved, the manufacturing cost and the time of the daughter board are reduced, and the efficiency of the chip tests is improved.
Description
Technical Field
The application is applied to the technical field of processing test chips, in particular to a test device.
Background
Before the integrated circuit chips are produced in batches, the integrated circuit chips are generally subjected to an aging test (to ensure the service life and reliability of the chips) and a performance test (to test the functions and performance of the chips in batches), and the integrated circuit chips passing the aging test and the performance test can be defined as good products.
At present, different integrated circuit chips to be tested in the same package can be tested by using different daughter boards. The cost for designing and manufacturing a specific test daughter board for an integrated circuit chip is higher, the early preparation time for customizing the aging test daughter board is longer, and the test efficiency is reduced.
Disclosure of Invention
The application provides a testing device to solve the problem that testing device's daughter board cost is higher and change inconvenience.
In order to solve the above technical problem, the present application provides a testing apparatus, which includes: the test device comprises a motherboard, a test device and a test device, wherein a plurality of test areas are arranged on the motherboard; the daughter boards respectively comprise a chip mounting circuit board and a peripheral circuit integrated circuit board which are detachably connected; each daughter board is correspondingly detachably connected with a test area on the motherboard through the chip mounting circuit board.
Wherein, the chip mounting circuit board includes: the chip circuit board main body is detachably connected with the corresponding test area, and a plurality of metal holes are formed in one side, away from the motherboard, of the chip circuit board main body in an array manner; the chip socket is used for mounting a chip, and a plurality of contact pins are arranged on one side of the chip socket close to the chip circuit board main body and correspond to the plurality of metal holes; the chip socket is correspondingly inserted into the plurality of metal holes of the chip circuit board main body by the plurality of contact pins for connection.
The plurality of pins of the chip socket correspond to the plurality of metal holes of the chip circuit board main body one to one and are welded and fixed so as to be connected.
The test area is provided with a plurality of first connecting pieces, and the first connecting pieces are electrically connected with the motherboard; a plurality of second connecting pieces are arranged on one side of the chip circuit board main body of the chip mounting circuit board, which is close to the test area, corresponding to the plurality of first connecting pieces, and the plurality of second connecting pieces are electrically connected with the chip circuit board main body; the first connecting pieces are matched with the second connecting pieces in model number, so that the chip circuit board main body of the chip mounting circuit board is correspondingly detachably connected with the first connecting pieces in the testing area through the second connecting pieces.
Wherein, a plurality of first connecting pieces include the public seat of connector, and a plurality of second connecting pieces include the female seat of connector.
The side of the chip circuit board main body of the chip installation circuit board, which is far away from the test area, is also provided with a plurality of third connecting pieces, and the third connecting pieces are electrically connected with the chip circuit board main body; a plurality of fourth connecting pieces are arranged on the peripheral circuit integrated circuit board at positions corresponding to the plurality of third connecting pieces, and the plurality of fourth connecting pieces are electrically connected with the peripheral circuit integrated circuit board; the third connecting piece is matched with the fourth connecting piece in type, so that the chip circuit board main body of the chip installation circuit board is correspondingly detachably connected with the fourth connecting pieces of the peripheral circuit integrated circuit board through the third connecting pieces.
Wherein, a plurality of third connecting pieces include the female seat of connector, and a plurality of fourth connecting pieces include the public seat of connector.
Wherein, peripheral circuit integrated circuit board still includes: a peripheral circuit board main body connected to the chip mounting circuit board through a plurality of fourth connecting members; and the peripheral application circuit is used for assisting in testing the chip and is electrically connected with the peripheral circuit board main body.
Wherein, the peripheral circuit integrated circuit board is also provided with a through groove; the chip socket penetrates through the through groove on the peripheral circuit integrated circuit board to be connected with the chip circuit board main body.
The motherboard is also provided with a plurality of golden finger interfaces, the golden finger interfaces are used for connecting the test machine, and the golden finger interfaces are respectively electrically connected with the test areas.
The beneficial effects of the application are; different from the prior art, the test device can flexibly replace daughter boards by utilizing a plurality of detachably connected daughter boards and mother boards so as to aim at different types of chips, and further utilizes the detachable chip mounting circuit board and the peripheral circuit integrated circuit board to enable the daughter boards to flexibly replace the peripheral circuit integrated circuit to test different types of chips and flexibly replace the chip mounting circuit board to adapt to different packaged chips, thereby improving the compatibility and the adaptation degree of the daughter boards to the types of the chips, avoiding the daughter board reproduction caused by the mismatching of the chip mounting of the daughter boards and the peripheral circuit integrated circuit, further reducing the manufacturing cost and the time of the daughter boards, and improving the efficiency of chip testing.
Drawings
FIG. 1 is a schematic diagram of an exploded view of one embodiment of a test apparatus provided herein;
FIG. 2 is a schematic top view of an embodiment of the motherboard shown in FIG. 1.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that if directional indications (such as up, down, left, right, front, back, 8230; \8230;) are referred to in the embodiments of the present application, the directional indications are only used to explain the relative positional relationship between the components, the motion situation, etc. in a specific posture (as shown in the attached drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic diagram of an explosion structure of an embodiment of a testing apparatus provided in the present application.
The test apparatus 100 of the present embodiment includes: a motherboard 110 and a plurality of daughter boards 140. The motherboard 110 has a plurality of test areas 111 disposed thereon. In a specific application scenario, the plurality of test areas 111 on the motherboard 110 may be arranged in an array. In another specific application scenario, the plurality of test areas 111 on the motherboard 110 may also be arranged according to other arrangement rules, and the specific arrangement manner may be set based on an actual situation, which is not limited herein.
Each sub-board 140 includes a chip-mounting circuit board 120 and a peripheral circuit integrated circuit board 130, which are detachably connected, respectively. I.e., the chip-mounted circuit board 120 and the peripheral circuit integrated circuit board 130. The chip-mounted circuit board 120 is used for mounting a chip, and the peripheral circuit integrated circuit board 130 is used for auxiliary testing of the chip. When the chip-mounted circuit board 120 and the peripheral circuit integrated circuit board 130 are detachably mounted, when different types of chips are tested, the peripheral circuit integrated circuit board 130 and/or the chip-mounted circuit board 120 corresponding to the chips can be flexibly replaced based on the characteristics of the chips, so that the types of the chips and the packages of the chips are matched. The test apparatus 100 of the present embodiment only needs to be equipped with a plurality of peripheral circuit integrated circuit boards 130 and a chip mounting circuit board 120, and does not need to be equipped with a complete daughter board capable of handling all chip packages and chip contents.
Each daughter board 140 is detachably connected to a corresponding test area 111 on the motherboard 110 via the chip-mounted circuit board 120. The motherboard 110 may be connected to a plurality of daughter boards 140 simultaneously, so as to test a plurality of chips simultaneously, or may be connected to only one daughter board 140, so as to test only one chip, and the number of connections of the daughter boards 140 may be set based on actual requirements.
The detachable mounting of the chip-mounting circuit board 120 of each daughter board 140 and the motherboard 110 can further increase the flexible configuration of the test apparatus 100, so that the chip-mounting circuit board 120 and/or the peripheral circuit integrated circuit board 130 can be flexibly replaced when different types of chips are tested, the whole daughter board 140 of the test apparatus 100 does not need to be replaced or manufactured, the test efficiency is improved, the time cost is reduced, the capital for manufacturing or ordering new daughter boards 140 is saved, and the detachable mounting of the chip-mounting circuit boards 120 of the daughter boards 140 and the motherboard 110 has the characteristics of simple structure, convenient use and low cost.
In a specific application scenario, the testing apparatus 100 of the embodiment may test a chip connected to the chip-mounted circuit board 120 under the condition that the motherboard 110 is connected to the chip-mounted circuit board 120, and the chip-mounted circuit board 120 is connected to the peripheral circuit integrated circuit board 130. In particular, the chip may be burn-in tested, quality tested, or otherwise tested based on its testing requirements. When the type of the chip or the test requirement is changed, the test can be performed by directly replacing the type of the peripheral circuit integrated circuit board 130, so that the whole daughter board 140 is not replaced, the compatibility of the test device 100 is improved, and the whole number and the manufacturing cost of the daughter board 140 are reduced.
Through the structure, the testing device of the embodiment utilizes the plurality of daughter boards and the mother board which are detachably connected to enable the testing device to flexibly replace the daughter boards so as to aim at different types of chips, and further utilizes the detachable chip mounting circuit board and the peripheral circuit integrated circuit board to enable the daughter boards to flexibly replace the peripheral circuit integrated circuit to test different types of chips and flexibly replace the chip mounting circuit board to adapt to different packaged chips, the compatibility and the adaptation degree of the daughter boards to the chips and the types are improved, the daughter board remaking caused by mismatching of the chip mounting of the daughter boards and the peripheral circuit integrated circuit is avoided, the manufacturing cost and the duration of the whole daughter board are further reduced, and the chip testing efficiency is improved.
In other embodiments, the chip-mounted circuit board 120 includes: a chip circuit board body 123 and a chip socket 124. The chip circuit board body 123 is used to make electrical connection between the chip socket 124 and the motherboard 110. The chip socket 124 is used for mounting a chip.
A plurality of metal holes 126 are arranged in an array on a side of the chip circuit board body 123 remote from the motherboard 110. And a plurality of pins 125 are disposed on a side of the chip socket 124 close to the chip circuit board body 123 at positions corresponding to the plurality of metal holes 126. The chip socket 124 is inserted into a plurality of metal holes 126 of the chip circuit board body 123 by a plurality of pins 125 for connection.
In a specific application scenario, the plurality of pins 125 on the chip socket 124 are matched with the plurality of metal holes 126 on the chip circuit board body 123 in type, number and position, so that the plurality of pins 125 and the plurality of metal holes 126 are plugged to realize the electrical connection between the chip socket 124 and the chip circuit board body 123.
After the chip is mounted on the chip socket 124, the chip can be electrically connected to the motherboard 110 through the chip socket 124, the pins 125, the metal holes 126, and the chip circuit board body 123 in this order.
In a specific embodiment, the plurality of pins 125 of the chip socket 124 correspond to the plurality of metal holes 126 of the chip circuit board main body 123 one by one and are soldered and fixed, so that the chip socket 124 and the chip circuit board main body 123 are electrically connected and fixedly mounted, thereby improving the connection stability between the chip and the chip circuit board main body 123 and improving the reliability and stability of the chip test.
In another embodiment, the plurality of pins 125 of the chip socket 124 and the plurality of metal holes 126 of the chip circuit board main body 123 may be connected in a one-to-one correspondence and detachable manner, so as to perform electrical connection and flexible installation between the chip socket 124 and the chip circuit board main body 123. Thus, when the chip socket 124 is damaged or not matched with a chip, only the chip socket 124 needs to be replaced without replacing the entire chip-mounted circuit board 120, thereby reducing the replacement cost.
The chip circuit board main body 123 is detachably connected to the corresponding test area 111, that is, the chip-mounted circuit board 120 is detachably connected and electrically connected to the corresponding test area 111 through the chip circuit board main body 123.
The chip circuit board main body 123 is detachably connected with the test area 111 through the chip circuit board main body 123, so that the chip circuit board main body 123 can be flexibly replaced to match different chips or different demand scenarios, and the adaptability and compatibility of the test device 100 are improved.
In other embodiments, a plurality of first connectors 112 are disposed on the test area 111, and the plurality of first connectors 112 are electrically connected to the motherboard 110.
A plurality of second connectors 121 are disposed at positions corresponding to the plurality of first connectors 112 on a side of the chip circuit board body 123 of the chip-mounted circuit board 120 close to the test region 111, and the plurality of second connectors 121 are electrically connected to the chip circuit board body 123.
The first connectors 112 and the second connectors 121 are matched in type, so that the chip circuit board main body 123 of the chip-mounted circuit board 120 is detachably connected to the plurality of first connectors 112 of the test area 111 through the plurality of second connectors 121.
In one embodiment, the second connectors 121 on the chip circuit board body 123 are the same in number and corresponding in position to the first connectors 112 on the test region 111, so that when the second connectors 121 and the first connectors 112 are connected to each other, a stable connection between the chip mounting circuit board 120 and the motherboard 110 is achieved.
In a specific application scenario, the first connectors 112 include male connector sockets, and the second connectors 121 include female connector sockets. The male connector seat is of a convex connector structure, and the female connector seat is of a concave connector structure. In a specific application scenario, the female connector seat may include a female pin header and the male connector seat may include a pin header. Wherein, through protruding respectively, the public seat of concave connector and the female seat of connector realize, the stability and the reliability that chip circuit board main part 123 and test area 111 are connected can be improved to the structure block between the utilization connector to the connection between chip circuit board main part 123 and the test area 111, reduce the phenomenon emergence of the test failure because of contact failure leads to.
In another specific application scenario, the first connectors 112 also include female connectors, and the second connectors 121 include male connectors, and the specific connector configuration thereof may be set based on actual situations, which is not limited herein.
In other embodiments, a plurality of third connectors 122 are further disposed on a side of the chip circuit board main body 123 of the chip-mounted circuit board 120 away from the testing area 111, and the third connectors 122 are electrically connected to the chip circuit board main body 123.
A plurality of fourth connecting members 132 are disposed on the peripheral circuit integrated circuit board 130 at positions corresponding to the plurality of third connecting members 122, and the plurality of fourth connecting members 132 are electrically connected to the peripheral circuit integrated circuit board 130.
The third connecting members 122 and the fourth connecting members 132 are matched in type, so that the chip circuit board main body 123 of the chip-mounted circuit board 120 is detachably connected to the fourth connecting members 132 of the peripheral circuit integrated circuit board 130 through the third connecting members 122. That is, the peripheral circuit integrated circuit board 130 may be electrically connected to the motherboard 110 sequentially through the fourth connecting member 132, the third connecting member 122, the chip circuit board main body 123, the second connecting member 121, and the first connecting member 112, so as to implement the function of the peripheral circuit integrated circuit board 130, and the peripheral circuit integrated circuit board 130 may be electrically connected to the chip socket 124 sequentially through the fourth connecting member 132, the third connecting member 122, the chip circuit board main body 123, the metal hole 126, and the contact pin 125, so as to implement the auxiliary test of the chip mounted on the chip socket 124.
The side of the chip circuit board main body 123 away from the motherboard 110 is provided with a plurality of third connectors 122 and a plurality of metal holes 126, wherein the plurality of third connectors 122 and the plurality of metal holes 126 are disposed at intervals and respectively connected to the plurality of fourth connectors 132 of the peripheral circuit integrated circuit board 130 and the plurality of pins 125 of the chip socket 124.
In a specific application scenario, the plurality of metal holes 126 on the side of the chip circuit board body 123 away from the motherboard 110 may be centered and arranged in an array. And the third connecting members 122 may be disposed on at least one side of the metal holes 126, for example: two-sided or four-sided, etc. So that the peripheral circuit integrated circuit board 130 connected by the third connecting members 122 is disposed on at least one side of the chip socket 124 connected by the metal holes 126, for example: opposite or surrounding arrangement, etc.
In a particular embodiment, the plurality of third connectors 122 may include female connector receptacles and the plurality of fourth connectors 132 may include male connector receptacles. In another specific application scenario, the third connectors 122 also include male connector seats, and the fourth connectors 132 include female connector seats, and the specific connector structure configuration thereof may be set based on actual situations, and is not limited herein. Wherein, through protruding respectively, the public seat of concave connector and the female seat of connector realize, the chip circuit board main part 123 is connected with peripheral circuit integrated circuit board 130 between, can utilize the structure block between the connector to improve the stability and the reliability that chip circuit board main part 123 and peripheral circuit integrated circuit board 130 are connected, reduces the phenomenon of the test failure because of contact failure leads to and takes place.
In other embodiments, the peripheral circuit integrated circuit board 130 further includes: a peripheral circuit board main body 131 and peripheral application circuits (not shown), wherein the peripheral circuit board main body 131 is connected to the chip-mounted circuit board 120 through a plurality of fourth connectors 132, and the peripheral application circuits are used for auxiliary testing of the chips and electrically connected to the peripheral circuit board main body 131.
In other embodiments, a through groove 133 is further disposed on the peripheral circuit integrated circuit board 130. A through slot 133 is disposed through the peripheral circuit board 130, wherein the through slot 133 is configured to receive the chip socket 124, such that the chip socket 124 is connected to the chip board body 123 through the through slot 133 on the peripheral circuit board 130. Thus, the peripheral circuit integrated circuit board 130 and the chip-mounted circuit board 120 are mounted in a spliced manner, thereby reducing the size of the sub-board 140 and realizing the miniaturization and lightness of the sub-board 140.
In other embodiments, the motherboard 110 is further provided with a plurality of gold finger interfaces 113, the plurality of gold finger interfaces 113 are used for connecting the test machine, and the gold finger interfaces 113 are respectively electrically connected with the test areas 111.
In a specific application scenario, when the plurality of gold finger interfaces 113 of the motherboard 110 are connected to the testing machine, the first connecting member 112 of the motherboard 110 is connected to the second connecting member 121 of the chip circuit board main body 123 of the chip mounting circuit board 120; the metal holes 126 of the chip circuit board body 123 of the chip-mounted circuit board 120 are connected with the pins 125 of the chip socket 124; the third connecting member 122 of the chip circuit board body 123 of the chip-mounted circuit board 120 is connected to the fourth connecting member 132 of the peripheral circuit integrated circuit board 130, and when a chip is mounted on the chip socket 124, the chip can be tested by using the testing apparatus 100.
Referring to fig. 2, fig. 2 is a schematic top view of an embodiment of the motherboard shown in fig. 1.
The motherboard 110 of the present embodiment includes a motherboard main body 114, a plurality of test areas 111, and a plurality of gold finger interfaces 113. The plurality of test regions 111 are arranged on the motherboard body 114 in an array and spaced apart from each other. The plurality of gold finger interfaces 113 are arranged at the edge of the motherboard main body 114 in a protruding manner and are used for being connected with a test machine. A plurality of gold finger interfaces 113 are also respectively connected to each test area 111 to implement the function of the test area 111.
The test area 111 is provided with a plurality of first connecting pieces 112, and the first connecting pieces 112 may be arranged in two rows, so as to increase the acting point of connection between the first connecting pieces 112 and the second connecting pieces 121 and improve the connection stability between the first connecting pieces 112 and the second connecting pieces 121.
Through the structure, the testing device of the embodiment utilizes the plurality of daughter boards and the mother board which are detachably connected to enable the testing device to flexibly replace the daughter boards so as to aim at different types of chips, and further utilizes the detachable chip mounting circuit board and the peripheral circuit integrated circuit board to enable the daughter boards to flexibly replace the peripheral circuit integrated circuit to test different types of chips and flexibly replace the chip mounting circuit board to adapt to different packaged chips, the compatibility of the daughter boards to the chips and the types is improved, the daughter board remaking caused by mismatching of the chip mounting of the daughter boards and the peripheral circuit integrated circuit is avoided, the manufacturing cost and the duration of the whole daughter board are further reduced, and the chip testing efficiency is improved.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A test apparatus, characterized in that the test apparatus comprises:
the test device comprises a motherboard, a test device and a test device, wherein a plurality of test areas are arranged on the motherboard;
the daughter boards respectively comprise a chip mounting circuit board and a peripheral circuit integrated circuit board which are detachably connected; and each daughter board is correspondingly detachably connected with a test area on the mother board through the chip mounting circuit board.
2. The test device of claim 1, wherein the chip-mounted circuit board comprises:
the chip circuit board main body is detachably connected with the corresponding test area, and a plurality of metal holes are formed in one side, far away from the motherboard, of the chip circuit board main body in an array manner;
the chip socket is used for mounting a chip, and a plurality of contact pins are arranged on one side of the chip socket close to the chip circuit board main body and correspond to the plurality of metal holes;
the chip socket is correspondingly inserted into the plurality of metal holes of the chip circuit board main body by the plurality of contact pins for connection.
3. The test device of claim 2,
and a plurality of contact pins of the chip socket correspond to a plurality of metal holes of the chip circuit board main body one by one and are welded and fixed for connection.
4. The test device of claim 2,
a plurality of first connecting pieces are arranged on the test area and electrically connected with the motherboard;
a plurality of second connecting pieces are arranged on one side of the chip circuit board main body of the chip mounting circuit board, which is close to the test area, corresponding to the plurality of first connecting pieces, and the plurality of second connecting pieces are electrically connected with the chip circuit board main body;
the first connecting pieces are matched with the second connecting pieces in type, so that the chip circuit board main body of the chip installation circuit board is correspondingly detachably connected with the first connecting pieces in the test area through the second connecting pieces.
5. The test device of claim 4, wherein the first plurality of connectors comprises male connector receptacles and the second plurality of connectors comprises female connector receptacles.
6. The test device as claimed in claim 2, wherein a plurality of third connectors are further provided on a side of the chip circuit board main body of the chip-mounted circuit board away from the test area, the third connectors being electrically connected to the chip circuit board main body;
a plurality of fourth connecting pieces are arranged on the peripheral circuit integrated circuit board at positions corresponding to the plurality of third connecting pieces, and the plurality of fourth connecting pieces are electrically connected with the peripheral circuit integrated circuit board;
the third connecting piece is matched with the fourth connecting piece in type, so that the chip circuit board main body of the chip installation circuit board is correspondingly detachably connected with the fourth connecting pieces of the peripheral circuit integrated circuit board through the third connecting pieces.
7. The testing device of claim 6, wherein the plurality of third connectors comprise female connector receptacles and the plurality of fourth connectors comprise male connector receptacles.
8. The test device of claim 6, wherein the peripheral circuit integrated circuit board further comprises:
a peripheral circuit board main body connected with the chip mounting circuit board through the plurality of fourth connecting members;
and the peripheral application circuit is used for assisting in testing the chip and is electrically connected with the peripheral circuit board main body.
9. The testing device of claim 6, wherein a through slot is further disposed on the peripheral circuit integrated circuit board;
the chip socket penetrates through the through groove on the peripheral circuit integrated circuit board and is connected with the chip circuit board main body.
10. The testing device according to any one of claims 1 to 9, wherein a plurality of gold finger interfaces are further disposed on the motherboard, the plurality of gold finger interfaces are used for connecting a testing machine, and the gold finger interfaces are electrically connected to the testing regions respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111619098.5A CN115267480A (en) | 2021-12-27 | 2021-12-27 | Testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111619098.5A CN115267480A (en) | 2021-12-27 | 2021-12-27 | Testing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115267480A true CN115267480A (en) | 2022-11-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111619098.5A Pending CN115267480A (en) | 2021-12-27 | 2021-12-27 | Testing device |
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| CN (1) | CN115267480A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116482494A (en) * | 2023-03-22 | 2023-07-25 | 广东微容电子科技有限公司 | Chip type multilayer ceramic capacitor test fixture |
-
2021
- 2021-12-27 CN CN202111619098.5A patent/CN115267480A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116482494A (en) * | 2023-03-22 | 2023-07-25 | 广东微容电子科技有限公司 | Chip type multilayer ceramic capacitor test fixture |
| CN116482494B (en) * | 2023-03-22 | 2023-11-21 | 广东微容电子科技有限公司 | Chip type multilayer ceramic capacitor test fixture |
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