CN219715670U - Test panel and performance test assembly - Google Patents
Test panel and performance test assembly Download PDFInfo
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- CN219715670U CN219715670U CN202320120811.XU CN202320120811U CN219715670U CN 219715670 U CN219715670 U CN 219715670U CN 202320120811 U CN202320120811 U CN 202320120811U CN 219715670 U CN219715670 U CN 219715670U
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- 238000012360 testing method Methods 0.000 title claims abstract description 270
- 238000011056 performance test Methods 0.000 title claims abstract description 28
- 239000000725 suspension Substances 0.000 claims abstract description 48
- 230000002093 peripheral effect Effects 0.000 claims abstract description 42
- 230000032683 aging Effects 0.000 claims abstract description 29
- 238000004378 air conditioning Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 19
- 238000013461 design Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 4
- 241000287531 Psittacidae Species 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
The utility model provides a test platelet and a performance test assembly. The test platelet includes: a platelet body; a plurality of first peripheral elements carried by the platelet body; the first test interface comprises a first network public interface, a first suspension interface and a first external interface, wherein the first network public interface is electrically connected with the plurality of first peripheral elements, the first suspension interface is electrically connected with the first external interface, the first network public interface and the first suspension interface are used for electrically connecting an aging sub-board to be electrically connected with a chip to be tested and the plurality of first peripheral elements, and the first external interface is used for electrically connecting a test circuit to perform performance test on the chip to be tested. The test small plate provided by the utility model has simple structure and can reduce the aging test cost.
Description
Technical Field
The utility model relates to the field of semiconductor devices, in particular to a test small plate and a performance test assembly.
Background
Before packaging, integrated circuit chips often require burn-in and performance testing to test the reliability and quality risk potential of the chips.
However, different peripheral circuits are required to be arranged on the chips to be tested with different models, so that the design cost of the burn-in daughter board is high.
Disclosure of Invention
In a first aspect, the present utility model provides a test platelet comprising:
a platelet body;
a plurality of first peripheral elements carried by the platelet body; a kind of electronic device with high-pressure air-conditioning system
The first test interface comprises a first network public interface, a first suspension interface and a first external interface, wherein the first network public interface is electrically connected with the plurality of first peripheral elements, the first suspension interface is electrically connected with the first external interface, the first network public interface and the first suspension interface are used for electrically connecting an aging sub-board to be electrically connected with a chip to be tested and the plurality of first peripheral elements, and the first external interface is used for electrically connecting a test circuit to perform performance test on the chip to be tested.
Wherein the test platelet further comprises:
the first connector comprises a first electric connecting piece and a first switching piece, one end of the first electric connecting piece is electrically connected with the first network public interface and the first suspension interface, the first switching piece is provided with a first through hole, the first switching piece is abutted to the small plate body, and the first through hole accommodates the first electric connecting piece.
Wherein the test platelet further comprises:
the second connector comprises a second electric connecting piece and a second switching piece, one end of the second electric connecting piece is electrically connected with the first external interface, the second switching piece is sleeved on the second electric connecting piece, and the other end of the second electric connecting piece protrudes out of the second switching piece.
Wherein the test platelet further comprises:
a plurality of second peripheral elements carried by the platelet body; a kind of electronic device with high-pressure air-conditioning system
The second test interface comprises a second network public interface, a second suspension interface and a second external interface, wherein the second network public interface is electrically connected with the plurality of second external elements, the second suspension interface is electrically connected with the second external interface, the second network public interface and the second suspension interface are used for electrically connecting an aging daughter board to be electrically connected with a chip to be tested of the aging daughter board and the plurality of second external elements, and the second external interface is used for electrically connecting a test circuit to perform performance test on the chip to be tested.
Wherein the test platelet further comprises:
the third connector comprises a third electric connecting piece and a third switching piece, one end of the third electric connecting piece is electrically connected with the second network public interface and the second suspension interface, the third switching piece is provided with a second through hole, the third switching piece is abutted to the small plate body, and the second through hole accommodates the third electric connecting piece.
Wherein the test platelet further comprises:
the fourth connector comprises a fourth electric connecting piece and a fourth switching piece, one end of the fourth electric connecting piece is electrically connected to the second external interface, the fourth switching piece is sleeved on the fourth electric connecting piece, and the other end of the fourth electric connecting piece protrudes out of the fourth switching piece.
When the test small board is used for connecting a test burn-in daughter board to perform performance test, one of the first test interface and the second test interface is electrically connected with the burn-in daughter board.
The pin definition of the first test interface is different from the pin definition of the second test interface, and the model of the burn-in daughter board used for electric connection by the first test interface is different from the model of the burn-in daughter board used for electric connection by the second test interface.
The first test interface is used for electrically connecting the aging sub-boards with various types, and the second test interface is used for electrically connecting the aging sub-boards with various types;
when the pin definition of the first test interface is the same as the pin definition of the second test interface, the aging sub-boards of various types used for electric connection by the first test interface are the same as the aging sub-boards of various types used for electric connection by the second test interface;
when the pin definition of the first test interface is different from the pin definition of the second test interface, the burn-in sub-board of the plurality of types used for the electrical connection of the first test interface is different from the burn-in sub-board of the plurality of types used for the electrical connection of the second test interface.
The utility model provides a test small board, which is electrically connected with an aging sub-board through a first network public interface and a first suspension interface, so that a plurality of first peripheral elements are electrically connected to a chip to be tested on the aging sub-board, thereby forming a minimum running environment of the chip to be tested, and the test small board is connected with a test circuit through a first external interface to test the performance of the chip to be tested, and has a simple structure. In addition, the test small board can provide a plurality of first peripheral elements required by operation for the chip to be tested, so that a peripheral circuit of the chip to be tested is not required to be arranged on the aging sub-board, the structure of the aging sub-board is simplified, the design cost of the aging sub-board is reduced, and the aging test cost is further reduced. Therefore, the test small plate provided by the utility model has simple structure and can reduce the burn-in test cost.
In a second aspect, the present utility model also provides a performance testing assembly comprising:
the burn-in daughter board comprises a daughter board body, a chip bonding pad and a third test interface, wherein the chip bonding pad and the third test interface are arranged on the daughter board body at intervals, the chip bonding pad is electrically connected with the third test interface, and the chip bonding pad is used for mounting a chip to be tested;
the test platelet of the first aspect, the test platelet electrically connected with the third test interface through the first test interface to be electrically connected to a chip under test mounted to the chip pad, when the test platelet further includes a second test interface, the test platelet electrically connected with the third test interface through one of the first test interface and the second test interface to be electrically connected to a chip under test mounted to the chip pad.
The test small board of the performance test assembly provided by the embodiment is connected with the first suspension interface and the third test interface of the aging sub-board through the first network public interface, so that the plurality of first peripheral elements are electrically connected to the chip to be tested on the aging sub-board, thereby forming the minimum running environment of the chip to be tested, and the performance test can be performed on the chip to be tested through the first external interface connection test circuit, and the structure is simple. In addition, the test small board can provide a plurality of first peripheral elements required by operation for the chip to be tested, so that a peripheral circuit of the chip to be tested is not required to be arranged on the aging sub-board, the structure of the aging sub-board is simplified, the design cost of the aging sub-board is reduced, and the aging test cost is further reduced. Therefore, the performance test assembly provided by the utility model has a simple structure and can reduce the aging test cost.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a test platelet according to an embodiment of the present utility model.
Fig. 2 is a schematic view of the structure of the test panel of fig. 1 with a first connector.
Fig. 3 is a schematic cross-sectional view taken along line A-A in fig. 2.
Fig. 4 is a schematic structural diagram of a performance testing assembly according to an embodiment of the utility model.
Fig. 5 is a schematic structural diagram of the burn-in daughter board of fig. 4.
Fig. 6 is a schematic structural diagram of an aged daughter board in this embodiment.
Fig. 7 is a schematic diagram of wiring of the network common interface and peripheral elements of the test panel in this embodiment.
Fig. 8 is a schematic diagram illustrating the definition of pins of the first suspension interface and the first external interface when the CVT5001 chip is connected to the test board in the present embodiment.
Fig. 9 is a schematic diagram illustrating the definition of pins of the first suspension interface and the first external interface when the CVT5002A chip is connected to the test board in the present embodiment.
Fig. 10 is a schematic diagram illustrating the definition of pins of the second suspension interface and the second external interface when the CVT5002B chip is connected to the test board 10 in the present embodiment.
Fig. 11 is a schematic diagram illustrating the definition of pins of the second suspension interface and the second external interface when the CVT5003 chip is connected to the test board in the present embodiment.
Reference numerals: a performance test assembly 1; testing the platelets 10; a platelet body 11; a first peripheral element 12; a first test interface 13; a first network public interface 131; a first suspension interface 132; a first external interface 133; a first connector 14; a first electrical connection 141; a first adapter 142; a first through hole 1421; a second connector 15; a second electrical connection 151; a second adapter 152; a second peripheral element 16; a second test interface 17; a second network public interface 171; a second suspension interface 172; a second external interface 173; a third connector 18; a third electrical connector 181; a third adapter 182; a second through hole 1821; a fourth connector 19; a fourth electrical connector 191; a fourth adapter 192; burn-in daughter board 20; a sub-board body 21; a chip pad 22; a third test interface 23; an aging interface 231; and a third suspension interface 232.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without any inventive effort, are intended to be within the scope of the utility model.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" or "implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment or implementation may be included in at least one embodiment of the utility model. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The present utility model provides a test platelet 10. Referring to fig. 1, fig. 1 is a schematic structural diagram of a test platelet according to an embodiment of the utility model. In this embodiment, the test board 10 includes a board body 11, a plurality of first peripheral elements 12, and a first test interface 13. The plurality of first peripheral elements 12 is carried by the platelet body 11. The first test interface 13 includes a first network public interface 131, a first suspension interface 132, and a first external interface 133. The first network common interface 131 is electrically connected to the plurality of first peripheral elements 12. The first suspension interface 132 is electrically connected to the first external interface 133. The first network common interface 131 and the first suspension interface 132 are used for electrically connecting the burn-in daughter board 20 to electrically connect the chips to be tested mounted on the burn-in daughter board 20 with the plurality of first peripheral elements 12. The first external interface 133 is used for electrically connecting with a testing circuit to perform performance testing on the chip to be tested.
In this embodiment, the test platelet 10 is used for performance testing after burn-in testing (High Temp Operating Life, HTOL) of chips. Specifically, before the chip is packaged, a small batch of chips are inspected as chips to be tested, the chips to be tested are loaded on the burn-in daughter board 20 and assembled with related devices to perform burn-in test on the chips to be tested, and performance test is performed on the chips to be tested after the burn-in test. Related devices include burn-in motherboards, burn-in sockets, test platelets 10, automated test equipment (Automatic Test Equipmen, ATE), incubators, and the like.
In this embodiment, the test board 10 is used for being connected with the burn-in daughter board 20 in a matching manner, so as to perform performance test on the chip to be tested loaded on the burn-in daughter board 20. Specifically, the first network common interface 131 and the first suspension interface 132 in the first test interface 13 are electrically connected to the burn-in daughter board 20, so as to be electrically connected to the chip to be tested, so that the plurality of first peripheral elements 12 are electrically connected to the chip to be tested, to provide peripheral circuits required for operation for the chip to be tested, and to form a minimum operation environment for the chip to be tested. After the burn-in daughter board 20 is connected to the test board 10, the performance test can be performed on the chip to be tested by connecting the test circuit through the first external interface 133 in the first test interface 13.
In the related art, peripheral elements required for the operation of the chip to be tested need to be set on the burn-in daughter board 20, and different types of chips to be tested need to be configured with different peripheral elements, so that the design cost of the burn-in daughter board 20 is high.
In this embodiment, the plurality of first peripheral elements 12 required for the operation of the chip to be tested are disposed on the test board 10, the test board 10 is connected to the burn-in daughter board 20 through the first network common interface 131, the first suspension interface 132 and the first external interface 133 to form a minimum motion environment of the chip to be tested, so as to perform performance test on the chip to be tested, and the design structure of the test board 10 is simple. In addition, the burn-in daughter board 20 does not need to be provided with a peripheral circuit of the chip to be tested, so that the structure of the burn-in daughter board 20 is simplified, and the design cost of the burn-in daughter board 20 is reduced. In addition, the first network common interface 131 has the same pin definition as the interface on the burn-in motherboard, reducing the design cost of the test panel 10.
In summary, the present utility model provides a test platelet 10. The test small board 10 is electrically connected with the burn-in board 20 through the first network public interface 131 and the first suspension interface 132, so that the plurality of first peripheral elements 12 are electrically connected to the chip to be tested on the burn-in board 20, thereby forming a minimum operation environment of the chip to be tested, and the first external interface 133 is connected with a test circuit to perform performance test on the chip to be tested, so that the test small board has a simple structure. In addition, since the test small board 10 can provide the plurality of first peripheral elements 12 required for the operation of the chip to be tested, the burn-in daughter board 20 does not need to be provided with a peripheral circuit of the chip to be tested, so that the structure of the burn-in daughter board 20 is simplified, the design cost of the burn-in daughter board 20 is reduced, and the burn-in test cost is further reduced. Therefore, the test panel 10 provided by the utility model has a simple structure and can reduce the burn-in test cost.
Referring to fig. 1, 2 and 3, fig. 2 is a schematic structural diagram of the test panel of fig. 1 with a first connector; fig. 3 is a schematic cross-sectional view taken along line A-A in fig. 2. In this embodiment, the test platelet 10 further comprises a first connector 14. The first connector 14 includes a first electrical connector 141 and a first adapter 142. One end of the first electrical connector 141 is electrically connected to the first network public interface 131 and the first suspension interface 132. The first adaptor 142 has a first through hole 1421. The first adaptor 142 abuts against the small plate body 11, and the first through hole 1421 accommodates the first electrical connector 141.
In this embodiment, the first adaptor 142 has a first through hole 1421, so that the burn-in daughter board 20 can be quickly inserted into the first through hole 1421 by placing pins in order to be electrically connected with the test board 10, thereby improving the connection efficiency of the burn-in daughter board 20 and the test board 10.
In addition, the first through hole 1421 of the first adapter 142 accommodates the first electrical connector 141, so as to protect the first electrical connector 141.
In addition, the first connector 142 abuts against the platelet body 11, and plays a role of supporting the first electrical connector 141.
Referring to fig. 2 and 3 again, in the present embodiment, the test board 10 further includes a second connector 15. The second connector 15 includes a second electrical connector 151 and a second adapter 152. One end of the second electrical connector 151 is electrically connected to the first external interface 133. The second adaptor 152 is sleeved on the second electrical connector 151, and the other end of the second electrical connector 151 protrudes out of the second adaptor 152.
In this embodiment, the second electrical connector 151 protrudes from the second adapter 152, so that the first external interface 133 is electrically connected to the test circuit.
In addition, the second adaptor 152 is sleeved on the second electrical connector 151, so as to protect and support the second electrical connector 151.
Further, the second adapter 152 is disposed against the platelet body 11 to support the second electrical connector 151.
Referring to fig. 1 again, in the present embodiment, the test board 10 further includes a plurality of second peripheral elements 16 and a second test interface 17. The plurality of second peripheral elements 16 are carried by the platelet body 11. The second test interface 17 includes a second network public interface 171, a second floating interface 172, and a second external interface 173. The second network common interface 171 is electrically connected to the plurality of second peripheral elements 16. The second suspension interface 172 is electrically connected to the second external interface 173. The second network common interface 171 and the second suspension interface 172 are used for electrically connecting the burn-in daughter board 20 to electrically connect the chips to be tested mounted on the burn-in daughter board 20 with the plurality of second peripheral elements 16. The second external interface 173 is used for electrically connecting with a testing circuit to perform a performance test on the chip under test.
In this embodiment, the pin definition of the second test interface 17 is the same as or different from the pin definition of the first test interface 13. When the pin definition of the second test interface 17 is the same as the pin definition of the first test interface 13, the test platelet 10 can select any one of the first test interface 13 and the second test interface 17 to be electrically connected with the burn-in daughter board 20, and when one of the test interface and the second test interface is damaged, the other test platelet can still be electrically connected with the burn-in daughter board 20 to perform performance test on the chip to be tested. When the pin definition of the second test interface 17 is different from the pin definition of the first test interface 13, the test platelet 10 can support connection of burn-in platelets of various types, i.e. can support testing of chips to be tested of various types, thereby improving suitability of the test platelet 10.
Referring to fig. 2 and 3 again, in the present embodiment, the test board 10 further includes a third connector 18, and the third connector 18 includes a third electrical connector 181 and a third adapter 182. One end of the third electrical connection is electrically connected to the second network public interface 171 and the second floating interface 172. The third adaptor 182 has a second through hole 1821. The third adaptor 182 abuts against the small plate body 11, and the second through hole 1821 accommodates the third electrical connector 181.
In this embodiment, the third adaptor 182 has a second through hole 1821, so that the burn-in daughter board 20 can be quickly inserted into the second through hole 1821 by placing pins in order to be electrically connected with the test board 10, thereby improving the connection efficiency of the burn-in daughter board 20 and the test board 10.
In addition, the second through hole 1821 of the third adaptor 182 accommodates the third electrical connector 181, so as to protect the third electrical connector 181.
In addition, the third adaptor 182 abuts against the platelet body 11, and plays a role in supporting the third electrical connector 181.
Referring again to fig. 2 and 3, in the present embodiment, the test board 10 further includes a fourth connector 19. The fourth connector 19 includes a fourth electrical connector 191 and a fourth adapter 192. One end of the fourth electrical connector 191 is electrically connected to the second external interface 173. The fourth adaptor 192 is sleeved on the fourth electrical connector 191, and the other end of the fourth electrical connector 191 protrudes out of the fourth adaptor 192.
In this embodiment, the fourth electrical connector 191 protrudes from the fourth adaptor 192, so as to facilitate the electrical connection of the second external interface 173 to a test circuit.
In addition, the fourth adaptor 192 is sleeved on the fourth electrical connector 191, and can protect and support the fourth electrical connector 191.
Further, the fourth adapter 192 is disposed against the platelet body 11 to support the fourth electrical connector 191.
Furthermore, when the test platelet 10 is used for connecting a test burn-in daughter board 20 for performance testing, one of the first test interface 13 and the second test interface 17 is electrically connected to the burn-in daughter board 20, i.e. the test platelet 10 is electrically connected to only one burn-in daughter board 20 at a time to avoid circuit interference between the first test interface 13 and the second test interface 17.
Optionally, the pin definition of the first test interface 13 is different from the pin definition of the second test interface 17. The model of the burn-in daughter board 20 used for electrical connection by the first test interface 13 is different from the model of the burn-in daughter board 20 used for electrical connection by the second test interface 17, that is, the model of the chip to be tested electrically connected by the first test interface 13 is different from the model of the chip to be tested electrically connected by the second test interface 17, so that the test panel 10 can support performance tests of chips with various models, and the suitability of the test panel 10 is improved.
Optionally, the first test interface 13 is used for electrically connecting multiple types of burn-in daughter boards 20. The second test interface 17 is used for electrically connecting multiple types of burn-in daughter boards 20. When the pin definition of the first test interface 13 is the same as the pin definition of the second test interface 17, the burn-in sub-board 20 of multiple types for electrical connection of the first test interface 13 is the same as the burn-in sub-board 20 of multiple types for electrical connection of the second test interface 17. When the pin definition of the first test interface 13 is different from the pin definition of the second test interface 17, the burn-in sub-board 20 of the plurality of types for electrical connection of the first test interface 13 is different from the burn-in sub-board 20 of the plurality of types for electrical connection of the second test interface 17. In this embodiment, the first test interface 13 and the second test interface 17 may be both capable of connecting with burn-in daughter boards 20 of multiple types, that is, the first test interface 13 and the second test may be both capable of connecting with chips to be tested of multiple types, so that the test platelet 10 may support performance tests of chips of multiple types, and suitability of the test platelet 10 may be further improved.
Referring to fig. 4 and 5, fig. 4 is a schematic structural diagram of a performance testing component according to an embodiment of the utility model; fig. 5 is a schematic structural diagram of the burn-in daughter board of fig. 4. In this embodiment, the performance test assembly 1 includes the burn-in daughter board 20 and the test platelet 10 according to any of the foregoing embodiments. The burn-in daughter board 20 includes a daughter board body 21, a chip pad 22, and a third test interface 23. The chip bonding pads 22 and the third test interface 23 are disposed at intervals on the daughter board body 21. The chip pad 22 is electrically connected to the third test interface 23. The chip bonding pad 22 is used for mounting a chip to be tested. The test platelet 10 is electrically connected to the third test interface 23 through the first test interface 13 to be electrically connected to the chip under test mounted on the chip pad 22. When the test platelet 10 further includes a second test interface 17, the test platelet 10 is electrically connected to the third test interface 23 through one of the first test interface 13 and the second test interface 17 to be electrically connected to a chip under test mounted on the chip pad 22.
In this embodiment, the test board 10 of the performance test assembly 1 provided in this embodiment is connected to the third test interface 23 of the burn-in board 20 through the first network common interface 131 and the first suspension interface 132, so that the plurality of first peripheral elements 12 are electrically connected to the chip to be tested on the burn-in board 20, thereby forming a minimum operation environment of the chip to be tested, and the first external interface 133 is connected to a test circuit to perform performance test on the chip to be tested. In addition, since the test small board 10 can provide the plurality of first peripheral elements 12 required for the operation of the chip to be tested, the burn-in daughter board 20 does not need to be provided with a peripheral circuit of the chip to be tested, so that the structure of the burn-in daughter board 20 is simplified, the design cost of the burn-in daughter board 20 is reduced, and the burn-in test cost is further reduced. Therefore, the performance test assembly 1 provided by the utility model has a simple structure and can reduce the burn-in test cost.
Further, the burn-in daughter board 20 is connected to the test platelet 10 in a vertical state with respect to the test platelet 10, so that the occupied space of the burn-in daughter board 20 on the test platelet 10 can be reduced, and the space utilization rate of the test platelet 10 is improved, so that the test platelet 10 can be designed into a smaller size, and the design cost and the material cost of the test platelet 10 are further reduced.
Examples
Referring to fig. 1, fig. 6 to fig. 11, table 1 and table 2, fig. 6 is a schematic structural diagram of an aging sub-board in the present embodiment; FIG. 7 is a schematic diagram of wiring of the network common interface and peripheral components of the test panel in this embodiment; FIG. 8 is a schematic diagram illustrating the definition of the pins of the first suspension interface and the first external interface when the CVT5001 chip is connected to the test board in the present embodiment; FIG. 9 is a schematic diagram showing the definition of the pins of the first suspension interface and the first external interface when the CVT5002A chip is connected to the test board in the present embodiment; fig. 10 is a schematic diagram showing the definition of pins of the second suspension interface and the second external interface when the CVT5002B chip is connected to the test board 10 in the present embodiment; fig. 11 is a schematic diagram illustrating the definition of pins of the second suspension interface and the second external interface when the CVT5003 chip is connected to the test board in the present embodiment. This embodiment is schematically illustrated with four types of chips, CVT5001, CVT5002A, CVT5002B, CVT5003, of the Parrot product line.
In this embodiment, the third test interface 23 includes an burn-in interface 231 and a third suspension interface 232. The third test interface 23 is shown as 30 connection points in parallel, and there are 20 connection points in each column, where the burn-in interface 231 is 20 connection points in parallel for burn-in testing. The third suspension interface 232 is a series of 10 connection points, and is used for leading out all pin angles on the chip to be tested together with the burn-in interface 231 so as to perform performance test. In addition, the arrangement order of the third test interfaces 23 in the list shown in tables 1 and 2 is identical to the distribution order of the third test interfaces 23 shown in fig. 6. And the interface definitions in tables 1 and 2 indicate the pin signals that need to be accessed.
In this embodiment, the third test interface 23 is configured as three parallel rows of connection points, and correspondingly, the third test interface 23 is connected to the first network common interface 131 and the first floating interface 132 of the first test interface 13 in the test platelet 10 in fig. 1, or to the second network common interface 171 and the second floating interface 172 of the second test interface 17 in the test platelet 10 in fig. 1. The first suspension interface 132 and the second suspension interface 172 have different pin definitions according to different types of electrically connected chips to be tested, so that the first suspension interface 132 and the second suspension interface 172 can be matched with the chips to be tested in various types.
While embodiments of the present utility model have been shown and described above, it should be understood that the above embodiments are illustrative and not to be construed as limiting the utility model, and that variations, modifications, alternatives and alternatives to the above embodiments may be made by those skilled in the art within the scope of the utility model, which is also to be regarded as being within the scope of the utility model.
Claims (10)
1. A test platelet, the test platelet comprising:
a platelet body;
a plurality of first peripheral elements carried by the platelet body; a kind of electronic device with high-pressure air-conditioning system
The first test interface comprises a first network public interface, a first suspension interface and a first external interface, wherein the first network public interface is electrically connected with the plurality of first peripheral elements, the first suspension interface is electrically connected with the first external interface, the first network public interface and the first suspension interface are used for electrically connecting an aging sub-board to be electrically connected with a chip to be tested and the plurality of first peripheral elements, and the first external interface is used for electrically connecting a test circuit to perform performance test on the chip to be tested.
2. The test platelet of claim 1, further comprising:
the first connector comprises a first electric connecting piece and a first switching piece, one end of the first electric connecting piece is electrically connected with the first network public interface and the first suspension interface, the first switching piece is provided with a first through hole, the first switching piece is abutted to the small plate body, and the first through hole accommodates the first electric connecting piece.
3. The test platelet of claim 2, further comprising:
the second connector comprises a second electric connecting piece and a second switching piece, one end of the second electric connecting piece is electrically connected with the first external interface, the second switching piece is sleeved on the second electric connecting piece, and the other end of the second electric connecting piece protrudes out of the second switching piece.
4. A test platelet as in any one of claims 1 to 3 further comprising:
a plurality of second peripheral elements carried by the platelet body; a kind of electronic device with high-pressure air-conditioning system
The second test interface comprises a second network public interface, a second suspension interface and a second external interface, wherein the second network public interface is electrically connected with the plurality of second external elements, the second suspension interface is electrically connected with the second external interface, the second network public interface and the second suspension interface are used for electrically connecting an aging daughter board to be electrically connected with a chip to be tested of the aging daughter board and the plurality of second external elements, and the second external interface is used for electrically connecting a test circuit to perform performance test on the chip to be tested.
5. The test platelet of claim 4, further comprising:
the third connector comprises a third electric connecting piece and a third switching piece, one end of the third electric connecting piece is electrically connected with the second network public interface and the second suspension interface, the third switching piece is provided with a second through hole, the third switching piece is abutted to the small plate body, and the second through hole accommodates the third electric connecting piece.
6. The test platelet of claim 5, further comprising:
the fourth connector comprises a fourth electric connecting piece and a fourth switching piece, one end of the fourth electric connecting piece is electrically connected to the second external interface, the fourth switching piece is sleeved on the fourth electric connecting piece, and the other end of the fourth electric connecting piece protrudes out of the fourth switching piece.
7. The test platelet of claim 6, wherein one of the first test interface and the second test interface is electrically connected to the burn-in daughter board when the test platelet is used to connect to a test burn-in daughter board for performance testing.
8. The test platelet of claim 7, wherein the pin definition of the first test interface is different from the pin definition of the second test interface, and wherein the burn-in daughter board for the first test interface is of a different model than the burn-in daughter board for the second test interface.
9. The test panel of claim 7 or 8, wherein the first test interface is for electrically connecting multiple models of burn-in daughter boards and the second test interface is for electrically connecting multiple models of burn-in daughter boards;
when the pin definition of the first test interface is the same as the pin definition of the second test interface, the aging sub-boards of various types used for electric connection by the first test interface are the same as the aging sub-boards of various types used for electric connection by the second test interface;
when the pin definition of the first test interface is different from the pin definition of the second test interface, the burn-in sub-board of the plurality of types used for the electrical connection of the first test interface is different from the burn-in sub-board of the plurality of types used for the electrical connection of the second test interface.
10. A performance testing assembly, the performance testing assembly comprising:
the burn-in daughter board comprises a daughter board body, a chip bonding pad and a third test interface, wherein the chip bonding pad and the third test interface are arranged on the daughter board body at intervals, the chip bonding pad is electrically connected with the third test interface, and the chip bonding pad is used for mounting a chip to be tested;
the test platelet of any of claims 1-9, the test platelet electrically connected with the third test interface through the first test interface to electrically connect to a chip under test mounted to the chip pad, when the test platelet further comprises a second test interface, the test platelet electrically connected with the third test interface through one of the first test interface and the second test interface to electrically connect to a chip under test mounted to the chip pad.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202320120811.XU CN219715670U (en) | 2023-01-30 | 2023-01-30 | Test panel and performance test assembly |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202320120811.XU CN219715670U (en) | 2023-01-30 | 2023-01-30 | Test panel and performance test assembly |
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| CN219715670U true CN219715670U (en) | 2023-09-19 |
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| CN202320120811.XU Active CN219715670U (en) | 2023-01-30 | 2023-01-30 | Test panel and performance test assembly |
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