CN116344632A - POLO-IBC passivation contact battery and preparation method thereof - Google Patents
POLO-IBC passivation contact battery and preparation method thereof Download PDFInfo
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Abstract
The invention belongs to the field of solar photovoltaic industry, and particularly relates to a POLO-IBC passivation contact battery and a preparation method thereof. The passivation contact battery comprises a substrate, wherein the front surface of the substrate is sequentially provided with an AlOx passivation layer and a SiNx passivation layer from inside to outside, the back surface of the substrate is sequentially provided with a SiNx tunneling layer, a SiOx tunneling layer, a p+ layer formed by gradient doping of III-group element polycrystalline silicon, a SiNx tunneling layer, an n+ layer formed by gradient V-group element doping of polycrystalline silicon, an AlOx passivation layer, a SiNx passivation layer, a separation belt between N/P, p+ finger and n+ finger from inside to outside. According to the invention, the SiNx tunneling layer and the SiOx tunneling layer with higher thermal stability are prepared as the hole tunneling layer, and the n+ layer formed by doping polysilicon with gradient V group elements is used as the electron transmission layer, so that the doped polysilicon layer with better passivation performance is prepared, ohmic contact can be effectively improved, and filling factors are improved; meanwhile, silicon nitride with high thermal stability and small valence band offset is introduced to form an electron tunneling layer, so that the internal expansion of doping elements can be avoided; the open circuit voltage and short circuit current of the battery are raised.
Description
Technical Field
The invention belongs to the field of solar photovoltaic industry, and particularly relates to a POLO-IBC passivation contact battery and a preparation method thereof.
Background
Along with the continuous development of scientific technology, the development of key technology for developing large-size high-efficiency crystalline silicon batteries in green energy sources is imperative. Currently, PERC (Passivated Emitter and Rear Cell) solar cells of P-type monocrystalline silicon substrates have been produced on a large scale with a mass production level of about 23.5%, but their efficiency has further improved and stopped due to recombination caused by metal contact. Therefore, the passivation contact needs to be studied vigorously. Currently, the passivation contact batteries which start large-scale production expansion are TOPCon (Tunnel Oxide Passivated Contacts) and HJT (Heterojunction with Intrinsic Thin Layer), and the mass production efficiency of the batteries reaches 24.5%. But its front side current loss becomes the bottleneck limiting further efficiency, the next generation of cells should be oriented in principle with the structure of passivation contact bond IBC (Interdigitated back contact), e.g. POLO (Polysilicon on Oxide) -IBC, HBC, etc.
The POLO-IBC cell is the highest level of crystalline silicon research and development, and is currently becoming a hotspot for the new generation of technology for solar cell research and development. The passivation is carried out by adopting the polysilicon/silicon oxide film with the doped back surface fully covered, which is one-dimensional passivation contact, namely the back surface recombination is effectively reduced, the open-circuit voltage and the filling factor are improved, and meanwhile, the short-circuit current is improved due to the fact that the front surface is not shielded, so that the higher battery efficiency is obtained. The POLO-IBC technology has a significant advantage over other technologies (such as heterojunction solar cells) in that its excellent thermal stability is compatible with existing PERC solar cell manufacturing lines. However, the development of the structure is also limited by the heat stability and thickness of the tunneling oxide layer in the POLO structure, which is not easy to precisely control, and the doped elements are easily internally expanded to the silicon substrate, so that the complex is aggravated; high-temperature annealing damages the passivation quality of single-layer polysilicon; because the H content of the doped polysilicon film is low, the interface recombination is high, and the like, the improvement of open circuit voltage and filling factor is limited.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is known to a person skilled in the art.
Disclosure of Invention
The first object of the invention is to provide a POLO-IBC passivation contact battery, which is characterized in that a transmission layer with higher concentration is obtained through structural design, so that ohmic contact can be effectively improved, and the filling factor is improved; meanwhile, the doped elements can be prevented from being internally expanded to the silicon substrate, and the open-circuit voltage and the short-circuit current of the battery can be effectively improved.
The technical aim of the invention is realized by the following technical scheme:
the POLO-IBC passivation contact battery comprises a substrate, wherein the front surface of the substrate is sequentially provided with an AlOx passivation layer and a SiNx passivation layer from inside to outside, the back surface of the substrate is sequentially provided with a SiNx tunneling layer, a SiOx tunneling layer, a p+ layer formed by gradient doping of III-group element polycrystalline silicon, a SiNx tunneling layer, an n+ layer formed by gradient V-group element doping of polycrystalline silicon, an AlOx passivation layer, a SiNx passivation layer, a separation belt between N/P, p+ finger and n+ finger from inside to outside. The method comprises the steps of depositing and growing an ultrathin SiNx tunneling layer and a SiOx tunneling layer as hole tunneling layers in a one-step low-temperature PECVD mode, and then forming a hole transport layer by adopting in-situ gradient doping III-group element polycrystalline silicon; the thermal stability of the SiOx tunneling layer is ensured, the thickness of the SiOx tunneling layer is effectively controlled, the internal expansion of doping elements is reduced, and the passivation performance of the hole transport layer is improved. Effectively avoiding the damage of high-temperature annealing to the passivation quality of single-layer polysilicon. Meanwhile, a doped polysilicon layer with better passivation performance is prepared by adopting an in-situ gradient doping mode, so that the passivation quality of single-layer polysilicon is effectively prevented from being damaged by high-temperature annealing; the design of the multilayer film can further increase the concentration of H, reduce interface recombination and effectively improve the open-circuit voltage and short-circuit current of the battery.
The second purpose of the invention is to provide a preparation method of the POLO-IBC passivation contact battery, wherein the preparation of an electron transport layer and a hole transport layer is completed on PECVD equipment, and then a novel POLO-IBC structure can be formed through laser grooving, isolation, cleaning and passivation. The process flow is simplified as a whole, the investment is reduced, and the mass production efficiency of the battery is improved.
The technical aim of the invention is realized by the following technical scheme:
a preparation method of a POLO-IBC passivation contact battery comprises the following operation steps:
(1) Double-sided polishing: taking a monocrystalline silicon wafer as a silicon substrate, and performing surface morphology treatment on the monocrystalline silicon wafer;
(2) Stack deposition tunneling layer-microcrystalline silicon: sequentially growing a SiNx tunneling layer, a SiOx tunneling layer, a p+ layer formed by gradient doping of III-group element polycrystalline silicon, the SiNx tunneling layer, an n+ layer formed by gradient doping of V-group element polycrystalline silicon and a SiOx mask layer on one side of a monocrystalline silicon wafer, and marking the SiNx tunneling layer, the SiOx tunneling layer, the p+ layer formed by gradient doping of III-group element polycrystalline silicon and the SiOx mask layer as the back side;
(3) Back interdigital pattern: forming an interdigital fine gate pattern on the back surface, and simultaneously carrying out laser film opening at the interdigital P/N juncture to expose the silicon substrate;
(4) Cleaning: removing the n+ layer above the p+ layer with the interdigital back and the P/N junction to form a clean surface;
(5) High-temperature annealing: activating the activity of doping elements in the p+ layer and the n+ layer; depositing a SiOx mask layer on the surface;
(6) Front surface light trapping structure: acid washing to remove the SiOx mask layer on the front surface, and then texturing on the front surface; acid washing to remove the SiOx mask layers on the front and back sides and the damage layer generated by front texturing;
(7) Passivation layer: depositing an AlOx passivation layer and a SiNx passivation layer on the front surface and the back surface of the monocrystalline silicon wafer at the same time;
(8) Screen printing: and (3) screen printing on the back surface to form p+ finger and n+ finger, and sintering to obtain the POLO-IBC passivation contact battery.
Preferably, in the step (1), n/p type monocrystalline silicon wafer is used as silicon substrate, and alkali/hydrogen peroxide pre-cleaning is performed in a groove type machine, wherein alkali and H 2 O 2 The volume ratio of (1): 1-3, the temperature is 70-90 ℃ and the time is 2-6min. Organic and particulate matters on the surface of the original silicon wafer can be effectively removed; then polishing is carried out in alkali solution, and the volume ratio of alkali to polishing additive is 5-10:1, the temperature is 70-90 ℃ and the time is 2-6min, and the corrosion of alkali can be slowed down by the molecular adsorption action of the polishing additive, so that better flatness is formed. Specifically, an N-type silicon wafer with high minority carrier lifetime can be used as a silicon substrate, and the resistivity of the N-type silicon wafer is 0.3 to 1.5 omega cm, and the minority carrier lifetime is prolonged>1ms. Or a P-type silicon wafer with high minority carrier lifetime is used as a silicon substrate, the resistivity is 1-2 omega cm, and the minority carrier lifetime is prolonged>0.5ms. The improvement of minority carrier lifetime has a larger gain on efficiency, but the resistivity needs to be balanced to avoid affecting the contact performance, which is a process of balancing minority carrier lifetime and resistivity with each other.
Preferably, in the step (2), a SiNx tunneling layer, a SiOx tunneling layer, a p+ layer formed by gradient doping of III-group element polysilicon, a SiNx tunneling layer, an n+ layer formed by gradient doping of V-group element polysilicon and a SiOx mask layer are sequentially grown on one surface by adopting a PECVD/Cat-CVD/PVD mode; the thicknesses of the SiNx tunneling layer and the SiOx tunneling layer are respectively controlled to be 1-3nm, effective barrier cannot be formed when the thickness is lower than 1nm, and tunneling is difficult to form when the thickness is higher than 3nm; the thickness of the p+ layer formed by gradient doping III group element polysilicon is 200-500nm, and the thickness of the p+ layer cannot be lower than 200nm because the solid solubility of III group element in Si is lower, otherwise, effective transverse carrier transmission cannot be formed, and higher parasitic absorption can be generated when the thickness is higher than 500nm, so that the collection rate of short-circuit current density is low; the thickness of an n+ layer formed by doping polysilicon with gradient V group elements is 50-200nm, the solid solubility of V group elements in Si is higher, the thickness reaches 50nm, and the better contact performance can be formed, but the thickness cannot be too high, and higher parasitic absorption can be generated when the thickness is larger than 200nm, so that the collection rate of short-circuit current density is low.
Preferably, in the step (3), an interdigital III-doped fine grid pattern is formed on the back by utilizing a laser film opening mode (40-60W, 532nm wavelength), and the line width of the P layer is 70-200 mu m; and simultaneously, laser ablation etching (30-50W, 532nm wavelength) is adopted to perform laser film opening at the interdigital P/N juncture to expose the N/P type silicon substrate, wherein the grooving depth is 3-6 mu m. The groove depth is more than 3 mu m, so that the doped polysilicon is completely removed, but the groove depth is not too deep, when the groove depth is more than 6 mu m, extra recombination is generated, the line width is 10-50 mu m, and the interval only needs to cut off the lap joint of P/N, so that the gap is not too wide, and the influence on the collection of current is avoided.
Preferably, in the step (5), the activity of the doping element in the p+ layer and the n+ layer is activated by means of high-temperature annealing. Wherein the highest concentration of n+ layer surface is 2-6X10 20 atoms/cm, junction depth of 0.1-0.2 μm; the highest concentration of the surface of the p+ layer is 8 multiplied by 10 19 -3×10 20 atoms/cm 3 The junction depth is 0.3-0.6 μm. The conditions of the high-temperature annealing are as follows: the aerobic propulsion is carried out at 850-1000 ℃ for a process time of within 0.5-1 h. Where either the temperature is too low or the time is too short to activate the activity of the doping element; on the contrary, the internal expansion of the doping element can affect the passivation performance, and the junction depth is 0.1-0.2 μm.
Preferably, in the step (5), the thickness of the SiOx mask layer is 20-50nm, the SiOx has higher compactness, and the time for subsequent cleaning is satisfied when the thickness exceeds 20 nm; too thick adds unnecessary production costs.
Preferably, in step (6), HF/HNO having a chain weight fraction of 5%/10% is used 3 The SiOx mask layer on the front surface is removed by the mixed solution, and the front surface suede with the reflectivity of 9-10% is formed by using a groove type alkali suede making mode, wherein in order to increase the light absorption, the lower the reflectivity is, the better the reflectivity is, but the lower the passivation compound influence is considered, the reflectivity is not too low.
Preferably, in the step (7), a plasma atomic layer deposition (PEALD)/Atomic Layer Deposition (ALD) technology is used to perform double-sided passivation on aluminum oxide (AlOx), the thickness of the front-side and back-side AlOx passivation layers is 3-10nm, wherein a thickness greater than 3nm can achieve a good passivation effect, and too high results in cost waste and mismatching of metallization process; the method is characterized in that double-sided passivation silicon nitride (SiNx) is carried out on the front side and the back side in a PECVD mode, the thickness of a SiNx passivation layer is 70-90nm, the thickness is the optimal range value of a blue film, light can be well absorbed, the refractive index is 1.8-2.1, the PID effect is considered, and excessive high refractive index can cause extinction absorption, so that current collection is not facilitated.
Preferably, in the step (8), screen printing is performed by using non-burn-through silver paste; the sintering temperature is 700-850 ℃.
The beneficial effects of the invention are as follows:
(1) According to the novel passivation contact structure suitable for the POLO-IBC battery, the ultrathin SiNx tunneling layer and the SiOx tunneling layer with high thermal stability are prepared to serve as the hole tunneling layer, compared with a single-layer tunneling oxide layer, the thickness of the novel passivation contact structure can be effectively controlled, the inward expansion of doping elements is avoided, the concentration of H can be increased through the design of a multilayer film, and interface recombination is reduced. And then, the p+ layer formed by gradient doping of III-group element polysilicon is used as a hole transport layer, so that the thermal stability of the hole tunneling layer is ensured, the thickness of the hole tunneling layer is effectively controlled, and the passivation quality of single-layer polysilicon is effectively prevented from being damaged by high-temperature annealing. Compared with the existing SiOx/p+ -poly-Si layer structure, the passivation performance of the p+ layer can be improved while the internal expansion of doping elements is obviously reduced. The damage of high-temperature annealing to the passivation quality of single-layer polysilicon is effectively avoided, and the H passivation performance and the transverse conductivity of the tunneling layer are increased.
(2) According to the invention, the thickness and doping concentration of each layer are precisely controlled in an in-situ gradient doping mode, the p+ layer formed by gradient doping of III-group element polysilicon is used as a hole transmission layer, the n+ layer formed by gradient V-group element doping of polysilicon is used as an electron transmission layer, so that the doped polysilicon layer with better passivation performance is prepared, the balance of passivation, optical parasitic absorption and conductivity of the polysilicon layer is ensured, the passivation performance of the polysilicon layer is not lost while good conductivity is realized, and the optical parasitic absorption of the polysilicon is reduced. Further, silicon nitride with high thermal stability and small valence band offset is introduced between the p+ layer and the n+ layer to form an electron tunneling layer, so that internal expansion of doping elements can be avoided; the open-circuit voltage and the short-circuit current of the battery are effectively improved.
(3) The invention forms the required P region, N region and isolation zone between N/P by laser grooving and imaging, and activates the activity of doping elements in the p+ layer and the n+ layer by cleaning and high temperature annealing to form the required electron transport layer and hole transport layer. Due to the in-situ gradient doping mode, the transmission layer is guaranteed to have higher concentration, back surface recombination can be effectively reduced, ohmic contact can be effectively improved, and filling factors are improved; meanwhile, the preparation process is simple, the preparation of the electron transport layer and the hole transport layer is finished only on PECVD equipment, and then a novel POLO-IBC structure can be formed through the modes of laser grooving isolation, cleaning and passivation. The technological process is simplified on the whole, the investment is reduced, the efficiency is further improved by more than 0.2 percent compared with the conventional POLO-IBC battery structure, and the industrialized popularization is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
Fig. 1 is a schematic structural diagram of a POLO-IBC passivation contact cell in an embodiment of the present invention;
FIG. 2 is a flow chart of the preparation of a conventional POLO-IBC passivated contact cell of comparative example 1;
FIG. 3 is a flow chart of the preparation of a conventional POLO-IBC passivated contact cell in comparative example 2;
FIG. 4 is a flow chart of the preparation of a POLO-IBC passivated contact cell in an embodiment of the invention;
FIG. 5 is a graph showing the gradient doping profile of a p+ -poly layer in an embodiment of the present invention;
FIG. 6 is a graph showing the graded doping profile of an n+ -poly layer in an embodiment of the present invention.
Reference numerals: 1. a base; 2. an AlOx passivation layer; 3. a SiNx passivation layer; 4. a SiNx tunneling layer; 5. a SiOx tunneling layer; 6. a p+ layer formed by gradient doping of III-group element polysilicon; 7. a SiNx tunneling layer; 8. an n+ layer formed by gradient doping of V group element polysilicon; 9. an AlOx passivation layer; 10. a SiNx passivation layer; 11. a spacer between N/P; 12. p+ finger; 13. n+ finger.
Detailed Description
In order to further describe the technical means and effects adopted by the invention to achieve the preset aim, the specific implementation, the characteristics and the effects of the POLO-IBC passivation contact battery provided by the invention are described in detail below.
In the examples of the present invention, commercially available materials were sourced as follows:
example 1
The POLO-IBC passivation contact battery shown in fig. 1 comprises a substrate 1, wherein the front surface of the substrate is sequentially provided with an AlOx passivation layer 2 and a SiNx passivation layer 3 from inside to outside, and the back surface of the substrate is sequentially provided with a SiNx tunneling layer 4, a SiOx tunneling layer 5, a p+ layer 6 formed by gradient doping of III-group element polycrystalline silicon, a SiNx tunneling layer 7, an n+ layer 8 formed by gradient V-group element doping of polycrystalline silicon, an AlOx passivation layer 9, a SiNx passivation layer 10, a separation belt 11 between N/P, a p+ finger12 and an n+ finger13 from inside to outside.
As shown in fig. 4 to 6, a manufacturing procedure of a POLO-IBC passivation contact battery is as follows:
the N-type silicon chip with high minority carrier lifetime is used as a matrix, the resistivity is 0.3-1.5 omega cm, and the minority carrier lifetime is more than 1ms.
(1) Double-sided polishing: in the trough machine, RCA1# (NaOH/H) is adopted first 2 O 2 ) Pre-cleaning; and then alkali polishing is performed in an alkali/polishing additive solution.
(2) Deposition of tunneling layer-microcrystalline silicon: sequentially growing a SiNx tunneling layer, a SiOx tunneling layer, a p+ layer formed by gradient doping of III-group element polycrystalline silicon, the SiNx tunneling layer, an n+ layer formed by gradient doping of V-group element polycrystalline silicon and a SiOx mask layer on one side in a PECVD mode, wherein the thicknesses of the SiNx tunneling layer and the SiOx tunneling layer are respectively controlled to be 1nm and 1.5nm, and the thickness of the gradient boron-doped polycrystalline silicon is 300nm; the thickness of the gradient phosphorus doped polysilicon is 100nm.
(3) Back interdigital pattern: forming a fine grid pattern in the boron doped region by utilizing 532nm laser with power of more than 30W, wherein the line width of the P layer is 150 mu m; laser film opening is carried out at the interdigital P/N interface in a mode of ablation etching with 532nm laser and power of more than 50W, the N/P type silicon substrate is exposed, the grooving depth is 3-6 mu m, and the line width is 10-50 mu m.
(4) Cleaning: removing the n+ layer above the p+ layer with the interdigital back and the P/N junction by adopting a groove type alkali/polishing additive alkali polishing mode to form a clean surface;
(5) High-temperature annealing: the aerobic propulsion is carried out at 850-920 ℃ for a process time of less than 1 h. The highest surface concentration of the formed p+ layer is 1×10 20 atoms/cm 3 Junction 0.4 μm; the highest surface concentration of the n+ layer is 4×10 20 atoms/cm 3 Junction depth is 0.15 μm; the SiOx mask layer has a thickness of 40nm. The ECV curve is shown in fig. 4.
(6) Front surface light trapping structure: and removing the SiOx mask layer on the front surface by using HF with the chain mass fraction of 5%, and forming a suede with the reflectivity of 10% by using a groove type alkali velvet making mode. The front and back SiOx mask layers and the damaged layer were cleaned by mass fraction 4% hf.
(7) Passivation layer: double-sided deposition of an AlOx passivation layer is carried out by utilizing an Atomic Layer Deposition (ALD) technology, and the thickness is controlled to be 3nm; and then, plating a SiNx passivation layer on the two sides by adopting a PECVD mode, wherein the thickness is controlled to be 75-80nm, and the refractive index is 2.0.
(8) Screen printing: firstly, printing a main grid on the back, secondly, printing an n+ layer and a p+ layer fine grid, wherein the line width of a p+ finger is 30 mu m, the line width of the n+ finger is 25 mu m, and finally, completing the manufacturing of a finished product through the sintering process temperature of 740 ℃.
Example 2
The POLO-IBC passivation contact battery shown in fig. 1 comprises a substrate 1, wherein the front surface of the substrate is sequentially provided with an AlOx passivation layer 2 and a SiNx passivation layer 3 from inside to outside, the back surface of the substrate is sequentially provided with a SiNx tunneling layer 4, a SiOx tunneling layer 5, a p+ layer 6 formed by gradient doping of III-group element polycrystalline silicon, a SiNx tunneling layer 7, an n+ layer 8 formed by gradient V-group element doping of polycrystalline silicon, an AlOx passivation layer 9, a SiNx passivation layer 10, a separation belt 11 between N/P, a p+ finger12 and an n+ finger13 from inside to outside.
As shown in fig. 4 to 6, a manufacturing procedure of a POLO-IBC passivation contact battery is as follows:
the p-type silicon chip with high minority carrier lifetime is used as a matrix, the resistivity is 1-2 omega cm, and the minority carrier lifetime is more than 0.5ms.
(1) Double-sided polishing: in the trough machine, RCA1# (NaOH/H) is adopted first 2 O 2 ) Pre-cleaning; and then polished in an alkali (NaOH) solution.
(2) Deposition of tunneling layer-microcrystalline silicon: sequentially growing a SiNx tunneling layer, a SiOx tunneling layer, a p+ layer formed by gradient doping of III-group element polycrystalline silicon, the SiNx tunneling layer, an n+ layer formed by gradient doping of V-group element polycrystalline silicon and a SiOx mask layer on one side in a Cat-CVD mode, wherein the thicknesses of the SiNx tunneling layer and the SiOx tunneling layer are respectively controlled to be 1.5nm and 1nm, and the thickness of the gradient boron-doped polycrystalline silicon is 250nm; gradient phosphorus doped polysilicon thickness 80nm.
(3) Back interdigital pattern: forming a fine grid pattern in the boron doped region by utilizing 532nm laser with power of 40W, wherein the line width of the P layer is 180 mu m; laser film opening is carried out at the interdigital P/N interface by utilizing 532nm laser and a power 45W ablation etching mode, the P-type silicon substrate is exposed, the slotting depth is 5 mu m, and the line width is 30 mu m.
(4) Cleaning: removing the n+ layer above the p+ layer on the back interdigital and the P/N juncture by adopting a groove type TMAH (tetramethyl ammonium hydroxide) alkali polishing mode to form a clean surface;
(5) High-temperature annealing: aerobic propulsion is carried out at 1000 ℃ for a process time of less than 30 min. Forming a maximum surface concentration of 1.5X10 20 atoms/cm 3 A p+ layer having a junction depth of 0.3 μm; the highest surface concentration is 3X 10 20 atoms/cm 3 An n+ layer having a junction depth of 0.1 μm; depositing a SiOx mask layer on the surface; the SiOx mask layer has a thickness of 50nm.
(6) Front surface light trapping structure:by means of HF/HNO with a chain mass fraction of 5%/10% 3 And removing the SiOx mask layer on the front surface by the mixed solution, and forming a suede with the reflectivity of 9% by using a groove type alkali velvet making mode. The front and back SiOx mask layers and the damage layer were cleaned by means of HF/HCl 5%/5% by mass.
(7) Passivation layer: performing double-sided passivation on the AlOx passivation layer by using a plasma atomic layer deposition (PEALD) technology, wherein the thickness is controlled to be 4nm; and then, plating a SiNx passivation layer on the two sides by adopting a PECVD mode, wherein the thickness is controlled at 85nm, and the refractive index is 1.9.
(8) Screen printing: firstly, printing a main grid on the back, secondly, printing an n+ layer and a p+ layer fine grid, wherein the line width of a p+ finger is 30 mu m, the line width of the n+ finger is 25 mu m, and finally, completing the manufacturing of a finished product through the sintering process temperature of 750 ℃.
Comparative example 1
The conventional process shown in fig. 2 was used to fabricate a POLO-IBC passivated contact cell. The manufacturing process comprises the following steps:
(1) Double-side polishing, namely, taking a monocrystalline silicon wafer as a silicon substrate, and carrying out surface morphology treatment on the monocrystalline silicon wafer;
(2) Tunnel oxide layer-microcrystalline silicon deposition-growing a silicon oxide layer by a thermal oxidation mode for 2nm, and performing microcrystalline silicon deposition by an LPCVD mode for 200nm;
(3) Boron doping annealing, namely taking boron trichloride as a boron source, and doping for 100min at 900-1000 ℃;
(4) Mask layer growth-growing a 50nm oxide layer as a mask layer in a thermal oxidation mode;
(5) Laser film opening 1- -thin gate pattern is formed in boron doped region with power of 60W by 532nm laser;
(6) Cleaning 1, namely cleaning silicon powder in a slotting area by adopting an alkali polishing mode, and cleaning by hydrofluoric acid to obtain a clean surface;
(7) Tunnel oxide layer-microcrystalline silicon deposition-growing a silicon oxide layer by a thermal oxidation mode for 2nm, and performing microcrystalline silicon deposition by an LPCVD mode for 200nm;
(8) Phosphorus doping annealing, namely doping phosphorus oxychloride as a phosphorus source for 100min at 800-900 ℃;
(9) Single-side texturing-groove alkali texturing mode to form 10% reflectivity suede;
(10) Laser film opening 2-forming a fine grid pattern in a phosphorus doped region by utilizing 532nm laser with power of 50W;
(11) Cleaning 2, namely cleaning silicon powder in a slotting area in an alkali polishing mode, and cleaning by hydrofluoric acid to obtain a clean surface;
(12) Passivation-in situ deposition of alumina 5nm, pecvd deposition of silicon nitride 80nm;
(13) Screen-front and back electrode printing by screen printing and sintering in a chain sintering furnace.
Comparative example 2
The conventional process shown in fig. 3 was used to fabricate a POLO-IBC passivated contact cell. The manufacturing process comprises the following steps:
(1) Double-sided texturing-groove alkali texturing mode to form a suede with reflectivity of 11%;
(2) Oxidation-growing a 50nm oxide layer as a mask layer in a thermal oxidation manner;
(3) Single-sided polishing-after removing oxide layer on HF single side, alkali polishing treatment is carried out;
(4) Tunnel oxide layer-microcrystalline silicon deposition-growing a silicon oxide layer by a thermal oxidation mode for 2nm, and performing microcrystalline silicon deposition by an LPCVD mode for 200nm;
(5) Boron doping annealing, namely taking boron tribromide as a boron source, and doping for 100min at 900-1000 ℃;
(6) Film growth-growing a 60nm oxide layer as a mask layer in a thermal oxidation mode;
(7) Laser film opening 1- -thin gate pattern is formed in boron doped region with power of 60W by 532nm laser;
(8) Cleaning 1, namely cleaning silicon powder in a slotting area by adopting an alkali polishing mode, and cleaning by hydrofluoric acid to obtain a clean surface;
(9) Tunnel oxide layer-microcrystalline silicon deposition-growing a silicon oxide layer by a thermal oxidation mode for 2nm, and performing microcrystalline silicon deposition by an LPCVD mode for 200nm;
(10) Phosphorus doping annealing, namely doping phosphorus oxychloride as a phosphorus source for 100min at 800-900 ℃;
(11) Laser film opening 2-thin gate pattern is formed in boron doped region with power of 60W by 532nm laser;
(12) Cleaning 2, namely cleaning silicon powder in a slotting area in an alkali polishing mode, and cleaning by hydrofluoric acid to obtain a clean surface;
(13) Passivation-in situ deposition of alumina 3nm, pecvd deposition of silicon nitride 80nm;
(14) Screen-front and back electrode printing by screen printing and sintering in a chain sintering furnace.
Battery performance test results
The blue membrane structural characterization, i.e. the test before electrode preparation, was performed for the examples and comparative examples, and the performance test results are shown in table 1: the data is cell structure blue patch data, which may reflect that the scheme is practicable.
TABLE 1
The POLO-IBC passivation contact battery prepared in the embodiment 1-2 has a transmission layer with higher concentration, so that ohmic contact can be effectively improved, and the filling factor can be improved; meanwhile, the doped elements can be prevented from being internally expanded to the silicon substrate, and the open-circuit voltage and the short-circuit current of the battery can be effectively improved.
Compared with the embodiment 1, the process has more cleaning and high temperature steps, is too complicated, has large difficulty in controlling the production line, is not beneficial to industrialization and has high yield loss.
Comparative example 2 this procedure is similar to procedure 1, but the preparation procedure is too complex and the window of the tunnel oxide is too narrow compared to example 1; is not beneficial to industrialization and has high yield loss in the process.
It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A pouo-IBC passivated contact cell characterized by: the passivation contact battery comprises a substrate, wherein the front surface of the substrate is sequentially provided with an AlOx passivation layer and a SiNx passivation layer from inside to outside, the back surface of the substrate is sequentially provided with a SiNx tunneling layer, a SiOx tunneling layer, a p+ layer formed by gradient doping of III-group element polycrystalline silicon, a SiNx tunneling layer, an n+ layer formed by gradient V-group element doping of polycrystalline silicon, an AlOx passivation layer, a SiNx passivation layer, an isolation belt between N/P, p+ finger and n+ finger from inside to outside.
2. The method for preparing the POLO-IBC passivation contact battery according to claim 1, which is characterized in that: the method comprises the following operation steps:
(1) Double-sided polishing: taking a monocrystalline silicon wafer as a silicon substrate, and performing surface morphology treatment on the monocrystalline silicon wafer;
(2) Stack deposition tunneling layer-microcrystalline silicon: sequentially growing a SiNx tunneling layer, a SiOx tunneling layer, a p+ layer formed by gradient doping of III-group element polycrystalline silicon, the SiNx tunneling layer, an n+ layer formed by gradient doping of V-group element polycrystalline silicon and a SiOx mask layer on one side of the monocrystalline silicon piece, and marking the SiNx tunneling layer, the SiOx tunneling layer, the p+ layer formed by gradient doping of III-group element polycrystalline silicon and the SiOx mask layer as the back side;
(3) Back interdigital pattern: forming an interdigital fine gate pattern on the back surface, and simultaneously carrying out laser film opening at the interdigital P/N juncture to expose the silicon substrate;
(4) Cleaning: removing the n+ layer above the p+ layer with the interdigital back and the P/N junction to form a clean surface;
(5) High-temperature annealing: activating the activity of doping elements in the p+ layer and the n+ layer; depositing a SiOx mask layer on the surface;
(6) Front surface light trapping structure: acid washing to remove the SiOx mask layer on the front surface, and then texturing on the front surface; acid washing to remove the SiOx mask layer and the damage layer on the front and back;
(7) Passivation layer: depositing an AlOx passivation layer and a SiNx passivation layer on the front surface and the back surface of the monocrystalline silicon wafer at the same time;
(8) Screen printing: and (3) screen printing on the back surface to form p+ finger and n+ finger, and sintering to obtain the POLO-IBC passivation contact battery.
3. The method for preparing the POLO-IBC passivation contact battery according to claim 2, which is characterized in that: in the step (1), an n/p type monocrystalline silicon wafer is used as a silicon substrate, alkali/hydrogen peroxide pre-cleaning is carried out, and then polishing is carried out, so that a flat surface structure is formed.
4. The method for preparing the POLO-IBC passivation contact battery according to claim 2, which is characterized in that: in the step (2), the thicknesses of the SiNx tunneling layer and the SiOx tunneling layer are respectively 1-3nm, and the thickness of a p+ layer formed by gradient doping of III-group element polycrystalline silicon is 200-500nm; the thickness of the n+ layer formed by doping polysilicon with gradient V group elements is 50-200nm.
5. The method for preparing the POLO-IBC passivation contact battery according to claim 2, which is characterized in that: in the step (3), an interdigital III-group doped fine grid pattern is formed on the back by utilizing a laser film opening mode, and the line width of a P layer is 70-200 mu m; and meanwhile, laser film opening is carried out at the interdigital P/N juncture to expose the N/P type silicon substrate, the slotting depth is 3-6 mu m, and the line width is 10-50 mu m.
6. The method for preparing the POLO-IBC passivation contact battery according to claim 2, which is characterized in that: in the step (5), the activity of doping elements in the p+ layer and the n+ layer is activated by a high-temperature annealing mode; wherein the highest concentration of n+ layer surface is 2-6X10 20 atoms/cm 3 The junction depth is 0.1-0.2 mu m; the highest concentration of the surface of the p+ layer is 8 multiplied by 10 19 -3×10 20 atoms/cm 3 The junction depth is 0.3-0.6 mu m.
7. The method for preparing the POLO-IBC passivation contact battery according to claim 2, which is characterized in that: in the step (5), the SiOx mask layer has a thickness of 20-50nm.
8. The method for preparing the POLO-IBC passivation contact battery according to claim 2, which is characterized in that: in the step (6), the SiOx mask layer on the front surface is removed by a chain type acid washing/acid etching mode, and a good front surface suede is formed by a groove type alkali suede making mode.
9. The method for preparing the POLO-IBC passivation contact battery according to claim 2, which is characterized in that: in the step (7), the thickness of the front surface and the back surface AlOx passivation layers is 3-10 nm; the SiNx passivation layer has a thickness of 70-90nm and a refractive index of 1.8-2.1.
10. The method for preparing the POLO-IBC passivation contact battery according to claim 2, which is characterized in that: in the step (8), screen printing is carried out by adopting non-burn-through silver paste, and the sintering temperature is 700-850 ℃.
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| CN107644805A (en) * | 2017-08-15 | 2018-01-30 | 中国科学院宁波材料技术与工程研究所 | Hole passivation tunnelling film, preparation method and its application in solar cell |
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| CN115692544A (en) * | 2021-07-28 | 2023-02-03 | 环晟光伏(江苏)有限公司 | Preparation method of passivation structure of Topcon battery |
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