CN115036381A - P-type silicon back contact battery and preparation method thereof - Google Patents
P-type silicon back contact battery and preparation method thereof Download PDFInfo
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- CN115036381A CN115036381A CN202210580755.8A CN202210580755A CN115036381A CN 115036381 A CN115036381 A CN 115036381A CN 202210580755 A CN202210580755 A CN 202210580755A CN 115036381 A CN115036381 A CN 115036381A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 211
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 211
- 239000010703 silicon Substances 0.000 title claims abstract description 211
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 67
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 66
- 238000009792 diffusion process Methods 0.000 claims abstract description 66
- 239000011574 phosphorus Substances 0.000 claims abstract description 66
- 238000002161 passivation Methods 0.000 claims description 73
- 238000005530 etching Methods 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 31
- 238000000151 deposition Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 239000011800 void material Substances 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 13
- 230000000694 effects Effects 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 60
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 229910052733 gallium Inorganic materials 0.000 description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 5
- 229910000077 silane Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000002585 base Substances 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- OHZZTXYKLXZFSZ-UHFFFAOYSA-I manganese(3+) 5,10,15-tris(1-methylpyridin-1-ium-4-yl)-20-(1-methylpyridin-4-ylidene)porphyrin-22-ide pentachloride Chemical compound [Cl-].[Cl-].[Cl-].[Cl-].[Cl-].[Mn+3].C1=CN(C)C=CC1=C1C(C=C2)=NC2=C(C=2C=C[N+](C)=CC=2)C([N-]2)=CC=C2C(C=2C=C[N+](C)=CC=2)=C(C=C2)N=C2C(C=2C=C[N+](C)=CC=2)=C2N=C1C=C2 OHZZTXYKLXZFSZ-UHFFFAOYSA-I 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000003518 caustics Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000010329 laser etching Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 125000004437 phosphorous atom Chemical group 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- DLYUQMMRRRQYAE-UHFFFAOYSA-N tetraphosphorus decaoxide Chemical compound O1P(O2)(=O)OP3(=O)OP1(=O)OP2(=O)O3 DLYUQMMRRRQYAE-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000005922 Phosphane Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910000064 phosphane Inorganic materials 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- UHZYTMXLRWXGPK-UHFFFAOYSA-N phosphorus pentachloride Chemical compound ClP(Cl)(Cl)(Cl)Cl UHZYTMXLRWXGPK-UHFFFAOYSA-N 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 230000017105 transposition Effects 0.000 description 1
- IVIIAEVMQHEPAY-UHFFFAOYSA-N tridodecyl phosphite Chemical compound CCCCCCCCCCCCOP(OCCCCCCCCCCCC)OCCCCCCCCCCCC IVIIAEVMQHEPAY-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
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Abstract
The embodiment of the invention provides a P-type silicon back contact battery and a preparation method thereof, belonging to the technical field of silicon wafer battery preparation, wherein the battery comprises: the Si substrate is a P-type Si substrate; a plurality of sections of phosphorus diffusion layers are arranged on the reverse side of the Si substrate at intervals, and a blank area is reserved between the phosphorus diffusion layers of the adjacent sections; the first doped silicon layer is provided with a plurality of sections, and the plurality of sections of the first doped silicon layer are arranged on the plurality of sections of the phosphorus diffusion layers one by one; the phosphorus diffusion layer above the first doped silicon layer and the Si substrate form a PN junction; the second doped silicon layer is provided with a plurality of sections, and the plurality of sections of the second doped silicon layer are arranged in the plurality of blank areas; the electrodes are arranged and are respectively and electrically connected to the first doped silicon layer and the second doped silicon layer; the technical effect of improving the conversion efficiency of the P-type back contact battery is achieved.
Description
Technical Field
The invention relates to the technical field of silicon wafer battery preparation, in particular to a P-type silicon back contact battery and a preparation method thereof.
Background
Solar cells are increasingly used as a new alternative to energy. A solar cell is a device that converts solar energy into electrical energy. The solar cell generates current carriers by utilizing a photovoltaic principle, and then the current carriers are led out by using the electrodes, so that the electric energy is effectively utilized. Based on the distribution mode of the electrodes, the electrodes are divided into a double-sided electrode and a reverse-sided electrode; wherein the cells of the back electrode are also called back contact cells; and specific back contact cells are classified into P-type silicon back contact cells and N-type silicon back contact cells based on the type of the substrate.
At present, the conversion efficiency of a P-type silicon back contact battery is lower than that of an N-type silicon back contact battery, but the price of a P-type silicon wafer is lower than that of an N-type silicon wafer, and equipment for preparing the P-type silicon back contact battery is quite mature.
Therefore, the prior art problems are: how to improve the conversion efficiency of the P-type silicon back contact cell.
Disclosure of Invention
The embodiment of the application provides a P-type silicon back contact battery and a preparation method thereof, and solves the technical problem of how to improve the conversion efficiency of the P-type silicon back contact battery in the prior art; the technical effect of improving the conversion efficiency of the P-type back contact battery is achieved.
The embodiment of the application provides a P type silicon back contact battery, the battery includes: the substrate comprises a Si substrate, a P-type Si substrate and a Si substrate, wherein the Si substrate is a P-type Si substrate; a plurality of sections of phosphorus diffusion layers are arranged on the reverse side of the Si substrate at intervals, and a blank area is reserved between the phosphorus diffusion layers of the adjacent sections; the first doped silicon layer is provided with a plurality of sections, and the plurality of sections of the first doped silicon layer are arranged on the plurality of sections of the phosphorus diffusion layers one by one; the phosphorus diffusion layer above the first doped silicon layer and the Si substrate form a PN junction; the second doped silicon layer is provided with a plurality of sections, and the plurality of sections of the second doped silicon layer are arranged in the plurality of blank areas; and the electrodes are arranged and are respectively and electrically connected to the first doped silicon layer and the second doped silicon layer.
Preferably, a second passivation layer is arranged around the second doped silicon layer, the outer side surface of the second passivation layer is in contact with the Si substrate and the first doped silicon layer in an attaching manner, and the second doped silicon layer is separated from the Si substrate and the first doped silicon layer through the second passivation layer.
Preferably, a first passivation layer is arranged between the phosphorus diffusion layer and the first doped silicon layer, and two ends of the first passivation layer are respectively contacted with the second passivation layers outside the two adjacent sections of second doped silicon layers to coat the first doped silicon layer.
Preferably, the width of each section of the phosphorus diffusion layer is greater than that of the blank area, and the width of the first doped silicon layer is greater than that of the second doped silicon layer.
A preparation method of a P-type silicon back contact battery comprises the following steps: carrying out base material treatment on the Si substrate; the base material treatment of the Si substrate specifically includes: cleaning and texturing a Si substrate; carrying out phosphorus diffusion on the reverse side of the Si substrate to form a phosphorus diffusion layer; generating first passivation layers on the front side and the back side of the Si substrate; forming a first doped silicon layer on the opposite first passivation layer; forming a second doped silicon layer on the opposite second passivation layer; generating an antireflection layer outside the second passivation layer on the front surface; forming electrodes on the first doped silicon layer and the second doped silicon layer on the opposite sides; and further, the first passivation layer and the phosphorus diffusion layer corresponding to the blank area are sequentially removed, and a second passivation layer and a second doped silicon layer are sequentially generated in the blank area.
Preferably, the specific method for forming the first doped silicon layer or the second doped silicon layer is as follows: in-situ doped silicon deposition; or a method of depositing intrinsic silicon first, and then doping source diffusion or ion implantation.
Preferably, the specific method for removing the first doped silicon layer at the specific intervals to form a plurality of blank areas comprises the following steps: generating a first mask layer outside the first doped silicon layer on the reverse side, so that the first doped silicon layer is covered by the first mask layer; etching/corroding the first mask layer locally to enable the part of the first doped silicon layer on the reverse side to be in an exposed state; etching the exposed portions of the first doped silicon layer on the front and back sides to form a blank region in the first doped silicon layer on the back side.
Preferably, a second passivation layer is formed between the first doped silicon layer and the second doped silicon layer for separation, and the phosphorus diffusion layer above the first doped silicon layer and the Si substrate form a PN junction.
Preferentially, when the first passivation layer corresponding to the blank area is removed, the first passivation layer on the front surface is removed at the same time; and simultaneously generating a second passivation layer on the front surface and the first doped silicon layer when the second passivation layer is generated in the blank area.
Preferably, when the phosphorus diffusion layer corresponding to the blank region is removed, the etching is performed until the Si substrate corresponding to the phosphorus diffusion layer is exposed.
Preferably, the specific method of forming the second doped silicon layer on the opposite second passivation layer comprises: and generating a second doped silicon layer on the second passivation layer on the front side and the back side: filling the second doped silicon layer in the blank area of the first doped silicon layer; generating a second mask layer outside the second doped silicon layer on the reverse side; locally etching/corroding the second mask layer to enable the part of the second doped silicon layer corresponding to the first doped silicon layer to be in an exposed state; and corroding the exposed parts of the second doped silicon layers on the front and back surfaces, and enabling the first mask layer of the back surface corresponding to the first doped silicon layer to be in an exposed state.
Preferably, the first doped silicon layer and the second doped silicon layer have a thickness of
Preferably, the Si substrate is doped with gallium, and the doping concentration of the gallium is less than 7.5x10 15 cm -3 (ii) a And the resistivity of the substrate layer is greater than 1.8 omega cm.
Preferably, the first mask layer, the second mask layer and the anti-reflection layer may be made of the same material.
One or more technical solutions in the embodiments of the present application have at least one or more of the following technical effects:
1. in the embodiment of the application, a phosphorus diffusion layer is designed in a cell structure, and the specific phosphorus diffusion layer is arranged between a P-type silicon Si substrate and an N-type first doped silicon layer, so that the phosphorus diffusion layer is favorable for improving the collection of electrons, reducing the recombination of electrons and multiple electrons (holes) at an interface and improving the conversion efficiency; in addition, when the phosphorus diffusion layer corresponding to the blank area is removed, the etching is carried out until the Si substrate corresponding to the phosphorus diffusion layer is exposed; the collection of holes in the P-type second doped silicon layer is enhanced by thoroughly removing the phosphorus diffusion layer in the region of the second doped silicon layer to be generated; the technical problem of how to improve the conversion efficiency of the P-type silicon back contact battery in the prior art is solved; the technical effect of improving the conversion efficiency of the P-type back contact battery is achieved.
Drawings
Fig. 1 is a schematic structural view of a semi-finished battery fabricated at step S305 in an embodiment of the present application;
FIG. 2 is a schematic structural diagram of a P-type silicon back contact cell in an embodiment of the present application;
fig. 3 is a flow chart illustrating a method for manufacturing a P-type silicon back contact cell according to an embodiment of the present disclosure;
FIG. 4 is a flow chart of a specific preparation method of the preparation method of FIG. 3.
Reference numerals: 1. a Si substrate; 2. a phosphorus diffusion layer; 3. a first passivation layer; 4. a first doped silicon layer; 5. a first mask layer; 6. a blank area; 7. a second passivation layer; 8. a second doped silicon layer; 9. a second mask layer; 10. an anti-reflective layer; 11. and an electrode.
Detailed Description
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. In the present application, the steps/methods in the front-back sequence are not defined, and it should be understood that there is no specific sequence, and the sequence can be reversed; the term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be considered as limiting the present application.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In order to better understand the technical scheme, the technical scheme is described in detail in the following with reference to the attached drawings of the specification and specific embodiments.
A P-type silicon back contact cell for improving conversion efficiency, referring to the accompanying fig. 1-2, comprising: a Si substrate 1, a first doped silicon layer 4, a second doped silicon layer 8, and an electrode 11; wherein the Si substrate 1 is a P-type Si substrate 1; a plurality of sections of phosphorus diffusion layers 2 are arranged on the reverse side of the Si substrate 1 at intervals, and a blank area 6 is reserved between the phosphorus diffusion layers 2 of the adjacent sections; the first doped silicon layer 4 is provided with a plurality of sections, the plurality of sections of the first doped silicon layer 4 are arranged on the plurality of sections of the phosphorus diffusion layers 2 one by one, and the width of each section of the phosphorus diffusion layer 2 is greater than that of the blank area 6, so that the width of the first doped silicon layer 4 is greater than that of the second doped silicon layer 8, and the structural requirement of the back contact cell is met; the phosphorus diffusion layer 2 above the first doped silicon layer 4 and the Si substrate 1 form a PN junction; the second doped silicon layer 8 is provided with a plurality of sections, and the plurality of sections of the second doped silicon layer 8 are arranged in the plurality of blank regions 6; and a plurality of electrodes 11 are arranged, and the plurality of electrodes 11 are respectively and electrically connected to the first doped silicon layer 4 and the second doped silicon layer 8.
Regarding the second doped silicon layer 8, a second passivation layer 7 is arranged around the periphery of the second doped silicon layer 8, the outer side surface of the second passivation layer 7 is in contact with the Si substrate 1 and the first doped silicon layer 4 in a fitting manner, and the second doped silicon layer 8 is separated from the Si substrate 1 and the first doped silicon layer 4 through the second passivation layer 7.
With respect to the first doped silicon layer 4, the thickness of the first doped silicon layer 4 and the second doped silicon layer 8 are within
A first passivation layer 3 is arranged between the phosphorus diffusion layer 2 and the first doped silicon layer 4, and two ends of the first passivation layer 3 are respectively contacted with a second passivation layer 7 outside two adjacent sections of second doped silicon layers 8 so as to coat the first doped silicon layer 4.
In addition, as for the structure of the reverse side of the cell, in the process of preparing the second doped silicon layer 8, the first mask layer 5 is provided on the first doped silicon layer 4; in the preparation of the electrode 11 connected to the first doped silicon layer 4, a second mask layer 9 is provided on the second doped silicon layer 8. As for the structure of the front surface of the cell, the front surface of the Si substrate 1 is provided with the second passivation layer 7 and the antireflection layer 10 in this order.
A method for manufacturing a P-type silicon back contact cell, referring to fig. 3-4 of the specification, for improving the conversion efficiency of a P-type silicon back contact cell of a conventional structure, the method comprising:
s1, the Si substrate 1 is subjected to base material processing.
S101, cleaning and texturing the Si substrate 1.
Cleaning and texturing a P-type silicon Si substrate 1; the Si substrate 1 can be cleaned by ultrasonic cleaning, RCA cleaning, heating, boiling and washing; and (3) texturing the front side and the back side of the Si substrate 1 after cleaning, wherein the purpose of texturing is to form a textured surface on the surface of the Si substrate 1 so as to reduce the reflectivity of a battery piece, and secondary reflection can be increased due to the uneven textured surface, so that the optical path and the incident mode are changed. The single crystal is treated by alkali under normal conditions, and a pyramid texture surface can be obtained; the porous random suede can be obtained by treating the polycrystal with acid.
Specifically, after texturing, the upper and lower end faces of the Si substrate 1 are respectively in a rough texture structure. The specific rough texture may be a wave-like pattern, pyramid or inverted pyramid pattern to increase surface area while reducing reflection of incident light.
Regarding the specific description of the Si substrate 1, in order to ensure minority carrier lifetime, it is preferable to improve the material integrity of the Si substrate 1, the Si substrate 1 is specifically a P-type silicon wafer, the Si substrate 1 is doped with gallium, and the doping concentration of gallium is less than 7.5x10 15 cm -3 The resistivity of the Si substrate 1 is more than 1.8 omega cm; further, the doping concentration of gallium is less than 7.1x10 15 cm -3 The resistivity of the Si substrate 1 is more than 2.0 omega cm; furthermore, the doping concentration of gallium is less than 4.6x10 15 cm -3 The resistivity of the Si substrate 1 is greater than 3.0 Ω · cm. Of course, the Si substrate 1 may also be boron-doped to build a P-type silicon substrate.
S102, phosphorus diffusion is carried out on the reverse side of the Si substrate 1, and a phosphorus diffusion layer 2 is formed.
The phosphorus diffusion process is carried out at the temperature of 850-900 ℃, so that the lower part of the Si substrate 1 forms a phosphorus diffusion layer 2 due to diffusion, and the P-type silicon-based Si substrate 1 and the phosphorus diffusion layer 2 above the first doped silicon layer 4 construct a PN junction. Particularly, the phosphorus diffusion layer 2 is designed in the cell structure, which is beneficial to improving the collection of electrons, reducing the recombination of electrons and multiple electrons (holes) at an interface and improving the conversion efficiency.
POCl is used for phosphorus diffusion 3 ，POCl 3 The liquid phosphorus source is adopted, and the liquid phosphorus source diffusion has the advantages of higher production efficiency, good stability, uniform and flat prepared PN junction, good surface of the phosphorus diffusion layer 2 and the like.
And S103, removing the PSG formed by phosphorus diffusion.
After the phosphorus diffusion layer 2 is formed, a first passivation layer 3 and a first doped silicon layer 4 are sequentially generated, the first doped silicon layer 4 is removed at intervals in a targeted manner to form a plurality of blank areas 6, the first passivation layer 3 and the phosphorus diffusion layer 2 corresponding to the blank areas 6 are further sequentially removed, and a second passivation layer 7 and a second doped silicon layer 8 are sequentially generated in the blank areas 6.
The PSG formation process is specifically as follows: in the presence of POCl 3 Then, POCl 3 Decomposing at more than 600 deg.C to obtain phosphorus pentachloride (PCl) 5 ) And phosphorus pentoxide (P) 2 O 5 )，PCl 5 Has corrosion effect on the surface of the silicon wafer when oxygen O is available 2 When present, PCl 5 Will decompose into P 2 O 5 And chlorine is released, so that nitrogen is diffused and oxygen with a certain flow is introduced at the same time. P is 2 O 5 Reacting with silicon at diffusion temperature to form silicon dioxide and phosphorus atoms, P 2 O 5 Deposited on the surface of a silicon wafer and continuously reacts with silicon to generate SiO 2 And phosphorus atoms, and forming phosphorus-silicon glass (PSG) on the surface of the silicon wafer.
S2, first passivation layers 3 are formed on both front and back surfaces of the Si substrate 1.
It is understood that the purpose of generating the first passivation layer 3 on the front and back sides of the Si substrate 1 is to passivate a defect state of the surface, such as dangling bonds of the surface; preferably the thickness of the first passivation layer 3
It should be noted that the first passivation layer 3 can be formed in various ways, such as by PECVD or LPCVD deposition; PECVD oxidation methods may also be employed. Thermal oxidation is generally used, and oxygen diffuses into the substrate to form silicon oxide, so that the passivation effect is good.
For example, the first passivation layer 3 may be formed of silicon nitride, silicon oxide, silicon oxynitride, or a composite of two or more of the above materials.
S3, a first doped silicon layer 4 is grown on the opposite first passivation layer 3, the first doped silicon layer 4 being in particular a poly-si (n) layer.
It will be appreciated that the construction of a poly-Si (n) layer with a void 6 is an important step in the manufacture of a bifacial cell, and then the design is such that the void 6 creates a poly-Si (p) layer, and the Si substrate 1 in combination with the poly-Si (n) layer and the poly-Si (p) layer allows for the generation of photogenerated carrier output.
S301, generating a poly-Si (n) layer outside the first passivation layer 3.
It will be appreciated that the thickness of the poly-Si (n) layer in the design is
The poly-Si (n) layer can be formed in two ways:
by adopting a method of LPCVD or PECVD in-situ doped silicon deposition, silane and a doping source (phosphorus) are put in, the concentration of phosphine in reaction gas is about 1 to 2 percent, amorphous silicon layers can be formed on the front surface and the back surface by utilizing LPCVD, and then the amorphous silicon is annealed to form polycrystalline silicon; obtaining single-sided silicon deposition by using PECVD;
method for depositing intrinsic silicon by LPCVD or PECVD, followed by a phosphorus diffusion process (POCl) 3 ) Or ion implantation (but the equipment is expensive, the processing is time-consuming, and the mass production is not suitable); and annealing at high temperature to obtain polycrystalline silicon.
In addition, the LPCVD method is used for manufacturing intrinsic polycrystalline silicon or amorphous silicon, the polycrystalline silicon is manufactured at high temperature, the deposition speed is high, and then phosphorus diffusion is performed; the amorphous silicon is prepared at low temperature, the deposition speed is slow, and then phosphorus diffusion is performed.
Illustratively, the annealing may be performed at a high temperature by PECVD. There are also reactive sputtering (PVD), electron beam evaporation and thermal decomposition of silane.
The glow discharge method (PECVD) is a method in which a reaction chamber is evacuated, hydrogen or silane diluted with argon is charged, and a radio frequency power supply is applied to two parallel plate electrodes 11 to ionize the silane and form plasma. An amorphous silicon film is deposited on the heated substrate. If the silane is admixed with a suitable amount of phosphane (pH) 3 ) Or diborane (B) 2 H 6 ) Thus obtaining the N-type or P-type amorphous silicon film.
If double sided silicon deposition is used, the silicon on the front side is removed in a subsequent silicon etch step, and if single sided silicon deposition is used, only a single sided etch of silicon is required.
S302, generating a first mask layer 5 outside the poly-Si (n) layer on the reverse side.
It is to be understood that the first mask layer 5 may be SiN x The function of the layer, the first mask layer 5, is to protect the poly-si (n) layer from corrosion.
S303, locally etching/corroding the first mask layer 5 to enable the part of the poly-Si (n) layer on the reverse side to be in an exposed state.
It will be appreciated that the etching/etching is effected with the first mask layer 5 located at a specific position opposite. The etching can be laser etching; the etching can be chemical etching, and the chemical etching agent is SiN capable of etching x And (3) a layer. The etching/etching method is matched with the first mask layer 5 to be in an exposed state in a local part of the poly-Si (n) layer, and the first doping layer can be etched due to the lack of the protection of the first mask layer 5 in the local area in the exposed state, so as to create conditions for constructing a blank area 6 in the middle of the reverse poly-Si (n) layer.
Regarding the choice of etching/etching area, the etching/etching area is used to create a blank area 6, the width of the blank area 6 is slightly larger than the width of the corresponding poly-Si (p) layer, so that the SiN on the opposite side is etched/etched at intervals x The area of the layer needs to be smaller than the SiN on the opposite side which is not etched/etched x A region of a layer.
S304, etching the exposed parts of the poly-Si (n) layers on the front and back sides, and generating a blank area 6 in the middle of the poly-Si (n) layer on the back side.
It will be appreciated that the chemical etchant used to etch silicon is selected to further etch the exposed portion of the poly-si (N) layer such that a void 6 is present between the opposing poly-si (N) layer, the width of the void 6 determining the width ratio between the P and N regions, as desired.
S305, removing the first passivation layer 3 with the front and back surfaces in an exposed state, and etching the phosphorus diffusion layer 2 corresponding to the blank area 6 to form a semi-finished product; the product state after the completion of the step refers to the attached figure 1 of the specification.
When the phosphorus diffusion layer 2 corresponding to the blank area 6 is removed, etching is carried out until the Si substrate 1 corresponding to the phosphorus diffusion layer 2 is exposed; by thoroughly removing the phosphorus diffusion layer 2 in the region of the second doped silicon layer 8 to be generated, the phosphorus diffusion layer 2 is prevented from being positioned between the Si substrate 1 and the poly-Si (P) layer, and the collection of holes in the P-type second doped silicon layer 8 is enhanced.
And S306, generating second passivation layers 7 on the front surface and the back surface of the semi-finished product.
When the first passivation layer 3 corresponding to the blank area 6 is removed, the first passivation layer 3 on the front surface is removed at the same time; on the other hand, and while the second passivation layer 7 is grown in the blank region 6, the second passivation layer 7 is simultaneously grown on the front surface, the first doped silicon layer 4.
The defect state of the surface of the Si substrate 1 is passivated by generating the second passivation layer 7 to repair the partial exposure of the obverse and reverse sides of the Si substrate 1 due to the thorough etching of the phosphorus diffusion layer 2. The generation manner of the second passivation layer 7 can be referred to the generation manner of the first passivation layer 3.
It should be particularly noted that the second passivation layer 7 on the opposite side may also serve as a separation layer, the outer side surface of the second passivation layer 7 is attached to and contacted with the Si substrate 1 and the first doped silicon layer 4, and the second doped silicon layer 8 is separated from the Si substrate 1 and the first doped silicon layer 4 by the second passivation layer 7, so as to separate the subsequently generated second doped silicon layer 8 in all directions, thereby avoiding the problem of electric leakage. Furthermore, two ends of the first passivation layer 3 are respectively contacted with the second passivation layer 7 outside the two adjacent sections of the second doped silicon layers 8 to coat the first doped silicon layer 4, so that electric leakage at the first doped silicon layer 4 is also avoided.
S4, a second doped silicon layer 8 is grown on the opposite second passivation layer 7, the second doped silicon layer 8 being in particular a poly-si (p) layer.
It should be noted that the steps S4 and S3 can be performed by transposition, i.e., a poly-Si (p) layer is formed, a blank region 6 of the poly-Si (p) layer is formed, and then a poly-Si (n) layer is formed on the blank region 6 of the poly-Si (p) layer.
S401, generating a poly-Si (p) layer on the outer surface of the front and back surfaces, and filling the poly-Si (p) layer in the blank area 6 of the poly-Si (n) layer.
Generating a second doped silicon layer 8 on the second passivation layer 7 on the front and back surfaces of the semi-finished cell, and filling the second doped silicon layer 8 in the blank area 6 between the first doped silicon layers 4; exemplary methods of forming poly-si (p) layers are referenced to methods of manufacturing poly-si (n) layers. In addition, the designed thickness of the poly-Si (p) layer is within
Preferably to the thickness of the poly-Si (n) layer, so that the first doping isThe doped silicon layers formed by the interleaving of the doped silicon layers 4 and the second doped silicon layers 8 have the same thickness.
S402, generating a second mask layer 9 outside the poly-Si (p) layer on the reverse side.
It is to be understood that the second mask layer 9 may be SiN x The second mask layer 9 serves to protect the poly-Si (p) layer from corrosion; the second mask layer 9 has a thickness of
In between.
S403, etching/corroding the second mask layer 9 locally to enable the part of the poly-Si (p) layer corresponding to the poly-Si (n) layer to be in an exposed state.
It is understood that the etching/etching is performed on the second mask layer 9 at a specific location opposite to the specific location where the poly-si (n) layer corresponds to a portion of the second mask layer 9 facing outward, such as a region of the second mask layer 9 corresponding to the poly-si (n) layer facing vertically downward. The etching can be laser etching; the etching can be chemical etching, and the chemical etching agent is SiN capable of etching x A layer. The etching/etching method is matched with the second mask layer 9 to expose a part of the poly-Si (p) layer, and the exposed part of the poly-Si (p) layer can be etched due to the lack of the protection of the second mask layer 9, so that a condition is created for exposing the poly-Si (p) layer.
Regarding the selection of the etching/etching region, the SiN layer on the reverse side is etched/etched based on the space of poly-Si (p) layer required for constructing PN junction x The zone size of the layer is adjusted.
S404, etching the exposed parts of the poly-Si (p) layer on the front surface and the back surface, and enabling the first mask layer 5 corresponding to the poly-Si (n) layer on the back surface to be in an exposed state.
If single-sided silicon deposition is used, only one side of the silicon needs to be etched.
It will be appreciated that the chemical etchant which etches silicon is selected to further etch the exposed portion of the poly-si (P) layer to remove the excess P-doped silicon layer so that the first mask layer 5 opposite the poly-si (n) layer is exposed in preparation for forming the electrode 11 for the poly-si (n) layer. The etched area size is only required to satisfy the requirement that the poly-Si (n) layer can be sintered into the electrode 11.
It should be noted that, in addition to the construction of the doped silicon layer by using the masking and etching methods in S3 and S4, if the requirement of mass production is not considered, ion implantation is performed by using an ion implanter, and after the intrinsic silicon is deposited, ion implantation in a specific region is achieved; specifically, phosphorus implantation is carried out at the position where a poly-Si (n) layer needs to be formed on the reverse side, boron implantation is carried out at the position where a poly-Si (p) layer needs to be formed, and mask patterns of the phosphorus implantation and the boron implantation are arranged alternately. It should be noted that the ion implanter is expensive and the ion implantation causes lattice damage and requires an annealing process.
Due to the design of the mask-etching scheme, the reverse poly-Si (p) layer is deposited along the poly-Si (n) layer and the blank area 6, so that the poly-Si (p) layer has an excessive section growing along the end faces of the first doped silicon layer 4 and the first mask layer 5; the elimination of the redundant segment can be achieved by further enlarging the area for etching/corroding the second mask layer 9 after the second mask layer 9 is generated, specifically, etching/corroding the area of the second mask layer 9 corresponding to the redundant segment on the second doped silicon layer 8, so as to ensure that when the second doped silicon layer 8 is corroded, the redundant segment of the second doped silicon layer 8 is corroded by increasing the corrosion time, thereby achieving the purpose that the first doped silicon layer 4 and the second doped silicon layer 8 are flush, reducing the total thickness of the finished battery, and reducing the total thickness of the finished battery
Similarly, if the excess portion of the second doped silicon layer 8 is preserved, advantages include: firstly, the production time is shortened, and the consumption of corrosive agents is saved; the bearing capacity of the battery with increased thickness is increased; and thirdly, when the redundant section of the second doped silicon layer 8 is prevented from being corroded, the corrosive agent corrodes the area of the second doped silicon layer 8, which needs to be contacted with the first doped silicon layer 4, so that the stable butt joint of the first doped silicon layer 4 and the second doped silicon layer 8 is ensured, the overall conversion efficiency of the battery is ensured, and further, the preparation method is more suitable for large-scale mass production products, and the product quality is ensured.
S5, an anti-reflection layer 10 is generated outside the second passivation layer 7 of the front side.
It is understood that SiN may also be used for the antireflective layer 10 herein x A layer to reduce reflection of incident light. The thickness of the antireflection layer 10 is within
In the meantime.
S6, forming an electrode 11 on the opposite poly-Si (n) layer and poly-Si (p) layer.
As for the manufacture of the electrode 11, a metal paste may be printed and sintered at high temperature; the electrode 11 may be a silver electrode 11 or an aluminum electrode 11. Specifically, the metal atoms in the electrode 11 can diffuse into the first doped silicon layer 4 and the second doped silicon layer 8 during the high temperature sintering process. The electrodes 11 located in the poly-Si (n) layer and the poly-Si (p) layer do not overlap each other.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A P-type silicon back contact cell, comprising:
the substrate comprises a Si substrate, a P-type Si substrate and a Si substrate, wherein the Si substrate is a P-type Si substrate; a plurality of sections of phosphorus diffusion layers are arranged on the reverse side of the Si substrate at intervals, and a blank area is reserved between the phosphorus diffusion layers of the adjacent sections;
the first doped silicon layer is provided with a plurality of sections, and the plurality of sections of the first doped silicon layer are arranged on the plurality of sections of the phosphorus diffusion layers one by one; the phosphorus diffusion layer above the first doped silicon layer and the Si substrate form a PN junction;
the second doped silicon layer is provided with a plurality of sections, and the plurality of sections of the second doped silicon layer are arranged in the plurality of blank areas; and
the electrodes are arranged and are respectively and electrically connected to the first doped silicon layer and the second doped silicon layer.
2. The method according to claim 1, wherein a second passivation layer is disposed around the second doped silicon layer, and an outer side surface of the second passivation layer is in contact with the Si substrate and the first doped silicon layer, and the second doped silicon layer is separated from the Si substrate and the first doped silicon layer by the second passivation layer.
3. The method according to claim 2, wherein a first passivation layer is disposed between the phosphorus diffusion layer and the first doped silicon layer, and both ends of the first passivation layer are respectively in contact with the second passivation layers outside the two adjacent sections of the second doped silicon layers to cover the first doped silicon layer.
4. The method of claim 1, wherein the width of each segment of the phosphorus diffusion layer is greater than the width of the void region, and the width of the first doped silicon layer is greater than the width of the second doped silicon layer.
5. A preparation method of a P-type silicon back contact battery is characterized by comprising the following steps:
carrying out base material treatment on the Si substrate; the base material treatment of the Si substrate specifically includes:
cleaning and texturing a Si substrate;
carrying out phosphorus diffusion on the reverse side of the Si substrate to form a phosphorus diffusion layer;
generating first passivation layers on the front side and the back side of the Si substrate;
forming a first doped silicon layer on the opposite first passivation layer;
forming a second doped silicon layer on the opposite second passivation layer;
generating an antireflection layer outside the second passivation layer on the front surface;
forming electrodes on the first doped silicon layer and the second doped silicon layer on the opposite sides;
and further, the first passivation layer and the phosphorus diffusion layer corresponding to the blank area are sequentially removed, and a second passivation layer and a second doped silicon layer are sequentially generated in the blank area.
6. The method of claim 5, wherein the first doped silicon layer or the second doped silicon layer is formed by: in-situ doped silicon deposition; or a method of depositing intrinsic silicon first, and then doping source diffusion or ion implantation.
7. The method of claim 5, wherein the specific step of removing the first doped silicon layer to form the plurality of empty regions at the specific intervals comprises:
generating a first mask layer outside the first doped silicon layer on the reverse side, so that the first doped silicon layer is covered by the first mask layer;
etching/corroding the first mask layer locally to enable the part of the first doped silicon layer on the reverse side to be in an exposed state;
etching the exposed portions of the first doped silicon layers on the front and back surfaces, and forming a blank region in the middle of the first doped silicon layer on the back surface.
8. The method of claim 5, wherein a second passivation layer is formed between the first doped silicon layer and the second doped silicon layer to separate the first doped silicon layer from the second doped silicon layer, and wherein the phosphorus diffusion layer over the first doped silicon layer and the Si substrate form a PN junction.
9. The manufacturing method according to claim 5, wherein when the first passivation layer corresponding to the blank region is removed, the first passivation layer on the front surface is removed at the same time; and simultaneously generating a second passivation layer on the front surface and the first doped silicon layer when the second passivation layer is generated in the blank area.
10. The method of claim 5, wherein the etching is performed until the Si substrate corresponding to the phosphorus diffusion layer is exposed when the phosphorus diffusion layer corresponding to the blank region is removed.
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