CN114597288A - Preparation method of back contact type double-sided battery - Google Patents

Preparation method of back contact type double-sided battery Download PDF

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CN114597288A
CN114597288A CN202210328416.0A CN202210328416A CN114597288A CN 114597288 A CN114597288 A CN 114597288A CN 202210328416 A CN202210328416 A CN 202210328416A CN 114597288 A CN114597288 A CN 114597288A
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曹建伟
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Zhejiang Qiushi Semiconductor Equipment Co Ltd
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Abstract

The embodiment of the invention provides a preparation method of a back contact type double-sided battery, belonging to the technical field of silicon wafer battery preparation, and the preparation method comprises the following steps: cleaning and texturing a Si substrate; generating passivation layers on the front surface and the back surface of the cleaned and textured Si substrate; generating a first doped layer on the passivation layer on the reverse side of the Si substrate; generating a second doped layer on the passivation layer on the reverse side of the Si substrate; generating an antireflection layer outside the passivation layer on the front surface; forming electrodes on the first doping layer and the second doping layer on the opposite sides; the technical effect of preparing the P-type back contact type double-sided battery is achieved.

Description

Preparation method of back contact type double-sided battery
Technical Field
The invention relates to the technical field of silicon wafer battery preparation, in particular to a preparation method of a back contact type double-sided battery.
Background
Solar cells are increasingly used as a new energy alternative. A solar cell is a device that converts solar energy into electrical energy. The solar cell generates current carriers by utilizing a photovoltaic principle, and then the current carriers are led out by using the electrodes, so that the electric energy is effectively utilized. Based on the distribution mode of the electrodes, the electrodes are divided into a double-sided electrode and a reverse-sided electrode; wherein the cells of the opposite electrode are also referred to as back contact cells.
At present, a solar cell mainly comprises a P-type silicon wafer, and electrodes arranged on the front side and the back side are mainly used; particularly, when the back contact battery is used, an N-type silicon wafer is generally selected, but the cost for preparing the N-type silicon wafer is higher than that of a P-type silicon wafer. If a back contact type double-sided battery can be manufactured by using a P-type silicon wafer, the cost is remarkably reduced.
Therefore, the prior art problems are: how to prepare a back contact type double-sided battery by utilizing a P-type silicon wafer.
Disclosure of Invention
The embodiment of the application provides a method for preparing a back contact type double-sided battery, which solves the technical problem of how to prepare the back contact type double-sided battery by using a P-type silicon wafer in the prior art; the technical effect of preparing the P-type back contact type double-sided battery is achieved.
The embodiment of the application provides a preparation method of a back contact type double-sided battery, which comprises the following steps: cleaning and texturing a Si substrate; generating passivation layers on the front side and the back side of the cleaned and textured Si substrate; generating a first doped layer on the passivation layer on the reverse side of the Si substrate; generating a second doped layer on the passivation layer on the reverse side of the Si substrate; generating an antireflection layer outside the passivation layer on the front surface; electrodes are formed on the opposite first and second doped layers.
Preferably, the specific method for generating the first doped layer or the second doped layer is as follows: in-situ doping; or a method of depositing intrinsic silicon first and then doping source diffusion or ion implantation.
Preferably, the first doping layer is generated on the passivation layer on the reverse side of the Si substrate and is provided with blank areas, and the blank areas are arranged at intervals relative to the first doping layer; and the second doped layer is generated in the blank region.
Preferably, the method of forming the blank region includes: generating a first mask layer outside the first doped layer on the reverse side of the Si substrate, so that the first doped layer is covered by the first mask layer; etching/corroding the first mask layer locally to enable the part of the first doping layer on the reverse side to be in an exposed state; and etching the exposed parts of the first doping layers on the front and back surfaces, and generating a blank area in the middle of the first doping layer on the back surface.
Preferably, the blank region exposes the passivation layer on the reverse side of the Si substrate to the outside, so that the second doped layer grows on the passivation layer in a fitting manner.
Preferably, the first doped layer and the second doped layer are in contact with each other, and a PN junction is formed on the Si substrate.
Preferably, the specific method for generating the second doped layer on the passivation layer on the opposite side of the Si substrate comprises the following steps: and generating a second doped layer on the passivation layer on the front side and the back side of the Si substrate: filling the blank area of the first doped layer with the second doped layer; generating a second mask layer outside the second doped layer on the reverse side; performing local etching/corrosion on the second mask layer to enable the part of the second doped layer corresponding to the first doped layer to be in an exposed state; and corroding the exposed parts of the second doping layers on the front and back surfaces, and enabling the first mask layer corresponding to the first doping layer on the back surface to be in an exposed state.
Preferably, the first doped layer and the second doped layer have a thickness of
Figure BDA0003572279580000021
Preferably, the Si substrate is doped with gallium, and the doping concentration of the gallium is less than 7.5x1015 cm-3; and the resistivity of the substrate layer is greater than 1.8 omega cm.
Preferably, the first mask layer, the second mask layer and the anti-reflection layer may be made of the same material.
Preferably, when the first doped layer is a poly-Si (N) layer (N-type polysilicon), the second doped layer is a poly-Si (P) layer (P-type polysilicon); or, when the first doped layer is a poly-Si (p) layer, the second doped layer is a poly-Si (n) layer.
One or more technical solutions in the embodiments of the present application at least have one or more of the following technical effects:
1. in the embodiment of the application, the back contact battery generally adopts an N-type silicon wafer, but the cost for preparing the N-type silicon wafer is higher than that of a P-type silicon wafer; if the back contact type double-sided battery can be manufactured by using the P-type silicon wafer, the cost is obviously reduced; the scheme of the application can be used for producing the back contact battery based on the P-type silicon wafer; the technical problem of how to prepare a back contact type double-sided battery by using a P-type silicon wafer in the prior art is solved; the technical effect of preparing the P-type back contact type double-sided battery is achieved.
Drawings
Fig. 1 is a flowchart illustrating a method for manufacturing a back contact type double-sided battery according to an embodiment of the present disclosure;
fig. 2 is a flow chart illustrating a method for manufacturing a back-contact double-sided battery according to another embodiment of the present disclosure;
FIG. 3 is a flow chart of a specific preparation of the preparation process of FIG. 1;
FIG. 4 is a schematic structural diagram after step S304 in FIG. 3;
fig. 5 is a schematic structural diagram after step S6 in fig. 3.
Reference numerals: 1. a Si substrate; 2. a passivation layer; 3. a first doped layer; 31. a blank area; 4. a first mask layer; 5. a second doped layer; 6. a second mask layer; 7. an anti-reflective layer; 8. and an electrode.
Detailed Description
The ordinal numbers used herein for the components, such as "first," "second," etc., are used merely to distinguish between the objects described, and do not have any sequential or technical meaning. In the present application, the steps/methods in the front-back sequence are not defined, and it should be understood that there is no specific sequence, and the sequence can be reversed; the term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like are used in the orientations and positional relationships indicated in the drawings, which are based on the orientations and positional relationships indicated in the drawings, and are used for convenience of description and simplicity of description, but do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.
A method for preparing a back contact type double-sided battery takes a first doping layer 3 as a poly-Si (n) layer and a second doping layer 5 as a poly-Si (p) layer as an example, and refers to the attached figures 1-3 of the specification, and comprises the following steps:
s1, cleaning the Si substrate 1 and making wool.
It is understood that the Si substrate 1 may be cleaned by ultrasonic cleaning, RCA cleaning, or heating, boiling, or rinsing; texturing the front surface and the back surface of the Si substrate 1 after cleaning to form textured surfaces on the upper surface and the lower surface; the textured structures obtained by specific texturing may be in a wavy, pyramidal or inverted pyramidal pattern to increase surface area while reducing reflection of incident light.
Regarding the specific description of the Si substrate 1, in order to ensure minority carrier lifetime and preferably improve the material integrity of the Si substrate 1, the Si substrate 1 may specifically be a P-type silicon wafer, the substrate layer 3 is doped with gallium, and the doping concentration of gallium is less than 7.5x1015cm-3The resistivity of the substrate layer 3 is more than 1.8 omega cm; further, the doping concentration of gallium is less than 7.1x1015cm-3The resistivity of the substrate layer 3 is more than 2.0 omega cm; furthermore, the doping concentration of gallium is less than 4.6x1015cm-3The substrate layer 3 has a resistivity of more than 3.0 Ω. Of course, the Si substrate 1 may also be an N-type silicon wafer, doped with phosphorus.
S2, passivation layers 2 are formed on both front and back surfaces of the Si substrate 1.
It is understood that the purpose of generating the passivation layers 2 on both the front and back sides of the Si substrate 1 is to passivate a defect state of the surface, such as dangling bonds of the surface; preferably, the thickness < > of the passivation layer 2
Figure BDA0003572279580000051
It should be noted that the passivation layer 2 can be formed in various ways, such as by PECVD or LPCVD deposition; PECVD oxidation methods may also be employed. Thermal oxidation is generally used, and oxygen diffuses into the substrate to form silicon oxide, so that the passivation effect is good.
Illustratively, the passivation layer 2 may be made of silicon nitride, silicon oxide, silicon oxynitride or a composite of two or more of the above materials; in case the passivation layer 2 is matched with the doped layer, the passivation layer 2 may adopt a scheme of silicon oxide + aluminum oxide.
S3, a poly-si (n) layer is formed on the passivation layer 2 on the opposite side.
It will be appreciated that the construction of a poly-Si (n) layer with blank 31 is an important step in the fabrication of a bifacial cell, and that the subsequent design is such that blank 31 creates a poly-Si (p) layer, which is then used to construct PN junctions on Si substrates.
S301, generating poly-Si (n) layer outside the passivation layer 2.
It will be appreciated that the thickness of the poly-Si (n) layer in the design is
Figure BDA0003572279580000052
The poly-Si (n) layer can be formed in two ways:
adopting an LPCVD or PECVD in-situ doping method, adding silane and a doping source (phosphorus), wherein the concentration of phosphine in reaction gas is about 1-2%, so that amorphous silicon layers are formed on the front surface and the back surface, and then annealing the amorphous silicon to form polycrystalline silicon;
method for depositing intrinsic silicon by LPCVD or PECVD, followed by a phosphorus diffusion process (POCl)3) Or ion implantation (but the equipment is expensive, the processing is time-consuming, and the mass production is not suitable); and annealing at high temperature to obtain polycrystalline silicon.
In addition, the LPCVD method is used for manufacturing intrinsic polycrystalline silicon or amorphous silicon, the polycrystalline silicon is manufactured at high temperature, the deposition speed is high, and then phosphorus diffusion is performed; the amorphous silicon is prepared at low temperature, the deposition speed is slow, and then phosphorus diffusion is performed.
Illustratively, the annealing may be performed at a high temperature by PECVD. There are also reactive sputtering (PVD), electron beam evaporation and thermal decomposition of silanes.
The glow discharge method (PECVD) is to vacuumize a reaction chamber, fill hydrogen or silane diluted by argon, and add a radio frequency power supply on two parallel plate electrodes to ionize the silane and form plasma. An amorphous silicon film is deposited on the heated substrate. When silane is doped with an appropriate amount of phosphane (PH3) or diborane (B2H6), an N-type or P-type amorphous silicon film can be obtained.
S302, generating a first mask layer 4 outside the poly-Si (n) layer on the reverse side.
It will be appreciated that the first mask layer 4 may be SiNxThe function of the layer, the first mask layer 4, is to protect the poly-si (n) layer from corrosion.
S303, the first mask layer 4 is locally etched/corroded, so that the poly-Si (n) layer on the reverse side is locally exposed.
It will be appreciated that the etching/etching is effected with the first mask layer 4 located at a specific position opposite. The etching can be laser etching; the etching can be chemical etching, and the chemical etching is selected from etchable SiNxAnd (3) a layer. The etching/etching method is matched with the first mask layer 4 to expose a part of the poly-Si (n) layer, and the exposed part can be etched due to the lack of the protection of the first mask layer 4, so as to create conditions for constructing a blank area 31 in the middle of the reverse poly-Si (n) layer.
Regarding the selection of the etching/etching region, the SiN layer on the reverse side is etched/etched based on the space of poly-Si (p) layer required for constructing PN junctionxThe zone size of the layer is adjusted.
S304, etching the exposed parts of the poly-Si (n) layers on the front and back sides, and generating a blank area 31 in the middle of the poly-Si (n) layer on the back side.
It will be appreciated that the chemical etchant which etches silicon is selected to further etch the exposed portion of the poly-si (N) layer such that a void 31 is present between the opposing poly-si (N) layer, the width of the void 31 determining the width ratio between the P and N regions; so as to achieve the effect of forming a poly-Si (n) layer having a margin 31 on the passivation layer 2 on the opposite side of the Si substrate 1. The product state after this step is completed refers to the attached figure 4 of the specification.
S4, a poly-si (p) layer is formed on the passivation layer 2 on the opposite side.
It should be noted that the steps S4 and S3 can be performed by transposition, that is, a poly-Si (p) layer is formed, a blank region 31 of the poly-Si (p) layer is formed, and then a poly-Si (n) layer is formed on the blank region 31 of the poly-Si (p) layer.
S401, generating a poly-Si (p) layer on the outer surface of the front and back surfaces, and filling the poly-Si (p) layer in the blank area 31 of the poly-Si (n) layer.
Namely, a second doping layer 5 is generated on the passivation layer 2 on the front and back sides of the Si substrate 1, and the second doping layer 5 is filled in the blank area 31 of the first doping layer 3; exemplary methods of forming poly-si (p) layers are described with reference to methods of forming poly-si (n) layers. In addition, the designed thickness of the poly-Si (p) layer is within
Figure BDA0003572279580000071
Preferably, the thickness of the poly-si (n) layer is made uniform, so that the thickness of the alternately formed doped layers of the first doped layer 3 and the second doped layer 5 is made uniform.
S402, generating a second mask layer 6 outside the poly-Si (p) layer on the reverse side.
It is to be understood that the second mask layer 6 may be SiNxThe second mask layer 6 serves to protect the poly-Si (p) layer from corrosion; the second mask layer 6 has a thickness of
Figure BDA0003572279580000081
In the meantime.
S403, etching/corroding the second mask layer 6 locally to enable the part of the poly-Si (p) layer corresponding to the poly-Si (n) layer to be in an exposed state.
It is understood that the etching/etching is performed on the second mask layer 6 at a specific location opposite to the specific location where the poly-si (n) layer corresponds to a portion of the second mask layer 6 facing outward, such as a region of the second mask layer 6 corresponding to the poly-si (n) layer facing vertically downward. The etching can be laser etching; the etching can be chemical etching, and the chemical etching is selected from etchable SiNxAnd (3) a layer. The etching/etching method is combined with the second mask layer 6 to expose a part of the poly-Si (p) layerThe exposed local area, which lacks the protection of the second mask layer 6, can be etched to allow for the exposure of the poly-si (p) layer.
Regarding the selection of the etching/etching area, the SiN on the opposite side is etched/etched based on the space of the poly-Si (p) layer required for the PN junctionxThe zone size of the layer is adjusted.
S404, etching the exposed parts of the poly-Si (p) layer on the front surface and the back surface, and enabling the first mask layer 4 corresponding to the poly-Si (n) layer on the back surface to be in an exposed state.
It will be appreciated that the chemical etchant which etches silicon is selected to further etch the exposed portion of the poly-si (P) layer to remove the excess P-type doped layer so that the first mask layer 4 opposite the poly-si (n) layer is exposed in preparation for forming the electrode 8 for the poly-si (n) layer. The etched area size only needs to be sufficient to sinter the poly-si (n) layer into the electrode 8.
Particularly, S3 and S4 are configured by using a masking and etching method to form the doped layer, and besides, if the requirement of mass production is not considered, an ion implanter is used to perform ion implantation to implement ion implantation in a specific region after the intrinsic silicon deposition; specifically, phosphorus implantation is carried out at the position where a poly-Si (n) layer needs to be formed on the reverse side, boron implantation is carried out at the position where a poly-Si (p) layer needs to be formed, and mask patterns of the phosphorus implantation and the boron implantation are arranged alternately. It should be noted that the ion implanter is expensive and the ion implantation causes lattice damage and requires an annealing process.
Due to the design of the mask-etching scheme, the poly-Si (p) layer on the reverse side is a layer deposited along the poly-Si (n) layer and the blank area 31, so that an excessive section growing along the end faces of the first doping layer 3 and the first mask layer 4 exists in the poly-Si (p) layer; the elimination of the redundant segment can select to further enlarge the area of the etched/corroded second mask layer 6 after the second mask layer 6 is generated, specifically, the area of the second mask layer 6 corresponding to the redundant segment on the second doped layer 5 is etched/corroded, so that when the second doped layer 5 is corroded, the redundant segment of the second doped layer 5 is corroded by increasing the corrosion time, and the redundant segment can be generatedThe purpose of leveling the first doping layer 3 and the second doping layer 5 is achieved, the overall thickness of the finished battery is reduced, and the reduction of the thickness of the finished battery is realized
Figure BDA0003572279580000091
Similarly, if the redundant segment of the second doped layer 5 is preserved, the advantages include: firstly, the production time is shortened, and the consumption of corrosive agents is saved; the bearing capacity of the battery with increased thickness is increased; and thirdly, when the redundant section of the second doping layer 5 is prevented from being corroded, the corrosive agent corrodes the area of the second doping layer 5, which is required to be contacted with the first doping layer 3, so that the stable butt joint of the first doping layer 3 and the second doping layer 5 is ensured, the overall conversion efficiency of the battery is ensured, and further, the preparation method described in the application is more suitable for products in large-scale mass production, and the product quality is ensured.
S5, an anti-reflection layer 7 is generated outside the passivation layer 2 of the front side.
It is understood that SiN may also be used for the antireflective layer 7 herexA layer to reduce reflection of incident light. The thickness of the antireflection layer 7 is within
Figure BDA0003572279580000092
In the meantime.
S6, forming electrodes 8 on the opposite poly-Si (n) and poly-Si (p) layers.
As for the manufacture of the electrode 8, a metal paste may be printed and sintered at high temperature; the electrode 8 may be a silver electrode 8 or an aluminum electrode 8. Specifically, the metal atoms in the electrode 8 can diffuse into the doped layer during the high temperature sintering process. The electrodes 8 are provided with electrodes 8 with respect to the poly-Si (n) layer and the poly-Si (p) layer, respectively, which do not overlap.
Regarding the preparation method, referring to the attached figure 2 of the specification, the doping type of the Si substrate 1 is changed into an N-type Si substrate 1; and the order of generating a poly-Si (n) layer and a poly-Si (p) layer is changed, the poly-Si (p) layer is generated firstly, then the poly-Si (n) layer is generated on the basis of the poly-Si (p) layer, and finally the electrode 8 is added in a sintering way. The product state after this step is completed refers to the specification and the attached figure 5.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A method of making a back-contact bifacial battery, the method comprising:
cleaning and texturing a Si substrate;
generating passivation layers on the front side and the back side of the cleaned and textured Si substrate;
generating a first doped layer on the passivation layer on the reverse side of the Si substrate;
generating a second doped layer on the passivation layer on the reverse side of the Si substrate;
generating an antireflection layer outside the passivation layer on the front surface;
electrodes are formed on the opposite first and second doped layers.
2. The method according to claim 1, wherein the specific method for forming the first doped layer or the second doped layer is: in-situ doping; or a method of depositing intrinsic silicon first, and then doping source diffusion or ion implantation.
3. The method according to claim 1, wherein the first doped layer is formed on the passivation layer on the opposite side of the Si substrate to have a plurality of blank regions spaced apart from the first doped layer; and the second doped layer is generated in the blank region.
4. The manufacturing method according to claim 3, wherein the blank region is formed by:
generating a first mask layer outside the first doping layer on the reverse side of the Si substrate, so that the first doping layer is covered by the first mask layer;
etching/corroding the first mask layer locally to enable the part of the first doping layer on the reverse side to be in an exposed state;
and etching the exposed parts of the first doping layers on the front and back surfaces, and generating a blank area in the middle of the first doping layer on the back surface.
5. The method according to claim 4, wherein the blank region exposes the passivation layer on the opposite side of the Si substrate to the outside, so that the second doped layer is grown on the passivation layer in a fitting manner.
6. The method of claim 1, wherein the first doped layer and the second doped layer are in contact and form a PN junction on the Si substrate.
7. The method of claim 3, wherein the step of forming the second doped layer on the passivation layer opposite the Si substrate comprises:
and generating a second doped layer on the passivation layer on the front side and the back side of the Si substrate: filling the blank area of the first doped layer with the second doped layer;
generating a second mask layer outside the second doped layer on the reverse side;
performing local etching/corrosion on the second mask layer to enable the part of the second doped layer corresponding to the first doped layer to be in an exposed state;
and corroding the exposed parts of the second doping layers on the front and back surfaces, and enabling the first mask layer corresponding to the first doping layer on the back surface to be in an exposed state.
8. The method of claim 1, wherein the first and second doped layers are at a thickness of
Figure FDA0003572279570000021
9. The method according to claim 1, wherein the Si substrate is doped with gallium, and a doping concentration of gallium is less than 7.5x1015cm-3(ii) a And the resistivity of the substrate layer is greater than 1.8 omega cm.
10. The method of any one of claims 1-9, wherein when the first doped layer is a poly-si (n) layer, the second doped layer is a poly-si (p) layer; or, when the first doped layer is a poly-Si (p) layer, the second doped layer is a poly-Si (n) layer.
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