CN105742391A - Tunnel silicon oxide passivated contact solar cell and preparation method thereof - Google Patents
Tunnel silicon oxide passivated contact solar cell and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 331
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 331
- 239000010703 silicon Substances 0.000 claims abstract description 331
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 122
- 238000000034 method Methods 0.000 claims abstract description 99
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- 238000003475 lamination Methods 0.000 claims abstract description 84
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 67
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- 238000002161 passivation Methods 0.000 claims description 92
- 238000005229 chemical vapour deposition Methods 0.000 claims description 40
- 239000007789 gas Substances 0.000 claims description 35
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- 239000010409 thin film Substances 0.000 abstract description 19
- 230000004888 barrier function Effects 0.000 abstract description 4
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- 230000005641 tunneling Effects 0.000 description 22
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- 238000006243 chemical reaction Methods 0.000 description 17
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- -1 nitrogen hydrogen Chemical class 0.000 description 11
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- 229910052796 boron Inorganic materials 0.000 description 10
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 9
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- 239000012528 membrane Substances 0.000 description 9
- 229910017604 nitric acid Inorganic materials 0.000 description 9
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- 239000002184 metal Substances 0.000 description 8
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
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- 238000005259 measurement Methods 0.000 description 2
- 229910052756 noble gas Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
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- 229910015845 BBr3 Inorganic materials 0.000 description 1
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- 230000009286 beneficial effect Effects 0.000 description 1
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- 229910052810 boron oxide Inorganic materials 0.000 description 1
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Substances BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 description 1
- 238000006388 chemical passivation reaction Methods 0.000 description 1
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- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/048—Encapsulation of modules
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/048—Encapsulation of modules
- H01L31/0481—Encapsulation of modules characterised by the composition of the encapsulation material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
The invention provides a solar cell. The solar cell comprises a silicon wafer, a passivated tunnel layer and a doping thin film silicon layer, wherein passivated tunnel layer is arranged between the silicon wafer and the doping thin film silicon layer, the passivated tunnel layer is one of a silicon oxide/silicon oxynitride gradient lamination layer, a silicon oxynitride/silicon nitride gradient lamination layer and a silicon oxide/silicon oxynitride/silicon nitride gradient lamination layer, the silicon oxynitride is nitrogen doping silicon oxide or oxygen doping silicon nitride, and the nitrogen concentration of the silicon oxide/silicon oxynitride gradient lamination layer, the silicon oxynitride/silicon nitride gradient lamination layer and the silicon oxide/silicon oxynitride/silicon nitride gradient lamination layer is gradiently reduced from a part far away from a silicon wafer side to the silicon wafer side. Since the tunnel barriers of silicon nitride and silicon oxynitride are relatively low, the thickness of the passivated tunnel layer can be appropriately widened on the premise of ensuring the tunnel efficiency, thus, the holes of the passivated tunnel layer are favorably reduced, the generation and combination rate of current leakage are reduced, the process window is expanded, and the process stability is improved.
Description
Technical field
The present invention relates to area of solar cell, particularly relate to a kind of tunnelling silica nitrogen layer passivation contact solar cell and preparation method thereof.
Background technology
Tunnel oxide passivation contact (TunnelOxidePassivatedContact, TOPCon) solaode is a kind of novel silicon solaode proposed by Germany's Forlan Hough solar energy research in recent years.Battery adopts n-type silicon chip, and silicon chip back side covers the silicon oxide layer of below lid layer 2nm as passivation tunnel layer, then covers lid layer doping film silicon layer again, makes the passivating back of battery.The basic battery structure of tunnel oxide passivation contact solar cell is shown in Figure 1, and the structure of solaode is followed successively by n-type silicon chip, passivation tunnel layer (silicon oxide layer), doping n-type thin film silicon layer, metal electrode layer.When battery operated, electronics is tunneled through passivation tunnel layer from n-type silicon chip and enters doping n-type thin film silicon layer.Additionally, this institute also disclosed double-edged design, adopt p-type floating region silicon chip (FloatZoneSilicon, FZ), both sides direct growth silicon oxide layer, deposit the membrane silicon layer of doping afterwards respectively.
At present, tunnel oxide passivation contact solar cell all adopts silicon oxide (SiOx, x≤2) and as passivation tunnel layer.Silicon oxide is generally of good interface passivation effect, is conducive to significantly reducing the recombination velocity of whole silicon chip back surface.But, silicon oxide layer is as passivation tunnel layer Shortcomings part also, energy gap relatively big (about 8.9eV) due to silicon oxide, electronics and hole transport potential barrier are bigger, it is unfavorable for the transmission in electronics or hole, after the silicon oxide layer thickness as tunnel oxide is more than 2nm, its tunneling efficiency begins to be remarkably decreased, affect fill factor, curve factor, in order to enable electronics to be tunneled through the silicon oxide layer as passivation tunnel layer, need to be made silicon oxide layer very thin, it is normally controlled in below 2nm, thus in preparation process, easily form hole, thus causing that leakage current increases, and in subsequent high temperature annealing process, the atoms such as the phosphorus in doping film silicon layer readily diffuse in the silicon oxide layer as passivation tunnel layer, destroy the integrity as the silicon oxide layer being passivated tunnel layer, cause leakage current and compound aggravation；Additionally very thin silicon oxide layer defect level density is relatively low, with positive charge density relatively low, the field passivation effect of silicon chip is weakened.
Summary of the invention
Based on this, it is an object of the invention to,, cracky thin as the passivation thickness that causes greatly due to energy gap of tunnel layer for silicon oxide layer, it is easily caused the technical problem that leakage current, compound aggravation and passivation effect weaken, it is provided that a kind of tunnelling silica nitrogen layer passivation contact solar cell and preparation method thereof.
The invention provides a kind of tunnelling silica nitrogen layer passivation contact solar cell, wherein, described solaode includes silicon chip, passivation tunnel layer, doping film silicon layer, described passivation tunnel layer is between described silicon chip and described doping film silicon layer, and wherein said passivation tunnel layer is the one in silicon oxide/silicon oxynitride gradient lamination, silicon oxynitride/silicon nitride gradient lamination, silicon oxide/silicon oxynitride/silicon nitride gradient lamination；Described silicon oxynitride is the silicon nitride of the doping silicon oxide of nitrogen or doped with oxygen；The nitrogen concentration of described silicon oxide/silicon oxynitride gradient lamination, silicon oxynitride/silicon nitride gradient lamination, silicon oxide/silicon oxynitride/silicon nitride gradient lamination reduces from the side away from silicon chip to the side gradient of adjacent silicon wafer.
Wherein in an embodiment, the thickness of described passivation tunnel layer is 0.5～5nm.
Wherein in an embodiment, in described passivation tunnel layer, the diffusion depth of nitrogen is 0.1～5nm.
Wherein in an embodiment, described silicon oxide/silicon oxynitride gradient lamination is not less than 20at.% away from the atomic concentration of nitrogen in the side 0.2nm depth bounds of described silicon chip, and in the side 0.2nm depth bounds of the contiguous described silicon chip of described silicon oxide/silicon oxynitride gradient lamination, the atomic concentration of nitrogen is not higher than 5at.%.
Wherein in an embodiment, described silicon oxynitride/silicon nitride gradient lamination is 30～57.1at.% away from the atomic concentration of nitrogen in the side 0.2nm depth bounds of described silicon chip, in the side 0.2nm depth bounds of the contiguous described silicon chip of described silicon oxynitride/silicon nitride gradient lamination, the atomic concentration of nitrogen is 5～30at.%, and the atomic concentration of oxygen is 10～40at.%.
Wherein in an embodiment, described silicon oxide/silicon oxynitride/silicon nitride gradient lamination is 30～57.1at.% away from the atomic concentration of nitrogen in the side 0.2nm depth bounds of described silicon chip, and in the side 0.2nm depth bounds of the contiguous described silicon chip of described silicon oxide/silicon oxynitride/silicon nitride gradient lamination, the atomic concentration of nitrogen is not higher than 5at.%.
The preparation method that present invention also offers a kind of tunnelling silica nitrogen layer passivation contact solar cell, described solaode includes silicon chip, passivation tunnel layer, doping film silicon layer, described passivation tunnel layer is between described silicon chip and described doping film silicon layer, the preparation method of wherein said passivation tunnel layer comprises the following steps: generate silicon oxide layer at described silicon chip surface, then at described silicon oxide layer Surface Creation silicon oxynitride layer or silicon nitride layer, it is annealed the product obtained afterwards processing；Or generate silicon oxynitride layer at described silicon chip surface, then at described silicon oxynitride Surface Creation silicon nitride layer, be annealed the product obtained afterwards processing；Or generate silicon oxide layer at described silicon chip surface, then at described silicon oxide layer Surface Creation silicon oxynitride layer, then at described silicon oxynitride layer Surface Creation silicon nitride layer, be annealed the product obtained afterwards processing.
In one embodiment of the invention, described at described silicon chip surface generation silicon oxide layer, at described silicon oxide layer Surface Creation silicon oxynitride layer or silicon nitride layer, silicon oxynitride layer is generated at described silicon chip surface, preparation method at described silicon oxynitride Surface Creation silicon nitride layer includes ald and prepares method, chemical vapour deposition technique, reactive sputtering, direct nitridation method, ionic-implantation, described chemical vapour deposition technique includes plasma reinforced chemical vapour deposition method, microwave plasma strengthens chemical vapour deposition (CVD), radio frequency plasma strengthens method, heated filament plasma gas phase deposition, Low Pressure Chemical Vapor Deposition, middle pressure chemical vapor deposition method, radio frequency glow discharge plasma reinforced chemical vapour deposition method, inductively coupled plasma strengthens chemical vapour deposition technique, photo chemical vapor deposition method, thermal chemical vapor deposition method.
In one embodiment of the invention, the reacting gas of described chemical vapour deposition technique includes SiH4、N2、NH3、N2O、O2In one or more.
In one embodiment of the invention, the flow-rate ratio of described reacting gas is SiH4:NH3=1:0.1～1:100 or SiH4:N2=1:0.1～1:200 or SiH4:N2O=1:0.1～1:100 or SiH4:O2=1:0.1～1:100 or SiH4:N2: O2=1:0.1:0.1～1:100:100.
In one embodiment of the invention, described annealing is the 1～600min that anneals in noble gas or nitrogen and hydrogen mixture atmosphere, with temperature 600～1000 DEG C.
A kind of tunnelling silica nitrogen layer passivation contact solar cell provided by the invention and preparation method thereof, has the advantage that
1. owing to the tunneling barrier of silicon nitride and silicon oxynitride is relatively low, silicon oxide/silicon oxynitride gradient lamination, silicon oxynitride/silicon nitride gradient lamination, silicon oxide/silicon oxynitride/silicon nitride gradient lamination is adopted can suitably to relax the thickness of passivation tunnel layer under the premise ensureing tunneling efficiency as passivation tunnel layer, thus advantageously reducing passivation tunnel layer hole, reduce generation and the recombination velocity of leakage current, widen process window and improve technology stability；
2. passivation tunnel layer provided by the invention is silicon oxide or silicon oxynitride with the contact interface of silicon chip, has the chemical passivation effect that silicon interface is good, it is possible to effectively reduce interface state density；
3. owing to silicon oxynitride and silicon nitride have relatively low band gap, silicon oxide/silicon oxynitride gradient lamination will between silicon nitride band gap (being about 5.3eV) and silicon oxide band gap (being about 8.9eV) as the band gap of tunnel layer, thus carrier can be made there to be higher tunneling efficiency, it is thus advantageous to improve the tunneling efficiency of carrier, improves the efficiency of battery；
4., owing to being passivated the increase of tunneling layer thickness, be conducive to stopping the diffusion of impurity under high-temperature process, for instance the diffusion of doping film silicon layer phosphorus；Further, impurity diffusion is had barrier effect by silicon oxynitride, introduces silicon oxynitride in passivation tunnel layer gradient, is equally beneficial for improving the passivation tunnel layer barrier effect to impurity；
5. due in silicon oxynitride and silicon nitride defect level density higher, the positive charge being with in silicon oxide/silicon oxynitride gradient lamination, silicon oxynitride, silicon oxynitride/silicon nitride gradient lamination is more than pure silica, one of which is adopted to be conducive to introducing the fixed charge that more concentration is higher as passivation tunnel layer, thus improving passivation effect；
6. preparation technology is simple, it is possible to compatible mutually with existing industrialization preparation, it is simple to popularization and application.
Accompanying drawing explanation
Fig. 1 is TOPCon solar battery structure schematic diagram in prior art；
Fig. 2 is the structural representation that solaode provided by the invention is substrate embodiment with n-type silicon chip.
Fig. 3 is the structural representation that solaode provided by the invention is substrate embodiment with p-type silicon chip.
Detailed description of the invention
For making technical solution of the present invention more preferably clear, below in conjunction with drawings and the specific embodiments, the present invention is further detailed explanation.
In order to overcome silicon oxide as the weak point of passivation tunnel layer, the present invention adopts silicon oxide/silicon oxynitride gradient lamination, silicon oxynitride/silicon nitride gradient lamination, silicon oxide/silicon oxynitride/silicon nitride gradient lamination as passivation tunnel layer, it is provided that a kind of tunnelling silica nitrogen layer passivation contact solar cell.Wherein, referring to Fig. 2, the structural representation be solaode provided by the invention being substrate embodiment with n-type silicon chip, described solaode includes n-type silicon chip, described n-type silicon chip, as substrate, is sequentially laminated with p+ diffused emitter, passivation layer, antireflection layer and front electrode in n-type silicon chip front；Passivation tunnel layer, phosphorus doping n-type thin film silicon layer and backplate it is sequentially laminated with at the n-type silicon chip back side.Wherein, described passivation tunnel layer is the one in silicon oxide/silicon oxynitride gradient lamination, silicon oxynitride/silicon nitride gradient lamination, silicon oxide/silicon oxynitride/silicon nitride gradient lamination, and described silicon oxynitride is the silicon nitride of the doping silicon oxide of nitrogen or doped with oxygen；The nitrogen concentration of described silicon oxide/silicon oxynitride gradient lamination, silicon oxynitride/silicon nitride gradient lamination, silicon oxide/silicon oxynitride/silicon nitride gradient lamination reduces from away from the one of n-type silicon chip laterally adjacent to the side gradient of n-type silicon chip.
Further, the thickness of described passivation tunnel layer is preferably 0.5～5nm, more preferably 1～3.0nm.
Further, in described passivation tunnel layer, the diffusion depth of nitrogen is preferably 0.1～5nm, more elects 0.5～1.5nm as.
Further, described silicon oxide/silicon oxynitride gradient lamination is preferably not less than 20at.% away from the atomic concentration of nitrogen in the side 0.2nm depth bounds of described silicon chip, and in the side 0.2nm depth bounds of the contiguous described silicon chip of described silicon oxide/silicon oxynitride gradient lamination, the atomic concentration of nitrogen is preferably no greater than 5at.%.
Further, described silicon oxynitride/silicon nitride gradient lamination be preferably 30～57.1at.% away from the atomic concentration of nitrogen in the side 0.2nm depth bounds of described silicon chip, in the side 0.2nm depth bounds of the contiguous described silicon chip of described silicon oxynitride/silicon nitride gradient lamination, the atomic concentration of nitrogen is preferably 5～30at.%, and the atomic concentration of oxygen is preferably 10～40at.%.
Further, described silicon oxide/silicon oxynitride/silicon nitride gradient lamination is preferably 30～57.1at.% away from the atomic concentration of nitrogen in the side 0.2nm depth bounds of described silicon chip, and in the side 0.2nm depth bounds of the contiguous described silicon chip of described silicon oxide/silicon oxynitride/silicon nitride gradient lamination, the atomic concentration of nitrogen is preferably no greater than 5at.%.
Certainly in other embodiments, it is also possible to be adopt routine techniques means replace certain Rotating fields of solaode or add certain Rotating fields, or adopt different electrode structures.
In addition, solaode provided by the invention can also adopt p-type silicon chip as substrate, referring to Fig. 3, it is sequentially laminated with the first passivation tunnel layer, phosphorus doping n-type thin film silicon layer, tin indium oxide (ITO) layer and front electrode in p-type silicon chip front, is sequentially laminated with the second passivation tunnel layer, boron doped p type membrane silicon layer and backplate at the p-type silicon chip back side.Wherein said first passivation tunnel layer and/or described second passivation tunnel layer are the one in silicon oxide/silicon oxynitride gradient lamination, silicon oxynitride/silicon nitride gradient lamination, silicon oxide/silicon oxynitride/silicon nitride gradient lamination, and described silicon oxynitride is the silicon nitride of the doping silicon oxide of nitrogen or doped with oxygen；The nitrogen concentration of described silicon oxide/silicon oxynitride gradient lamination, silicon oxynitride/silicon nitride gradient lamination, silicon oxide/silicon oxynitride/silicon nitride gradient lamination reduces from away from the one of n-type silicon chip laterally adjacent to the side gradient of n-type silicon chip.
Further, described passivation tunnelling thickness layer by layer is preferably 0.5～5nm, more preferably 1～3.0nm.
Further, in described passivation tunnel layer, the diffusion depth of nitrogen is preferably 0.1～5nm, more preferably 0.5～1.5nm..
Further, described silicon oxide/silicon oxynitride gradient lamination is preferably not lower than 20at.% away from the atomic concentration of nitrogen in the side 0.2nm depth bounds of described silicon chip, and in the side 0.2nm depth bounds of the contiguous described silicon chip of described silicon oxide/silicon oxynitride gradient lamination, the atomic concentration of nitrogen is preferably not higher than 5at.%.
Further, described silicon oxynitride/silicon nitride gradient lamination be preferably 30～57.1at.% away from the atomic concentration of nitrogen in the side 0.2nm depth bounds of described silicon chip, in the side 0.2nm depth bounds of the contiguous described silicon chip of described silicon oxynitride/silicon nitride gradient lamination, the atomic concentration of nitrogen is preferably 5～30at.%, and the atomic concentration of oxygen is preferably 10～40at.%.
Further, described silicon oxide/silicon oxynitride/silicon nitride gradient lamination is preferably 30～57.1at.% away from the atomic concentration of nitrogen in the side 0.2nm depth bounds of described silicon chip, and in the side 0.2nm depth bounds of the contiguous described silicon chip of described silicon oxide/silicon oxynitride/silicon nitride gradient lamination, the atomic concentration of nitrogen is preferably no greater than 5at.%.
Certainly in other embodiments, it is also possible to be adopt routine techniques means replace solaode Rotating fields or add certain Rotating fields, or adopt different electrode structures.
The preparation method of a kind of tunnelling silica nitrogen layer provided by the invention passivation contact solar cell, described solaode includes silicon chip, passivation tunnel layer, doping film silicon layer, described passivation tunnel layer is between described silicon chip and described doping film silicon layer, wherein said preparation method comprises the steps, silicon chip is carried out pretreatment, silicon chip one side surface or both side surface after the pre-treatment generate silicon oxide layer then at described silicon oxide layer Surface Creation silicon oxynitride layer or silicon nitride layer, are annealed the product obtained afterwards processing；Or generate silicon oxynitride layer at described pretreated silicon chip one side surface or both side surface, then at described silicon oxynitride Surface Creation silicon nitride layer, be annealed the product obtained afterwards processing；Or generate silicon oxide layer at described pretreated silicon chip one side surface or both side surface, then at described silicon oxide layer Surface Creation silicon oxynitride layer, then again at described silicon oxynitride layer Surface Creation silicon nitride layer, be annealed the product obtained afterwards processing.
Shown in Figure 2, when employing n-type silicon chip is as the substrate of solaode, the preparation method of the tunnel oxide passivation contact solar cell of described improvement comprises the steps:
N-type silicon chip is carried out pretreatment；
N-type silicon chip side after the pre-treatment generates silicon oxide layer or silicon oxynitride layer；
At the silicon oxide layer Surface Creation silicon oxynitride layer generated, or at the silicon oxynitride layer Surface Creation silicon nitride layer generated, or continue at silicon oxynitride layer Surface Creation silicon nitride layer after the silicon oxide layer Surface Creation silicon oxynitride layer generated；
By the silicon oxide layer of the stacking of generation and silicon oxynitride layer, or the silicon oxynitride layer of stacking and silicon nitride layer, or the silicon oxide layer of stacking, silicon oxynitride layer and silicon nitride layer, it is annealed processing, the nitrogen element making it away from n-type silicon chip spreads to n-type silicon chip direction, thus generating silicon oxide/silicon oxynitride gradient lamination or silicon oxynitride/silicon nitride gradient lamination or silicon oxide/silicon oxynitride/silicon nitride gradient lamination；
Surface Creation phosphorus doping n-type thin film silicon layer at silicon oxide/silicon oxynitride gradient lamination or silicon oxynitride/silicon nitride gradient lamination or silicon oxide/silicon oxynitride/silicon nitride gradient lamination；
Backplate is generated in phosphorus doping n-type thin film silicon surface；
Silicon chip opposite side after the pre-treatment generates p+ emitter stage；
Passivation layer is generated in p+ emitter surface；
Antireflection layer is generated in passivation layer surface；
Front electrode is generated at battery front side.
Above-mentioned steps does not limit its sequencing except what must implement on the basis of another step.
Shown in Figure 3, when employing p-type silicon chip is as the substrate of solaode, the preparation method of the tunnel oxide passivation contact solar cell of described improvement comprises the steps:
P-type silicon chip is carried out pretreatment；
P-type silicon chip both sides after the pre-treatment generate silicon oxide layer or silicon oxynitride layer；
At the silicon oxide layer Surface Creation silicon oxynitride layer generated, or at the silicon oxynitride layer Surface Creation silicon nitride layer generated, or continue at silicon oxynitride layer Surface Creation silicon nitride layer after the silicon oxide layer Surface Creation silicon nitride layer generated；
By the silicon oxide layer of the stacking of generation and silicon oxynitride layer, or the silicon oxynitride layer of stacking and silicon nitride layer, or the product of the silicon oxide layer of stacking, silicon oxynitride layer and silicon nitride layer is annealed processing, the nitrogen element making it away from p-type silicon chip spreads to p-type silicon chip direction, thus generating silicon oxide/silicon oxynitride gradient lamination or silicon oxynitride/silicon nitride gradient lamination or silicon oxide/silicon oxynitride/silicon nitride gradient lamination；
Generate phosphorus doping n-type thin film silicon layer at silicon oxide/silicon oxynitride gradient lamination or silicon oxynitride/silicon nitride gradient lamination or silicon oxide/silicon oxynitride/silicon nitride gradient stack surface, or generate boron doped p type membrane silicon layer at silicon oxide/silicon oxynitride gradient lamination or silicon oxynitride/silicon nitride gradient lamination or silicon oxide/silicon oxynitride/silicon nitride gradient stack surface；
In boron doped p type membrane silicon layer Surface Creation backplate；
Indium tin oxide layer is generated in phosphorus doping n-type thin film silicon surface；
Front electrode is generated at battery front side.
Above-mentioned steps does not limit its sequencing except what must implement on the basis of another step.
Further, pretreatment silicon chip carried out includes but not limited to the cleaning to silicon chip, making herbs into wool, polishing.
Further, the method generating silicon oxide layer can be selected from prior art, for instance UV-ozone method (UV-Ozone), concentrated nitric acid method, thermal oxidation method, sol-gal process, physical vaporous deposition, chemical vapour deposition technique, liquid phase deposition etc..
Further, the method generating silicon oxynitride layer can be selected from prior art, for instance atomic layer deposition method, chemical vapour deposition technique, reactive sputtering, direct nitridation method, ionic-implantationDeng, described chemical vapour deposition technique includes but not limited to that plasma enhanced chemical vapor deposition method (PEVCD), radio frequency plasma strengthen method, chemical vapour deposition technique, electron cyclotron resonance plasma enhancing chemical vapour deposition technique, radio frequency glow discharge plasma reinforced chemical vapour deposition method, inductively coupled plasma enhancing chemical vapour deposition technique, Low Pressure Chemical Vapor Deposition, photo chemical vapor deposition method, thermal chemical vapor deposition method.
Further, the method generating silicon nitride layer can be selected from prior art, for instance atomic layer deposition method, chemical vapour deposition technique, reactive sputtering, direct nitridation method, ionic-implantationDeng, described chemical vapour deposition technique includes but not limited to that plasma enhanced chemical vapor deposition method (PEVCD), radio frequency plasma strengthen method, chemical vapour deposition technique, electron cyclotron resonance plasma enhancing chemical vapour deposition technique, radio frequency glow discharge plasma reinforced chemical vapour deposition method, inductively coupled plasma enhancing chemical vapour deposition technique, Low Pressure Chemical Vapor Deposition, photo chemical vapor deposition method, thermal chemical vapor deposition method.
Further, generate silicon oxide layer, silicon oxynitride layer, silicon nitride layer method preferably employ plasma enhanced chemical vapor deposition method (PEVCD), using one or more in Nitrogen element gas, siliceous elemental gas, oxygen-containing elemental gas as reacting gas, react certain time under certain temperature, radio-frequency power, cavity air pressure conditions, obtain silicon oxide layer, silicon oxynitride layer, silicon nitride layer product.Described temperature is preferably 20～500 DEG C, and described radio-frequency power is preferably 30～150W, and described cavity air pressure is preferably 30～120Pa, and described Nitrogen element gas is preferably SiH4、N2、NH3、N2O、O2In one or more, reaction gas flow than be preferably be SiH4:NH3=1:0.1～1:100 or SiH4:N2=1:0.1～1:200 or SiH4:N2O=1:0.1～1:100 or SiH4:O2=1:0.1～1:100 or SiH4:N2: O2=1:0.1:0.1～1:100:100；The flow of reacting gas is preferably SiH4: 5～30sccm, NH3: 10～50sccm, N2: 10～50sccm.
Further, annealing is preferably in noble gas argon or nitrogen or nitrogen and hydrogen mixture atmosphere, is annealed into 1～600min with temperature 600～1000 DEG C.
Further, method at silicon oxide/silicon oxynitride gradient lamination or silicon oxynitride/silicon nitride gradient lamination or silicon oxide/silicon oxynitride/silicon nitride gradient stack surface generation phosphorus doping n-type thin film silicon layer or generation boron doped p type membrane silicon layer can be selected from prior art, for instance molecular beam epitaxy, pulsed laser deposition, magnetron sputtering method, spray pyrolysis, chemical vapour deposition technique, sol-gel process.
Further, generate backplate, generate p+ emitter stage, generate passivation layer, antireflection layer, indium tin oxide layer method be all selected from prior art.
The preparation method of solaode provided by the invention, except the preparation of passivation tunnel layer, all can adopt prior art means to prepare, and the present invention is not had materially affect by its concrete technological means.
Below in conjunction with specific embodiment, the present invention is further described.
Embodiment 1
The present embodiment is with n-type silicon chip for substrate, first n-type silicon chip is carried out pretreatment, use Tetramethylammonium hydroxide (TMAH), fluohydric acid gas (HF) and RCA cleanout fluid that the n-type silicon chip as substrate is carried out making herbs into wool, to remove mechanical damage layer, greasy dirt and metal impurities, form up-and-down matte on surface simultaneously；On n-type silicon chip side after the pre-treatment, grow, by the concentrated nitric acid of 68%, the silicon oxide (SiO that a layer thickness is 1.5nmx) layer；Then the n-type silicon chip generating silicon oxide layer is placed in plasma enhanced chemical vapor deposition (PECVD) equipment, at reacting gas SiH4Flow is 1sccm, NH3Flow is 10sccm, and cavity air pressure is 10Pa, and temperature is 100 DEG C, reacts 0.5min when radio-frequency power is 50W；Mix, at nitrogen hydrogen, the 60min that anneals under 800 DEG C of conditions in (FormingGas) atmosphere afterwards, eliminate defect, generate silicon oxide/silicon oxynitride gradient lamination；Generating thickness by plasma enhanced chemical vapor deposition method at silicon oxide/silicon oxynitride gradient stack surface be 20nm, phosphorus doping density is 1e19cm-3Phosphorus doping n-type thin film silicon layer；Generate, in phosphorus doping n-type thin film silicon surface, the Ag metallic back plate that a layer thickness is 1000nm by the method for magnetic control degree of spattering；Silicon chip opposite side after the pre-treatment is by by boron oxide (BxOy) solid source diffusion formed a layer thickness be 500nm generate p+ emitter layer；It is being 3nm aluminium oxide (Al by atomic deposition method in p+ emitter stage opposite side Surface Creation a layer thickness2O3) passivation layer；Utilize plasma enhanced chemical vapor deposition method at aluminium oxide (Al2O3) passivation layer opposite side Surface Creation a layer thickness is 50nm silicon nitride (SiNx) antireflection layer；Screen printing technique is adopted to generate front electrode at battery front side；Prepare solaode A1.
Solaode C-V characteristic test system (model: SoliA, U.S. NewportOrie provide) is adopted to measure the surface saturation current density of solaode A1, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency；Ellipsometer (model: M-1500DI, J.A.Woollam company of the U.S. provides) is adopted to measure the passivation tunneling layer thickness of solaode A1；X-ray fluorescence spectroscopy (model: AXISUTLTRADLD, Shimadzu Corporation of Japan provides) and ion microprobe (model: IMS1280, Ai Wensi company provides) is adopted to measure the passivation tunnel layer component of solaode A1.Result is in Table 1.
Embodiment 2
Preparing solaode with the method that embodiment 1 is identical, being distinctive in that in n-type silicon chip one side, growth thickness is the silicon oxide (SiO of 1.2nmx) layer；Then the n-type silicon chip generating silicon oxide layer is placed in plasma enhanced chemical vapor deposition (PECVD) equipment, at reacting gas SiH4Flow is 1sccm, NH3Flow is 10sccm, and cavity air pressure is 10Pa, and temperature is 100 DEG C, reacts 0.5min when radio-frequency power is 50W；Mix, at nitrogen hydrogen, the 30min that anneals under 850 DEG C of conditions in (FormingGas) atmosphere afterwards, prepare solaode A2.
Measuring the surface saturation current density of solaode A2, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A2, component result are in Table 1.
Embodiment 3
Preparing solaode with the method that embodiment 1 is identical, being distinctive in that in n-type silicon chip one side, growth thickness is the silicon oxide (SiO of 1nmx) layer；Then the n-type silicon chip generating silicon oxide layer is placed in plasma enhanced chemical vapor deposition (PECVD) equipment, at reacting gas SiH4Flow is 1sccm, NH3Flow is 10sccm, and cavity air pressure is 10Pa, and temperature is 100 DEG C, reacts 1.5min when radio-frequency power is 50W；Mix, at nitrogen hydrogen, the 1.5min that anneals under 850 DEG C of conditions in (FormingGas) atmosphere afterwards, prepare solaode A3.
Measuring the surface saturation current density of solaode A3, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A3, component result are in Table 1.
Embodiment 4
Preparing solaode with the method that embodiment 1 is identical, being distinctive in that in n-type silicon chip one side, growth thickness is the silicon oxide (SiO of 0.5nmx) layer；Then the n-type silicon chip generating silicon oxide layer is placed in plasma enhanced chemical vapor deposition (PECVD) equipment, at reacting gas SiH4Flow is 5sccm, NH3Flow is 20sccm, and cavity air pressure is 15Pa, and temperature is 200 DEG C, reacts 2.5min when radio-frequency power is 30W；Mix, at nitrogen hydrogen, the 480min that anneals under 600 DEG C of conditions in (FormingGas) atmosphere afterwards, prepare solaode A4.
Measuring the surface saturation current density of solaode A4, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A4, component result are in Table 1.
Embodiment 5
Preparing solaode with the method that embodiment 1 is identical, being distinctive in that in n-type silicon chip one side, growth thickness is the silicon oxide (SiO of 1nmx) layer；Then the n-type silicon chip generating silicon oxide layer is placed in plasma enhanced chemical vapor deposition (PECVD) equipment, at reacting gas SiH4Flow is 10sccm, NH3Flow is 50sccm, and cavity air pressure is 10Pa, and temperature is 400 DEG C, reacts 3min when radio-frequency power is 40W；Mix, at nitrogen hydrogen, the 3min that anneals under 1000 DEG C of conditions in (FormingGas) atmosphere afterwards, prepare solaode A5.
Measuring the surface saturation current density of solaode A5, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A5, component result are in Table 1.
Embodiment 6
Preparing solaode with the method that embodiment 1 is identical, being distinctive in that in n-type silicon chip one side, growth thickness is the silicon oxide (SiO of 1nmx) layer；Then the n-type silicon chip generating silicon oxide layer is positioned in plasma enhanced chemical vapor deposition (PECVD) equipment, at reacting gas SiH4Flow is 10sccm, N2O flow is 50sccm, and cavity air pressure is 10Pa, and temperature is 250 DEG C, reacts 3min, at silicon oxide layer superficial growth silicon oxynitride (SiON) layer when radio-frequency power is 100W；Afterwards at reacting gas SiH4Flow is 10sccm, N2Flow is 15sccm, and cavity air pressure is 10Pa, and temperature is 250 DEG C, reacts 3min, at silicon oxynitride (SiON) superficial growth silicon nitride (SN when radio-frequency power is 100Wx), mix, at nitrogen hydrogen, the 90min that anneals under 800 DEG C of conditions in (FormingGas) atmosphere afterwards, prepare solaode A6.
Measuring the surface saturation current density of solaode A6, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A6, component result are in Table 1.
Embodiment 7
Prepare solaode with the method that embodiment 1 is identical, be distinctive in that and strengthen in chemical vapour deposition (CVD) (PECVD) equipment in gas ions, at reacting gas SiH4Flow is 10sccm, N2O flow is 50sccm, and cavity air pressure is 10Pa, and temperature is 250 DEG C, reacts 3min when radio-frequency power is 100W, and in n-type silicon chip one side, growth thickness is silicon oxynitride (SiON) layer of 2.5nm；Then at reacting gas SiH4Flow is 10sccm, NH3Flow is 50sccm, and cavity air pressure is 10Pa, and temperature is 400 DEG C, reacts 1min, at silicon oxynitride layer superficial growth silicon nitride (SN when radio-frequency power is 40Wx) layer；Mix, at nitrogen hydrogen, the 30min that anneals under 900 DEG C of conditions in (FormingGas) atmosphere afterwards, prepare solaode A7.
Measuring the surface saturation current density of solaode A7, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A7, component result are in Table 1.
Comparative example 1
The present embodiment is with n-type silicon chip for substrate, first n-type silicon chip is carried out pretreatment, uses TMAH, HF and RCA cleanout fluid that n-type silicon chip substrate is carried out making herbs into wool, to remove mechanical damage layer, greasy dirt and metal impurities, form up-and-down matte on surface simultaneously；On n-type silicon chip side after the pre-treatment, grow, by the concentrated nitric acid of 68%, the silicon oxide (SiO that a layer thickness is 1.3nmx) layer；Be 20nm, phosphorus doping density by plasma enhanced chemical vapor deposition method at silicon oxide layer Surface Creation thickness it is 1e19cm-3Phosphorus doping n-type thin film silicon layer；Generate, in phosphorus doping n-type thin film silicon surface, the Ag metal electrode that a layer thickness is 1000nm by the method for magnetic control degree of spattering；Silicon chip opposite side after the pre-treatment is by by BBr3It is that 500nm generates p+ emitter layer that gas source diffusion forms a layer thickness；It is 3nm aluminium oxide (Al by atomic deposition method generating a layer thickness in p+ emitter surface2O3) passivation layer；Utilize plasma enhanced chemical vapor deposition method at aluminium oxide (Al2O3) to generate a layer thickness be 60nm silicon nitride (SiN to passivation layer surfacex) antireflection layer；Screen printing technique is adopted to generate front electrode at battery front side；Prepare solaode D1.
Measuring the surface saturation current density of solaode D1, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode D1, result is in Table 1.
The measurement result of the solaode of table 1 embodiment 1～7, comparative example 1 preparation
As it can be seen from table 1 when the thickness of tunnelling passivation layer is when more than 2nm, remain to obtain with prior art performance quite or more excellent solaode.
Embodiment 8
The present embodiment is with p-type silicon chip for substrate, first p-type silicon chip is carried out pretreatment, uses TMAH, HF and RCA cleanout fluid that p-type silicon chip substrate is carried out making herbs into wool, to remove mechanical damage layer, greasy dirt and metal impurities, form up-and-down matte on surface simultaneously；On p-type silicon chip both sides after the pre-treatment, the concentrated nitric acid by 68% respectively grows the silicon oxide (SiO that a layer thickness is 1.4nmx) layer；Then the p-type silicon chip generating silicon oxide layer is placed in plasma enhanced chemical vapor deposition (PECVD) equipment, at reacting gas SiH4Flow is 1sccm, NH3Flow is 10sccm, and cavity air pressure is 30Pa, and temperature is 100 DEG C, reacts 0.5min when radio-frequency power is 50W；Mix, at nitrogen hydrogen, the 60min that anneals under 800 DEG C of conditions in (FormingGas) atmosphere afterwards, eliminate defect, generate the silicon oxide/silicon oxynitride gradient lamination with gradient concentration silicon oxynitride；Generating thickness by plasma enhanced chemical vapor deposition method at one layer of silicon oxide/silicon oxynitride gradient stack surface be 20nm, phosphorus doping density is 1e19cm-3Phosphorus doping n-type thin film silicon layer, generating thickness by plasma enhanced chemical vapor deposition method at another layer of silicon oxide/silicon oxynitride gradient stack surface be 20nm, boron doping concentration is 1e15cm-3Boron doped p type membrane silicon layer；By the method for magnetic control degree of spattering at the Ag metal electrode that boron doped p type membrane silicon layer Surface Creation a layer thickness is 1000nm；Generate, in phosphorus doping n-type thin film silicon surface, the indium tin oxide layer that a layer thickness is 200nm by the method for magnetic control degree of spattering；Screen printing technique is adopted to generate front electrode at battery front side；Prepare solaode A8.
Measuring the surface saturation current density of solaode A8, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A8, component result are in Table 2.
Embodiment 9
Preparing solaode with the method that embodiment 8 is identical, be distinctive in that on p-type silicon chip both sides after the pre-treatment, the concentrated nitric acid by 68% respectively grows the silicon oxide (SiO that a layer thickness is 0.5nmx) layer；Then the p-type silicon chip generating silicon oxide layer is placed in plasma enhanced chemical vapor deposition (PECVD) equipment, at reacting gas SiH4Flow is 15sccm, NH3Flow is 50sccm, and cavity air pressure is 100Pa, and temperature is 200 DEG C, reacts 2min when radio-frequency power is 30W；Anneal 600min afterwards in argon gas atmosphere under 600 DEG C of conditions, eliminates defect, generates the silicon oxide/silicon oxynitride gradient lamination with gradient concentration silicon oxynitride, prepares solaode A9.
Measuring the surface saturation current density of solaode A9, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A9, component result are in Table 2.
Embodiment 10
Preparing solaode with the method that embodiment 8 is identical, be distinctive in that on p-type silicon chip both sides after the pre-treatment, the concentrated nitric acid by 68% respectively grows the silicon oxide (SiO that a layer thickness is 3.5nmx) layer；Then the p-type silicon chip generating silicon oxide layer is placed in plasma enhanced chemical vapor deposition (PECVD) equipment, at reacting gas SiH4Flow is 30sccm, NH3Flow is 40sccm, and cavity air pressure is 30Pa, and temperature is 400 DEG C, reacts 0.5min when radio-frequency power is 150W；Anneal 20min afterwards in nitrogen atmosphere under 1000 DEG C of conditions, eliminates defect, generates the silicon oxide/silicon oxynitride gradient lamination with gradient concentration silicon oxynitride, prepares solaode A10.
Measuring the surface saturation current density of solaode A10, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A10, component result are in Table 2.
Embodiment 11
Preparing solaode with the method that embodiment 8 is identical, be distinctive in that on p-type silicon chip both sides after the pre-treatment, the concentrated nitric acid by 68% respectively grows the silicon oxide (SiO that a layer thickness is 3nmx) layer；Then the p-type silicon chip generating silicon oxide layer is placed in plasma enhanced chemical vapor deposition (PECVD) equipment, at reacting gas SiH4Flow is 25sccm, N2Flow is 25sccm, and cavity air pressure is 120Pa, and temperature is 50 DEG C, reacts 2min when radio-frequency power is 120W；Mix, at nitrogen hydrogen, the 200min that anneals under 800 DEG C of conditions in (FormingGas) atmosphere afterwards, eliminate defect, generate the silicon oxide/silicon oxynitride gradient lamination with gradient concentration silicon oxynitride, prepare solaode A11.
Measuring the surface saturation current density of solaode A11, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A11, component result are in Table 2.
Embodiment 12
Preparing solaode with the method that embodiment 8 is identical, be distinctive in that on p-type silicon chip both sides after the pre-treatment, the concentrated nitric acid by 68% respectively grows the silicon oxide (SiO that a layer thickness is 2nmx) layer；Then the p-type silicon chip generating silicon oxide layer is placed in plasma enhanced chemical vapor deposition (PECVD) equipment, at reacting gas SiH4Flow is 10sccm, N2Flow is 10sccm, and cavity air pressure is, 60Pa, and temperature is 500 DEG C, reacts 3min when radio-frequency power is 80W；Mix, at nitrogen hydrogen, the 20min that anneals under 900 DEG C of conditions in (FormingGas) atmosphere afterwards, eliminate defect, generate the silicon oxide/silicon oxynitride gradient lamination with gradient concentration silicon oxynitride, prepare solaode A12.
Measuring the surface saturation current density of solaode A12, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A12, component result are in Table 2.
Embodiment 13
Prepare solaode with the method that embodiment 8 is identical, be distinctive in that the silicon oxide (SiO that growth thickness is 1nm in p-type silicon chip both sidesx) layer, then the p-type silicon chip generating silicon oxide layer is positioned in plasma enhanced chemical vapor deposition (PECVD) equipment, at reacting gas SiH4Flow is 10sccm, N2O flow is 150sccm, and cavity air pressure is 10Pa, and temperature is 250 DEG C, reacts 3min, at silicon oxynitride (SiON) layer that silicon oxide layer superficial growth thickness is 3nm when radio-frequency power is 100W；Afterwards at reacting gas SiH4Flow is 10sccm, N2Flow is 15sccm, and cavity air pressure is 10Pa, and temperature is 250 DEG C, reacts 3min, at silicon oxynitride (SiON) superficial growth silicon nitride (SN when radio-frequency power is 100Wx), mix, at nitrogen hydrogen, the 20min that anneals under 900 DEG C of conditions in (FormingGas) atmosphere afterwards, prepare solaode A13.
Measuring the surface saturation current density of solaode A13, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A13, component result are in Table 2.
Embodiment 14
Prepare solaode with the method that embodiment 8 is identical, be distinctive in that and strengthen in chemical vapour deposition (CVD) (PECVD) equipment in gas ions, at reacting gas SiH4Flow is 10sccm, N2O flow is 150sccm, and cavity air pressure is 10Pa, and temperature is 250 DEG C, reacts 2min when radio-frequency power is 100W, and on the both sides of p-type silicon chip, growth thickness is silicon oxynitride (SiON) layer of 2nm；Then at reacting gas SiH4Flow is 10sccm, N2Flow is 10sccm, and cavity air pressure is, 60Pa, and temperature is 500 DEG C, reacts 1min, at silicon oxynitride layer superficial growth silicon nitride (SN when radio-frequency power is 80Wx) layer；The 30min that anneals under 900 DEG C of conditions in (FormingGas) atmosphere is mixed afterwards at nitrogen hydrogen.
Measuring the surface saturation current density of solaode A14, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A14, component result are in Table 2.
Comparative example 2
P-type silicon chip, with p-type silicon chip for substrate, is first carried out pretreatment by the present embodiment, uses HF and HCl that p-type silicon chip substrate is carried out making herbs into wool, in order to remove mechanical damage layer, greasy dirt and metal impurities, forms up-and-down matte on surface simultaneously；On p-type silicon chip both sides after the pre-treatment, the concentrated nitric acid by 68% respectively grows the silicon oxide (SiO that a layer thickness is 2nmx) layer；Be 20nm, phosphorus doping density by plasma enhanced chemical vapor deposition method at one layer of silicon oxide layer Surface Creation thickness it is 1e19Phosphorus doping n-type thin film silicon layer, be 20nm, boron doping concentration by plasma enhanced chemical vapor deposition method at another layer of silicon oxide layer Surface Creation thickness be 1e15Boron doped p type membrane silicon layer；By the method for magnetic control degree of spattering at the Ag metal electrode that boron doped p type membrane silicon layer Surface Creation a layer thickness is 1000nm；Generate, in phosphorus doping n-type thin film silicon surface, the indium tin oxide layer that a layer thickness is 200nm by the method for magnetic control degree of spattering；Screen printing technique is adopted to generate front electrode at battery front side；Prepare solaode D2.
Measuring the surface saturation current density of solaode A14, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, the passivation tunneling layer thickness of solaode A14, result is in Table 2.
Measuring the surface saturation current density of solaode D2, open-circuit voltage, short circuit current, fill factor, curve factor, conversion efficiency in the same manner as in Example 1, result is in Table 2.
The measurement result of the solaode of table 2 embodiment 6-10, comparative example 2 preparation
From table 2 it can be seen that when the thickness of tunnelling passivation layer is when more than 2nm, remain to obtain with prior art performance quite or more excellent solaode.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, for the person of ordinary skill of the art, without departing from the inventive concept of the premise, it is also possible to making some deformation and improvement, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. tunnelling silica nitrogen layer passivation contact solar cell and, wherein, described solaode includes silicon chip, passivation tunnel layer, doping film silicon layer, described passivation tunnel layer is between described silicon chip and described doping film silicon layer, it is characterized in that, described passivation tunnel layer is the one in silicon oxide/silicon oxynitride gradient lamination, silicon oxynitride/silicon nitride gradient lamination, silicon oxide/silicon oxynitride/silicon nitride gradient lamination；Described silicon oxynitride is the silicon nitride of the doping silicon oxide of nitrogen or doped with oxygen；The nitrogen concentration of described silicon oxide/silicon oxynitride gradient lamination, silicon oxynitride/silicon nitride gradient lamination, silicon oxide/silicon oxynitride/silicon nitride gradient lamination reduces from the side away from silicon chip to the side gradient of adjacent silicon wafer.
2. solaode according to claim 1, it is characterised in that the thickness of described passivation tunnel layer is 0.5～5nm.
3. solaode according to claim 1, it is characterised in that in described passivation tunnel layer, the diffusion depth of nitrogen is 0.1～5nm.
4. the solaode according to any one of claims 1 to 3, it is characterized in that described silicon oxide/silicon oxynitride gradient lamination is not less than 20at.% away from the atomic concentration of nitrogen in the side 0.2nm depth bounds of described silicon chip, in the side 0.2nm depth bounds of the contiguous described silicon chip of described silicon oxide/silicon oxynitride gradient lamination, the atomic concentration of nitrogen is not higher than 5at.%.
5. the solaode according to any one of claims 1 to 3, what it is characterized in that described silicon oxynitride/silicon nitride gradient lamination is 30～57.1at.% away from the atomic concentration of nitrogen in the side 0.2nm depth bounds of described silicon chip, in the side 0.2nm depth bounds of the contiguous described silicon chip of described silicon oxynitride/silicon nitride gradient lamination, the atomic concentration of nitrogen is 5～30at.%, and the atomic concentration of oxygen is 10～40at.%.
6. the solaode according to any one of claims 1 to 3, it is characterized in that described silicon oxide/silicon oxynitride/silicon nitride gradient lamination is 30～57.1at.% away from the atomic concentration of nitrogen in the side 0.2nm depth bounds of described silicon chip, in the side 0.2nm depth bounds of the contiguous described silicon chip of described silicon oxide/silicon oxynitride/silicon nitride gradient lamination, the atomic concentration of nitrogen is not higher than 5at.%.
7. a tunnelling silica nitrogen layer passivation contact solar cell preparation method, described solaode includes silicon chip, passivation tunnel layer, doping film silicon layer, described passivation tunnel layer is between described silicon chip and described doping film silicon layer, it is characterized in that, the preparation method of described passivation tunnel layer comprises the following steps: generate silicon oxide layer at described silicon chip surface, then at described silicon oxide layer Surface Creation silicon oxynitride layer or silicon nitride layer, it is annealed the product obtained afterwards processing；Or generate silicon oxynitride layer at described silicon chip surface, then at described silicon oxynitride Surface Creation silicon nitride layer, be annealed the product obtained afterwards processing；Or generate silicon oxide layer at described silicon chip surface, then at described silicon oxide layer Surface Creation silicon oxynitride layer, then again at described silicon oxynitride layer Surface Creation silicon nitride layer, be annealed the product obtained afterwards processing.
null8. preparation method according to claim 7，It is characterized in that described at described silicon chip surface generation silicon oxide layer、At described silicon oxide layer Surface Creation silicon oxynitride layer or silicon nitride layer、Silicon oxynitride layer is generated at described silicon chip surface、Preparation method at described silicon oxynitride Surface Creation silicon nitride layer includes ald and prepares method、Chemical vapour deposition technique、Reactive sputtering、Direct nitridation method、Ionic-implantation，Described chemical vapour deposition technique includes plasma reinforced chemical vapour deposition method、Microwave plasma strengthens chemical vapour deposition (CVD)、Radio frequency plasma strengthens method、Heated filament plasma gas phase deposition、Low Pressure Chemical Vapor Deposition、Middle pressure chemical vapor deposition method、Radio frequency glow discharge plasma reinforced chemical vapour deposition method、Inductively coupled plasma strengthens chemical vapour deposition technique、Photo chemical vapor deposition method、Thermal chemical vapor deposition method.
9. preparation method according to claim 8, it is characterised in that the reacting gas of described chemical vapour deposition technique includes SiH4、N2、NH3、N2O、O2In one or more.
10. preparation method according to claim 9, it is characterised in that the flow-rate ratio of described reacting gas is SiH4:NH3=1:0.1～1:100 or SiH4:N2=1:0.1～1:200 or SiH4:N2O=1:0.1～1:100 or SiH4:O2=1:0.1～1:100 or SiH4:N2: O2=1:0.1:0.1～1:100:100.
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