CN116250173A

CN116250173A - Motor driving circuit and motor module

Info

Publication number: CN116250173A
Application number: CN202080105615.4A
Authority: CN
Inventors: 片冈耕太郎
Original assignee: Nidec Corp
Current assignee: Nidec Corp
Priority date: 2020-09-30
Filing date: 2020-12-24
Publication date: 2023-06-09
Also published as: TW202220366A; WO2022070446A1; TWI784727B

Abstract

Provided is a motor drive circuit capable of suppressing switching of PWM phases by generating a long ON (or OFF) duration immediately after switching of PWM signal phases. A motor drive circuit (100) has a first input terminal (P), a second input terminal (N), a capacitor (C), three serial bodies (112), and a signal generation unit (120). The PWM signals include a normal phase PWM Signal (PS) and an inverse phase PWM signal (NS). The PWM signal further has a connection pulse group (AS) between the normal phase PWM Signal (PS) and the reverse phase PWM signal (NS) and before and after the phase switching timing (tsw). The connection pulse group (AS) has a connection-on pulse (ASon) and a connection-off pulse (ASoff). The connection-on pulse (ASon) has a connection-on period (ATon). The off-connection pulse (ASoff) has an off-connection period (AToff). The connection on period (ATon) is shorter than the on period of 1 cycle of the PWM cycle before or after the phase switching.

Description

Motor driving circuit and motor module

Technical Field

The invention relates to a motor drive circuit and a motor module. The present application claims priority based on 30 th 9 th 2020 in japanese patent application No. 2020-164999, the contents of which are incorporated herein by reference.

Background

As a driving method of a three-phase motor, a two-phase modulation method is known (for example, patent document 1). The inverter device described in patent document 1 includes a control unit that compares command values of two phases other than one of the three phases that are kept on or off with two triangular reference waves having 180 degrees phase difference and equal amplitude and frequency, and PWM controls on/off of each switching element corresponding to the command values. The control unit switches one of the triangular reference waves to the other of the triangular reference waves, which is compared with the command value of one of the three phases that is kept on or off. Thus, compared with the case where PWM control is performed by comparing the command values of two phases other than the one phase that is kept on or off of the three phases with the same triangular reference wave, the current (capacitor ripple current) flowing in and out of the capacitor can be reduced.

Prior art literature

Patent literature

Patent document 1: japanese patent laid-open No. 2006-197707

Disclosure of Invention

Problems to be solved by the invention

However, in the inverter device described in patent document 1, switching of the phase of the PWM signal is limited to a case where the phase to be switched is kept on or off. That is, the triangular reference wave used for generating the PWM waveform of each phase is fixed to one of two triangular reference waves having 180 degrees phase difference during the switching period of the phase, and the triangular reference wave is not switched during the switching period. However, in the case of providing the output voltage mode as shown in fig. 4 (b) of patent document 1, since the motor connected to the output is an inductive load, a delay occurs in the current waveform with respect to the voltage waveform. At this time, if PWM control is performed on two phases of the switch by triangular waves having phases 180 degrees apart in a part of the rotation angle section, reverse current flow from the inverter to the capacitor occurs, and the effect of reducing the ripple current of the capacitor is reduced. In some cases, the total capacitor ripple current may be increased as compared to the case where the same triangular wave is used. In order to suppress this, it is necessary to change the phases of the PWM signals of two phases in the switch in a rotation angle section in which no reverse current flow from the inverter to the capacitor occurs, and to switch the phases of the same PWM signals in the rotation angle section in which reverse current flow occurs. However, in the inverter device described in patent document 1, when switching of the phase of the PWM signal is performed while the phase to be switched is not kept on or off, there is a possibility that a long on (or off) duration occurs immediately after switching of the phase of the PWM signal.

The present invention has been made in view of the above-described problems, and an object thereof is to provide a motor drive circuit and a motor module capable of suppressing the occurrence of a long on (or off) duration immediately after switching to perform switching of PWM phases.

Means for solving the problems

The exemplary motor drive circuit of the present invention controls the drive of a three-phase motor in a two-phase modulation scheme. The motor driving circuit includes a first input terminal, a second input terminal, a capacitor, three serial bodies, and a signal generating unit. A first voltage is applied to the first input terminal. A second voltage lower than the first voltage is applied to the second input terminal. The capacitor is connected between the first input terminal and the second input terminal. The three series bodies are formed by connecting two semiconductor switching elements in series. The signal generating unit generates PWM signals to be input to the three serial bodies, respectively. The PWM signals include a positive phase PWM signal and an inverse phase PWM signal. The phase of the inverted PWM signal is different from the phase of the normal phase PWM signal. The signal generating unit switches the phase of the PWM signal at a phase switching timing. The PWM signal also has a set of connected pulses between the positive phase PWM signal and the negative phase PWM signal and before and after the phase switching opportunity. The connection pulse group has a connection on pulse and a connection off pulse. The connection-on pulse has a connection-on period. The disconnection pulse has a disconnection period. The connection on period is shorter than the on period of 1 period of the PWM period before or after the phase switching.

An exemplary motor module of the present invention has the motor driving circuit and the three-phase motor described above. The three-phase motor is driven by the motor driving circuit.

Effects of the invention

According to the exemplary invention, it is possible to suppress switching of the PWM phase by generating a long on (or off) duration immediately after switching of the PWM signal phase.

Drawings

Fig. 1 is a block diagram of a motor module of an embodiment of the present invention.

Fig. 2 is a circuit diagram showing the inverter section.

Fig. 3 is a diagram showing PWM signals of an embodiment of the present invention.

Fig. 4 is a diagram showing PWM signals of an embodiment of the present invention.

Fig. 5 is a diagram showing PWM signals of the embodiment of the present invention.

Fig. 6 is a diagram showing PWM signals of the embodiment of the present invention.

Fig. 7 is a diagram showing PWM signals of the embodiment of the present invention.

Fig. 8 is a diagram showing PWM signals of the embodiment of the present invention.

Fig. 9 is a diagram showing PWM signals of the embodiment of the present invention.

Fig. 10 is a diagram showing PWM signals of the embodiment of the present invention.

Fig. 11 is a diagram showing PWM signals according to an embodiment of the present invention.

Fig. 12 is a diagram showing PWM signals according to an embodiment of the present invention.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals, and description thereof will not be repeated.

A motor according to an embodiment of the present invention will be described with reference to fig. 1 and 2. Fig. 1 is a block diagram of a motor module 200 according to an embodiment of the present invention. Fig. 2 is a circuit diagram showing the inverter section 110.

As shown in fig. 1, the motor module 200 has a motor drive circuit 100 and a three-phase motor M. The three-phase motor M is driven by a motor driving circuit 100. The three-phase motor M is, for example, a brushless DC motor. The three-phase motor M has a U-phase, a V-phase, and a W-phase.

The motor driving circuit 100 controls driving of the three-phase motor M in a two-phase modulation manner. The motor drive circuit 100 includes an inverter section 110 and a signal generation section 120.

The motor drive circuit 100 has three output terminals 102. The three output terminals 102 include an output terminal 102u, an output terminal 102v, and an output terminal 102w. The three output terminals 102 output the three-phase output voltage and the three-phase output current to the three-phase motor M. Specifically, the output terminal 102U outputs the U-phase output voltage Vu and the U-phase output current Iu to the three-phase motor M. The output terminal 102V outputs the V-phase output voltage Vv and the V-phase output current Iv to the three-phase motor M. The output terminal 102W outputs the W-phase output voltage Vw and the W-phase output current Iw to the three-phase motor M.

As shown in fig. 2, the motor driving circuit 100 has a first input terminal P, a second input terminal N, a capacitor C, and three series bodies 112. More specifically, in the present embodiment, the motor drive circuit 100 includes an inverter unit 110, and the inverter unit 110 includes a first input terminal P, a second input terminal N, a capacitor C, and three series bodies 112. The inverter section 110 also has a dc voltage source B. The dc voltage source B may be located outside the inverter unit 110.

A first voltage V1 is applied to the first input terminal P. The first input terminal P is connected to a dc voltage source B.

A second voltage V2 is applied to the second input terminal N. The second input terminal N is connected to a dc voltage source B. The second voltage V2 is lower than the first voltage V1.

The capacitor C is connected between the first input terminal P and the second input terminal N.

The three serial bodies 112 are formed by connecting two semiconductor switching elements in series. The semiconductor switching element is, for example, an IGBT (insulated gate bipolar transistor). The semiconductor switching element may be another transistor such as a field effect transistor. The three concatemers 112 include a concatemer 112u, a concatemer 112v, and a concatemer 112w. The three series bodies 112 are connected in parallel with each other. One end of each of the three series bodies 112 is connected to the first input terminal P. The other ends of the three series bodies 112 are connected to the second input terminal N. The rectifying elements D are connected in parallel to the semiconductor switching elements with the first input terminal P side (upper side of the drawing) as a cathode and the second input terminal N side (lower side of the drawing) as an anode, respectively. In the case of using a field effect transistor as the semiconductor switching element, a parasitic diode may be used as the rectifying element.

The three series bodies 112 each have a first semiconductor switching element and a second semiconductor switching element. Specifically, the series body 112u includes a first semiconductor switching element Up and a second semiconductor switching element Un. The series body 112v has a first semiconductor switching element Vp and a second semiconductor switching element Vn. The series body 112w has a first semiconductor switching element Wp and a second semiconductor switching element Wn.

The first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are connected to the first input terminal P. In other words, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are semiconductor switching elements on the high voltage side.

The second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are connected to the second input terminal N. In other words, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are semiconductor switching elements on the low voltage side.

The first semiconductor switching element is connected to the second semiconductor switching element at a connection point 114. Specifically, the first semiconductor switching element Up and the second semiconductor switching element Un are connected at a connection point 114 u. The first semiconductor switching element Vp and the second semiconductor switching element Vn are connected at a connection point 114 v. The first semiconductor switching element Wp and the second semiconductor switching element Wn are connected at a connection point 114 w.

The connection points 114 in each of the three series bodies 112 are connected to the three output terminals 102. Specifically, the connection point 114u in the series body 112u is connected to the output terminal 102 u. Connection point 114v in serial body 112v is connected to output terminal 102 v. The connection point 114w in the series body 112w is connected to the output terminal 102 w.

The first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are input with PWM signals. The PWM signal is output from the signal generating section 120. Hereinafter, in this specification, the PWM signal input to the first semiconductor switching element Up may be referred to as an "upppwm signal". In addition, the PWM signal input to the first semiconductor switching element Vp is sometimes referred to as a "VpPWM signal". The PWM signal input to the first semiconductor switching element Wp is sometimes referred to as a "WpPWM signal". The first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are switched on and off at a prescribed PWM period. For example, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned on when the upppwm signal, the VpPWM signal, and the WpPWM signal are at high levels, respectively. On the other hand, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned off when the upppwm signal, the VpPWM signal, and the WpPWM signal are low, respectively.

The second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are input with PWM signals. The PWM signal is output from the signal generating section 120. Hereinafter, in this specification, the PWM signal input to the second semiconductor switching element Un may be referred to as a "Un PWM signal". The PWM signal input to the second semiconductor switching element Vn may be referred to as a "VnPWM signal". The PWM signal input to the second semiconductor switching element Wn is sometimes referred to as a "WnPWM signal". The second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are switched on and off at a prescribed PWM period. For example, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned on when the Un pwm signal, the VnPWM signal, and the WnPWM signal are at high levels, respectively. On the other hand, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned off when the Un pwm signal, the VnPWM signal, and the WnPWM signal are low, respectively.

As shown in fig. 1, the signal generating unit 120 includes a carrier generating unit 122, a voltage command value generating unit 124, and a comparing unit 126. The signal generating unit 120 is a hardware circuit including a processor such as a CPU (Central Processing Unit: central processing unit), an ASIC (Application Specific Integrated Circuit: application specific integrated circuit), and the like. The processor of the signal generating unit 120 functions as a carrier generating unit 122, a voltage command value generating unit 124, and a comparing unit 126 by executing a computer program stored in a storage device.

The signal generation section 120 controls the inverter section 110. Specifically, the signal generating unit 120 generates a PWM signal and outputs the PWM signal to control the inverter unit 110. More specifically, the signal generating unit 120 generates PWM signals to be input to the three serial bodies 112, respectively.

The carrier generating unit 122 generates a carrier signal. The carrier signal is, for example, a triangular wave. In addition, the carrier signal may be a sawtooth wave.

The voltage command value generation unit 124 generates a voltage command value. The voltage command value corresponds to the voltage value output from the motor drive circuit 100. That is, the voltage command value generation unit 124 generates voltage values corresponding to the output voltage Vu, the output voltage Vv, and the output voltage Vw as voltage command values.

The comparator 126 generates a PWM signal by comparing the carrier signal and the voltage command value.

The PWM signal according to the embodiment of the present invention will be described with reference to fig. 1 to 3. Fig. 3 is a diagram showing PWM signals of an embodiment of the present invention. In fig. 3, a PWM signal of one phase among three-phase PWM signals is shown. In fig. 3, the normal phase PWM period PT is a period during which the normal phase PWM signal PS is output. The inverted PWM period NT is a period during which the inverted PWM signal NS is output. The connection pulse group period AT is a period during which the connection pulse group AS is output. Regarding the current waveform, the contribution of the current ripple caused by the switching of the other phase is ignored, and only the switching ripple component caused by the switching of the phase is extracted for illustration.

As shown in fig. 3, the PWM signal includes a normal phase PWM signal PS and an inverse phase PWM signal NS. The phase of the inverted PWM signal NS is different from the phase of the normal phase PWM signal PS. In the present embodiment, the phase of the inverted PWM signal NS is shifted from the phase of the normal PWM signal PS by 180 degrees.

The signal generating unit 120 generates a PWM signal by comparing the carrier signal CAS and the voltage command value V. The signal generating unit 120 switches the phase of the PWM signal at the phase switching timing tsw. Here, the signal generating unit 120 switches the phase of the PWM signal from the normal phase to the reverse phase at the phase switching timing tsw. That is, the phase of the PWM signal is positive before the phase switching timing tsw. On the other hand, after the phase switching timing tsw, the phase of the PWM signal is inverted. In the present embodiment, the phase switching timing tsw is the timing of the peak of the carrier signal CAS. In the present embodiment, the carrier signal CAS is a triangular wave.

The signal generating unit 120 changes the voltage command value V at the phase switching timing tsw. Here, the signal generating unit 120 changes the voltage command value from V to 1-V. The comparator 126 compares the voltage command value with the carrier signal CAS to generate a PWM signal. Specifically, when the phase of the PWM signal is positive, the PWM signal is turned off when the carrier signal CAS is equal to or higher than the voltage command value. On the other hand, the comparator 126 compares the voltage command value with the carrier signal CAS, and turns on the PWM signal when the carrier signal CAS is smaller than the voltage command value. On the other hand, when the phase of the PWM signal is inverted, the PWM signal is turned on when the carrier signal CAS is equal to or higher than the voltage command value. On the other hand, the comparator 126 compares the voltage command value with the carrier signal CAS, and turns off the PWM signal when the carrier signal CAS is smaller than the voltage command value. In this way, the signal generating unit 120 changes the phase of the PWM signal by changing the voltage command value and the method of the determination processing by the comparing unit 126.

The PWM signal further has a connection pulse group AS between the normal phase PWM signal PS and the reverse phase PWM signal NS before and after the phase switching timing tsw. The connection pulse group AS has a connection on pulse ASon and a connection off pulse ASoff. The connection-on pulse ASon has a connection-on period ATon. The off-connection pulse ASoff has an off-connection period AToff. The connection pulse group AS is located within a time range of 1 PWM period before and after the phase switching timing tsw.

The connection on period ATon is shorter than the on period of 1 cycle of the PWM cycle before or after the phase switching. In the present embodiment, the connection on period ATon is shorter than the on period Ton of 1 period of the PWM period before the phase switching. In detail, the connection on period ATon is a length of 1/2 of the on period Ton of 1 period of the PWM period before the phase switching. I.e., aton=ton/2.

The PWM signal has a connection pulse group AS before and after the phase switching timing tsw between the normal phase PWM signal PS and the reverse phase PWM signal NS. Therefore, the switching of the PWM phase can be suppressed by generating a long on (or off) duration immediately after the switching of the PWM signal phase for one of the phases in the PWM control. As a result, the capacitor ripple current can be reduced while suppressing an undesirable increase or decrease in phase current immediately after switching of the PWM signal phase, which may cause torque irregularities and noise.

The connection pulse group AS is located within 1 PWM period before and after the phase switching timing tsw. Therefore, it is possible to suppress switching of the PWM phase by generating a long on (or off) duration immediately after switching of the PWM signal phase that is liable to generate a long on (or off) duration. As a result, the capacitor ripple current can be reduced while suppressing occurrence of an undesirable increase or decrease in the phase current, which causes torque unevenness and noise.

The off period AToff is shorter than the off period of 1 period of the PWM period before or after the phase switching. Therefore, the capacitor ripple current can be reduced while suppressing occurrence of an undesirable increase or decrease in the phase current, which causes torque unevenness and noise. In the present embodiment, the connection off period AToff is shorter than the off period Toff of 1 period of the PWM period before the phase switching. Specifically, the off period AToff is 1/2 of the off period Toff of 1 period of the PWM period before the phase switching. I.e., atoff=toff/2.

The ratio of the connection on period ATon to the connection off period AToff is the same as the ratio of the on period Ton to the off period Toff of 1 cycle of the PWM cycle before or after the phase switching. Therefore, as shown in the current waveform of fig. 3, the variation in average current before and after the phase switching can be suppressed, and the torque unevenness and noise of the motor can be further suppressed. The ratio of the connection on period ATon to the connection off period AToff may be slightly different from the ratio of the on period Ton to the off period Toff of 1 cycle of the PWM cycle before or after the phase switching.

In addition, the connection off period AToff precedes the connection on period ATon, and the ratio of the off period in the period of the connection pulse group As is the same As the ratio of the off period in the PWM period before the phase switching. The ratio of the on period in the period in which the pulse group AS is connected is the same AS the ratio of the on period in the PWM period after the phase switching. Therefore, AS shown in the current waveform of fig. 3, the current value at the end of the connection pulse group AS period is substantially identical to the current peak before the phase switching. Therefore, the variation in average current before and after the phase switching can be suppressed, and the torque unevenness and noise of the motor can be further suppressed. The ratio of the off period to the period of the connection pulse group AS may be slightly different from the ratio of the off period to the PWM period before the phase switching. The ratio of the on period to the period of the connection pulse group AS may be slightly different from the ratio of the on period to the PWM period after the phase switching.

The period of the connection pulse group AS is 1/2 of the PWM period before or after the phase switching. I.e. at=t/2. Therefore, the variation in average current before and after the phase switching can be suppressed, and the torque unevenness and noise of the motor can be further suppressed.

The connection-on pulse ASon may have a plurality of pulses. Even in the case where the connection on pulse ASon has a plurality of pulses, the capacitor ripple current can be reduced.

The connection disconnection pulse ASoff may have a plurality of pulses. Even in the case where the connection disconnection pulse ASoff has a plurality of pulses, the capacitor ripple current can be reduced.

With the above configuration, even when switching between normal phase PWM and reverse phase PWM is performed in the phase of the switch, fluctuation of average current can be suppressed, and torque unevenness and noise of the motor can be suppressed. Therefore, the following operations can be performed: by applying the inverse PWM to one of the two phases in the switch, the inverse PWM is applied to the rotation angle section in which the ripple current of the capacitor can be suppressed, and by applying the normal phase PWM to the rotation angle section in which the ripple current of the capacitor is deteriorated by generating the reverse current to the capacitor when the inverse PWM is applied, the ripple current of the capacitor is effectively suppressed, the heat generation of the capacitor is suppressed, and the capacitor is reduced in size and cost. At the same time, torque unevenness and noise of the motor accompanying switching between the normal phase PWM and the reverse phase PWM can be suppressed. In the case of a two-phase modulation scheme, for example, a modulation scheme in which a phase to be switched is fixed on and a phase to be switched off are switched every 60 degrees of an electric rotation angle, a current waveform is delayed from a voltage waveform, and thus, when inverse PWM is applied, a rotation angle section in which a capacitor ripple current is deteriorated may occur. Therefore, by switching the PWM phases of the phases in the switching using the present embodiment, the PWM phases of the two phases in which the switching is performed only in such a rotation angle section are the same phase, and thus the capacitor ripple current can be suppressed while suppressing torque unevenness and noise of the motor. In the two-phase modulation scheme, when the phase that is not switched is fixed on only or is fixed off only, the rotation angle section in which the capacitor ripple current decreases when the inverse PWM is applied and the rotation angle section in which the capacitor ripple current deteriorates when the inverse PWM is applied are repeated every 60 degrees of the electric rotation angle. Therefore, by switching the PWM phases of the phases in the switch using the present embodiment, the PWM phases of the two phases that are switched in the rotation angle section of the former are made different, and the PWM phases of the two phases that are switched in the rotation angle section of the latter are made the same phase, so that the capacitor ripple current can be suppressed while suppressing torque unevenness and noise of the motor. The switching time of the normal phase PWM and the reverse phase PWM can be determined based on the zero crossing point of the motor current.

Next, switching of the PWM signal from the reverse phase to the normal phase according to the embodiment of the present invention will be described with reference to fig. 1, 2, and 4. Fig. 4 is a diagram showing PWM signals of an embodiment of the present invention.

As shown in fig. 4, the signal generating unit 120 switches the phase of the PWM signal from the opposite phase to the positive phase at the phase switching timing tsw.

Like the PWM signal shown in fig. 3, the PWM signal has a connection pulse group AS between the normal phase PWM signal PS and the reverse phase PWM signal NS before and after the phase switching timing tsw. Therefore, it is possible to suppress switching of the PWM phase by generating a long on (or off) duration immediately after switching of the PWM signal phase that is liable to generate a long on (or off) duration. As a result, the capacitor ripple current can be reduced while suppressing occurrence of torque unevenness and noise.

The connection on period ATon is 1/2 of the length of the on period Ton of 1 cycle of the PWM cycle before the phase switching. I.e., aton=ton/2.

The off period AToff is 1/2 of the off period Toff of 1 period of the PWM period before the phase switching. I.e., atoff=toff/2.

In addition, the connection on period ATon precedes the connection off period AToff, and the ratio of the on period in the period of the connection pulse group As is the same As the ratio of the on period in the PWM period before the phase switching. The ratio of the off period to the period of the connection pulse group AS is the same AS the ratio of the off period to the PWM period after the phase switching. Therefore, as shown in the current waveform of fig. 4, the variation in average current before and after the phase switching can be suppressed, and the torque unevenness and noise of the motor can be further suppressed. The ratio of the on period to the period of the connection pulse group AS may be slightly different from the ratio of the on period to the PWM period before the phase switching. The ratio of the off period to the period of the connection pulse group AS may be slightly different from the ratio of the off period to the PWM period after the phase switching.

As shown in the current waveform of fig. 4, even when the phase is switched from the reverse phase to the positive phase, the variation in average current before and after the phase switching can be suppressed, and the torque unevenness and noise of the motor can be further suppressed.

In the example described with reference to fig. 3 and 4, the phase switching timing tsw is the timing of the peak of the carrier signal CAS, but the phase switching timing tsw may be shifted from the timing of the peak of the carrier signal CAS.

The PWM signal according to the embodiment of the present invention will be described with reference to fig. 1, 2, and 5. Fig. 5 is a diagram showing PWM signals of the embodiment of the present invention.

AS shown in fig. 5, the PWM signal has a front pulse group BS and a rear pulse group CS in addition to the normal phase PWM signal PS, the reverse phase PWM signal NS, and the connection pulse group AS. The pre-pulse group Bs is located before the connecting pulse group As. The post pulse group CS is located after the connection pulse group AS.

The front pulse group BbS has a front on pulse Bson and a front off pulse BSoff. The front on pulse Bson has a front on period BTon. The pre-off pulse BSoff has a pre-off period BToff. The period of the pre-pulse group BS is the same as that of the previous PWM signal, i.e., the normal phase PWM signal PS in the present embodiment.

The rear pulse group CS has a rear on pulse CSon and a rear off pulse CSoff. The post-on pulse CSon has a post-on period CTon. The post-off pulse CSoff has a post-off period CToff. The period of the post-pulse group CS is the same as that of the post-PWM signal, that is, the inverted PWM signal NS in the present embodiment.

The phase switching timing tsw is delayed from the timing of the peak of the carrier signal CAS by a time t.

The signal generating unit 120 adjusts at least two pulse lengths of the connection pulse group AS, the pre-pulse group BS, and the post-pulse group CS. In the present embodiment, signal generation section 120 adjusts the pulse length of connection pulse group AS and post pulse group CS.

In the present embodiment, the phase switching timing tsw is delayed from the timing of the peak of the carrier signal CAS by the time t. Therefore, the time of the on-state accompanying the switching is delayed by the time t. Accordingly, the signal generating section 120 adjusts the connection on period ATon and the post-on period CTon to compensate for the amount of delay time t. Specifically, the signal generating unit 120 sets the voltage command value shifted from 1 to V as the voltage command value so that the connection on period ATon and the post-on period CTon are each longer by t/2 than when the voltage command value is set to 1 to V. That is, the signal generating unit 120 converts the voltage command value into a pulse length by shifting by a value corresponding to time t/2.

In this case, since the time of switching on is delayed by the time t, the off period AToff is Toff/2+t. I.e., atoff=toff/2+t.

In addition, the connection on period ATon is delayed by t/2 in place of the on delay time t, but is also delayed by off due to the shift of the voltage command value, and thus becomes Ton/2-t/2. I.e. aton=ton/2-t/2.

The time t is shortened by the offset of the voltage command value in the off period CToff, and Toff-t is set. I.e. ctoff=toff-t.

The post-on period Ton is extended by t/2 due to the shift of the voltage command value, and becomes ton+t/2. I.e., cton=ton+t/2.

The signal generating unit 120 adjusts at least two of the connection on period ATon, the front on period BTon, and the rear on period CTon. In the present embodiment, the signal generating unit 120 adjusts the connection on period ATon and the post-on period CTon. The sum of the adjustment value of the connection on period ATon, the adjustment value of the preceding on period BTon, and the adjustment value of the following on period CTon is 0. In the present embodiment, when the adjustment value of the connection on period ATon is set to t1a, the adjustment value of the preceding on period BTon is set to t1b, and the adjustment value of the following on period CTon is set to t1c, t1a= -t/2, t1b=0, and t1c=t/2. Thus, t1a+t1b+t1c=0.

The signal generating unit 120 adjusts at least two of the connection disconnection period AToff, the preceding disconnection period BToff, and the following disconnection period CToff. In the present embodiment, the signal generating unit 120 adjusts the off period AToff and the off period CToff. The sum of the adjustment value of AToff during the connection disconnection, the adjustment value of BToff during the previous disconnection, and the adjustment value of CToff during the subsequent disconnection is 0. When the adjustment value of the off period AToff is set to t2a, the adjustment value of the off period BToff is set to t2b, and the adjustment value of the off period CToff is set to t2c, t2a=t, t2b=0, and t2c= -t. Thus, t2a+t2b+t2c=0.

AS described with reference to fig. 1, 2, and 5, the signal generating unit 120 adjusts the pulse length of at least two of the connection pulse group AS, the front pulse group BS, and the rear pulse group CS. The total time of the on-time and the on-time does not change from the PWM signal shown in fig. 3. Therefore, the variation of the average current associated with the switching operation can be suppressed. In the example shown in fig. 3, the current amplitude is Δi/2 at the instant of the phase switching timing tsw, and the current waveform in the connection pulse group AS period is temporarily shifted to the high side, but in the example shown in fig. 5, the deflection of the current waveform is suppressed. Therefore, the variation of the average current associated with the switching operation can be further suppressed. The value of t is set to, for example, 2% to 10% of the period of the carrier signal CAS, whereby the variation in average current can be effectively suppressed.

Next, switching of the PWM signal from the reverse phase to the normal phase according to the embodiment of the present invention will be described with reference to fig. 1, 2, and 6. Fig. 6 is a diagram showing PWM signals of the embodiment of the present invention.

As shown in fig. 6, the signal generating unit 120 switches the phase of the PWM signal from the opposite phase to the positive phase at the phase switching timing tsw. As in the embodiment shown in fig. 5, the phase switching timing tsw is delayed from the timing of the peak of the carrier signal CAS by a time t.

In the present embodiment, the phase switching timing tsw is delayed from the timing of the peak of the carrier signal CAS by the time t. Therefore, the moment of disconnection accompanying the switching is delayed by a time t. Accordingly, the signal generating section 120 adjusts the connection disconnection period AToff and the post-disconnection period CToff to compensate for the amount of delay time t. Specifically, the signal generating unit 120 sets the value obtained by shifting the voltage command value from V to the voltage command value such that the off-period AToff and the off-period CToff are each longer by t/2 than the case where the voltage command value is set to V.

In this case, since the timing of the disconnection accompanying the switching is delayed by the time t, the connection on period ATon is Ton/2+t. I.e., aton=ton/2+t.

In addition, regarding the off period AToff, instead of the off delay time t, the on is also delayed by t/2 due to the offset of the voltage command value, and thus is Toff/2-t/2. I.e., atoff=toff/2-t/2.

The time t is shortened by the offset of the voltage command value in the post-on period Ton, and Ton-t is set. I.e., ton=ton-t.

The period CToff after the off period is extended by t/2 due to the deviation of the voltage command value, and becomes toff+t/2. I.e., ctoff=toff+t/2.

The signal generating unit 120 adjusts at least two of the connection on period ATon, the front on period BTon, and the rear on period CTon. In the present embodiment, the signal generating unit 120 adjusts the connection on period ATon and the post-on period CTon. The sum of the adjustment value of the connection on period ATon, the adjustment value of the preceding on period BTon, and the adjustment value of the following on period CTon is 0. In the present embodiment, when the adjustment value of the connection on period ATon is set to t1a, the adjustment value of the preceding on period BTon is set to t1b, and the adjustment value of the following on period CTon is set to t1c, t1a=t, t1b=0, and t1c= -t. Thus, t1a+t1b+t1c=0.

The signal generating unit 120 adjusts at least two of the connection disconnection period AToff, the preceding disconnection period BToff, and the following disconnection period CToff. In the present embodiment, the signal generating unit 120 adjusts the off period AToff and the off period CToff. The sum of the adjustment value of AToff during the connection disconnection, the adjustment value of BToff during the previous disconnection, and the adjustment value of CToff during the subsequent disconnection is 0. When the adjustment value of the off period AToff is set to t2a, the adjustment value of the off period BToff is set to t2b, and the adjustment value of the off period CToff is set to t2c, t2a= -t/2, t2b=0, and t2c=t/2. Thus, t2a+t2b+t2c=0.

AS described with reference to fig. 1, 2, and 6, the signal generating unit 120 adjusts the pulse length of at least two of the connection pulse group AS, the front pulse group BS, and the rear pulse group CS. The total time of the on-time and the on-time does not change from the PWM signal shown in fig. 4. Therefore, the variation of the average current associated with the switching operation can be suppressed. In the example shown in fig. 4, the current amplitude is Δi/2 at the instant of the phase switching timing tsw, and the current waveform in the connection pulse group AS period is temporarily shifted to the low side, but in the example shown in fig. 6, the deflection of the current waveform is suppressed. Therefore, the variation of the average current associated with the switching operation can be further suppressed. The value of t is set to, for example, 2% to 10% of the period of the carrier signal CAS, whereby the variation in average current can be effectively suppressed.

In the example described with reference to fig. 5, the signal generating unit 120 shifts the voltage command value by a value corresponding to the time t/2 by converting the voltage command value into the pulse length, but may shift the voltage command value by a value corresponding to the time t by converting the voltage command value into the pulse length.

The PWM signal according to the embodiment of the present invention will be described with reference to fig. 1, 2, and 7. Fig. 7 is a diagram showing PWM signals of the embodiment of the present invention.

In the present embodiment, the phase switching timing tsw is delayed from the timing of the peak of the carrier signal CAS by the time t. Therefore, the time of the on-state accompanying the switching is delayed by the time t. Accordingly, the signal generating section 120 adjusts the connection on period ATon and the post-on period CTon to compensate for the amount of delay time t. Specifically, the signal generating unit 120 sets the voltage command value shifted from 1 to V as the voltage command value such that the connection on period ATon and the post-on period CTon are each longer by t than when the voltage command value is set to 1 to V. That is, the signal generating unit 120 converts the voltage command value into a pulse length by shifting the pulse length by a value corresponding to time t.

Note that, the connection on period ATon is Ton/2 because the off is delayed by t due to the offset of the voltage command value instead of the on delay time t. I.e., aton=ton/2.

In addition, the post-on period Ton is Ton. I.e., cton=ton.

In the present embodiment, the signal generating unit 120 does not adjust the connection on period ATon, the preceding on period BTon, and the following on period CTon.

AS described with reference to fig. 1, 2, and 7, the signal generating unit 120 adjusts the pulse length of at least two of the connection pulse group AS, the front pulse group BS, and the rear pulse group CS. The total time of the on-time and the on-time does not change from the PWM signal shown in fig. 4. Therefore, the variation of the average current associated with the switching operation can be suppressed. In this example, the value of t is set to, for example, 5% to 20% of the period of the carrier signal CAS, whereby the variation in average current can be effectively suppressed.

In the example described with reference to fig. 5 to 7, the signal generating unit 120 adjusts the connection on period ATon and the post-on period CTon to compensate for the amount of delay time t, but the signal generating unit 120 may adjust the pre-on period BTon to compensate for the amount of delay time t.

The PWM signal according to the embodiment of the present invention will be described with reference to fig. 1, 2, and 8. Fig. 8 is a diagram showing PWM signals of the embodiment of the present invention.

In the present embodiment, the phase switching timing tsw is delayed from the timing of the peak of the carrier signal CAS by the time t. Therefore, the time of the on-state accompanying the switching is delayed by the time t. Therefore, the signal generating section 120 adjusts the pre-on period BTon to compensate for the amount of delay time t in advance. Specifically, the signal generating unit 120 sets the voltage command value shifted from V as the voltage command value so that the previous on period BTon is longer by t than the case where the voltage command value is set to V. More specifically, the signal generating unit 120 sets the voltage command value shifted from V to be a value obtained by shifting the on-time of the preceding on-pulse Bson by t/2 and delays the off-time of the preceding on-pulse Bson by t/2. That is, the signal generating unit 120 converts the voltage command value into a pulse length by shifting by a value corresponding to time t/2.

In this case, the pre-off period BToff is shortened by time t/2 due to the shift of the voltage command value, and becomes Toff-t/2. I.e. BToff = Toff-t/2.

Further, since the turn-on is advanced by time t/2 and the turn-off is delayed by time t/2 due to the offset of the voltage command value, the previous turn-on period BTon is ton+t. I.e., bton=ton+t.

Further, since the off-state is delayed by time t/2 and the on-state of the switching is delayed by time t, the off-state period AToff is Toff/2+t/2. I.e., atoff=toff/2+t/2.

In addition, since the turn-on is delayed by time t, the connection turn-on period ATon is Ton/2-t. I.e., aton=ton/2-t.

The signal generating unit 120 adjusts at least two of the connection on period ATon, the front on period BTon, and the rear on period CTon. In the present embodiment, the signal generating unit 120 adjusts the connection on period ATon and the pre-on period BTon. The sum of the adjustment value of the connection on period ATon, the adjustment value of the preceding on period BTon, and the adjustment value of the following on period CTon is 0. In the present embodiment, when the adjustment value of the connection on period ATon is set to t1a, the adjustment value of the preceding on period BTon is set to t1b, and the adjustment value of the following on period CTon is set to t1c, t1a= -t, t1b=t, and t1c=0. Thus, t1a+t1b+t1c=0.

The signal generating unit 120 adjusts at least two of the connection disconnection period AToff, the preceding disconnection period BToff, and the following disconnection period CToff. In the present embodiment, the signal generating unit 120 adjusts the off period AToff and the pre-off period BToff. The sum of the adjustment value of AToff during the connection disconnection, the adjustment value of BToff during the previous disconnection, and the adjustment value of CToff during the subsequent disconnection is 0. When the adjustment value of the off period AToff is set to t2a, the adjustment value of the off period BToff is set to t2b, and the adjustment value of the off period CToff is set to t2c, t2a=t/2, t2b= -t/2, and t2c=0. Thus, t2a+t2b+t2c=0.

AS described with reference to fig. 1, 2, and 8, the signal generating unit 120 adjusts the pulse length of at least two of the connection pulse group AS, the front pulse group BS, and the rear pulse group CS. The total time of the on-time and the on-time does not change from the PWM signal shown in fig. 4. Therefore, the variation of the average current associated with the switching operation can be suppressed.

In the example described with reference to fig. 5 to 8, the phase switching timing tsw is delayed from the timing of the peak of the carrier signal CAS, but the phase switching timing tsw may be earlier than the timing of the peak of the carrier signal CAS.

The PWM signal according to the embodiment of the present invention will be described with reference to fig. 1, 2, and 9. Fig. 9 is a diagram showing PWM signals of the embodiment of the present invention.

In the present embodiment, the phase switching timing tsw is advanced by the time t from the timing of the peak of the carrier signal CAS. Therefore, the timing of the on-state accompanying the switching is advanced by the time t. Therefore, the signal generating unit 120 adjusts the pre-on period BTon to adjust the amount by which the time t is advanced. Specifically, the signal generating unit 120 sets the value obtained by shifting the voltage command value from V as the voltage command value so that the previous on period BTon is shorter by t than the case where the voltage command value is V. More specifically, the signal generating unit 120 sets the voltage command value shifted from V to be a value obtained by shifting the voltage command value by t/2, and advances the time of turning on the previous on pulse Bson by t/2. That is, the signal generating unit 120 converts the voltage command value into a pulse length by shifting by a value corresponding to time t/2.

In this case, since the off period is prolonged by time t/2, the pre-off period BToff is toff+t/2. I.e. btoff=toff+t/2.

Further, since the turn-on is delayed by time t/2 and the turn-off is advanced by time t/2 due to the offset of the voltage command value, the previous turn-on period BTon is Ton-t. I.e., bton=ton-t.

Further, since the off is advanced by time t/2 and the on time of the switching is advanced by time t, the off period AToff is Toff/2-t/2. I.e., atoff=toff/2-t/2.

In addition, since the on is advanced by time t, the connection on period ATon is Ton/2+t. I.e., aton=ton/2+t.

The signal generating unit 120 adjusts at least two of the connection on period ATon, the front on period BTon, and the rear on period CTon. In the present embodiment, the signal generating unit 120 adjusts the connection on period ATon and the pre-on period BTon. The sum of the adjustment value of the connection on period ATon, the adjustment value of the preceding on period BTon, and the adjustment value of the following on period CTon is 0. In the present embodiment, when the adjustment value of the connection on period ATon is set to t1a, the adjustment value of the preceding on period BTon is set to t1b, and the adjustment value of the following on period CTon is set to t1c, t1a=t, t1b= -t, and t1c=0. Thus, t1a+t1b+t1c=0.

The signal generating unit 120 adjusts at least two of the connection disconnection period AToff, the preceding disconnection period BToff, and the following disconnection period CToff. In the present embodiment, the signal generating unit 120 adjusts the off period AToff and the pre-off period BToff. The sum of the adjustment value of AToff during the connection disconnection, the adjustment value of BToff during the previous disconnection, and the adjustment value of CToff during the subsequent disconnection is 0. When the adjustment value of the off period AToff is set to t2a, the adjustment value of the off period BToff is set to t2b, and the adjustment value of the off period CToff is set to t2c, t2a= -t/2, t2b=t/2, and t2c=0. Thus, t2a+t2b+t2c=0.

AS described with reference to fig. 1, 2, and 9, the signal generating unit 120 adjusts the pulse length of at least two of the connection pulse group AS, the front pulse group BS, and the rear pulse group CS. The total time of the on-time and the on-time does not change from the PWM signal shown in fig. 4. Therefore, the variation of the average current associated with the switching operation can be suppressed.

In the example described with reference to fig. 3 to 9, the carrier signal CAS is a triangular wave, but the carrier signal CAS may be a saw tooth.

The PWM signal according to the embodiment of the present invention will be described with reference to fig. 1, 2, and 10. Fig. 10 is a diagram showing PWM signals of the embodiment of the present invention.

As shown in fig. 10, in the present embodiment, the carrier signal CAS is a sawtooth wave. Here, the signal generating unit 120 switches the phase of the PWM signal from the normal phase to the reverse phase at the phase switching timing tsw.

The PWM signal has a normal phase PWM signal PS, an inverse phase PWM signal NS, a connection pulse group AS, a pre-pulse group BS, and a post-pulse group CS.

In order to suppress the variation of the average current accompanying the switching operation of the phase of the PWM signal, it is preferable to match the current Ia at the time of the on-state of the front on pulse Bson and the current Ib at the time of the on-state of the rear on pulse CSon as much as possible. That is, the connection on period ATon is preferably set so that the current decreases by Δi during the period of 2Toff from when the front on pulse Bson is turned off to when the rear on pulse CSon is turned on.

The current increases by Δi if only the on-time Ton is turned on, and decreases by Δi if only the off-time Toff is turned off, so that the connection on-period ATon is preferably set to t=ton+toff, aton=toff×ton/T.

When aton=toff×ton/T, the off period from the front on pulse Bson to the rear on pulse CSon is 2 Toff-aton=toff× (1+toff/T). The current rise during the on period is Δi×aton/ton=Δi·toff/T. The current decrease during off period is Δi×toff× (1+toff/T)/toff=Δi+Δi·toff/T. Therefore, the difference between the current rise in the on period and the current decrease in the off period, that is, the current from the off of the front on pulse Bson to the on of the rear on pulse CSon, decreases to Δi. Therefore, the current Ia at the time of turning on the front on pulse Bson can be made to coincide with the current Ib at the time of turning on the rear on pulse CSon. As a result, the variation of the average current associated with the switching operation of the phase of the PWM signal can be suppressed.

The signal generating unit 120 sets the voltage command value shifted from 1 to V at the phase switching timing tsw so that the connection period ATon becomes toff×ton/T.

Next, switching of the PWM signal from the reverse phase to the normal phase according to the embodiment of the present invention will be described with reference to fig. 1, 2, and 11. Fig. 11 is a diagram showing PWM signals according to an embodiment of the present invention.

As shown in fig. 11, in the present embodiment, the carrier signal CAS is a sawtooth wave. Here, the signal generating unit 120 switches the phase of the PWM signal from the reverse phase to the positive phase at the phase switching timing tsw.

In the present embodiment, the connection on pulse ASon of the connection pulse group AS and the post-on pulse CSon of the post-pulse group CS are connected.

In order to suppress the variation of the average current accompanying the switching operation of the phase of the PWM signal, it is preferable to make the current Ic at the time of the on-state of the front on pulse Bson and the current Id at the time of the on-state of the rear on pulse CSon as uniform as possible. That is, the connection on period ATon is preferably set so that the current decreases by Δi during the period T from when the front on pulse Bson is turned off to when the rear on pulse CSon is turned on.

The current increases by Δi if only the on-time Ton is turned on, and decreases by Δi if only the off-time Toff is turned off, so that it is preferable that the connection on-period ATon be set to t=ton+toff, aton=ton-TonToff/T.

When aton=ton-TonToff/T, the off period from the front on pulse Bson to the rear on pulse CSon is toff+tontoff/T. The current rise during the on period is Δi×aton/ton=Δi—Δi·toff/T. The current reduction during off period is Δi× (toff+tontoff/T)/toff=Δi+Δi·ton/T. Therefore, the difference between the current rise in the on period and the current decrease in the off period, that is, the current from the off of the front on pulse Bson to the on of the rear on pulse CSon, decreases to Δi. Therefore, the current Ic at the time of turning on the front on pulse Bson can be made to coincide with the current Id at the time of turning on the rear on pulse CSon. As a result, the variation of the average current associated with the switching operation of the phase of the PWM signal can be suppressed.

The signal generating unit 120 sets the voltage command value shifted from V at the phase switching timing tsw so that the connection period ATon becomes Ton-TonToff/T.

In the example described with reference to fig. 3 to 11, the voltage command value is changed, but the voltage command value may be constant.

The PWM signal according to the embodiment of the present invention will be described with reference to fig. 1, 2, and 12. Fig. 12 is a diagram showing PWM signals according to an embodiment of the present invention.

As shown in fig. 12, in the present embodiment, the voltage command value is constant. In the present embodiment, the phase of the carrier signal CAS is changed at the phase switching timing tsw. Specifically, at the phase switching timing tsw, the carrier signal CAS is switched from the peak to the trough. Therefore, the comparison processing of the carrier signal CAS and the voltage command value by the comparison unit 126 of the signal generation unit 120 does not need to be switched between the normal phase and the reverse phase. For example, the processing can be performed in both the normal phase and the reverse phase so that the carrier signal is turned off when the carrier signal is larger than the voltage command value and the carrier signal is turned on when the carrier signal is larger than the voltage command value. Therefore, the operation can be simplified in the switching process of the phase of the PWM signal.

In the example described with reference to fig. 12, the phase switching timing tsw may be shifted from the timing of the peak of the carrier signal CAS in the same manner as the examples described with reference to fig. 5 to 9.

In the example described with reference to fig. 3 to 9 and 12, the carrier signal CAS is a triangular wave, and in the example described with reference to fig. 10 and 11, the carrier signal CAS is a saw tooth, but the carrier signal CAS may switch between a triangular wave and a saw tooth at the phase switching timing tsw. For example, the carrier signal CAS may be a triangular wave in the normal phase and a sawtooth wave in the reverse phase. Alternatively, the carrier signal CAS may be a sawtooth wave in the normal phase and a triangular wave in the reverse phase.

The embodiments of the present invention are described above with reference to the drawings (fig. 1 to 12). However, the present invention is not limited to the above-described embodiments, and may be implemented in various forms within a scope not departing from the gist thereof. For ease of understanding, the drawings schematically show the respective components as main components, and the thickness, length, number, and the like of the components are different from those of the actual drawings for convenience of drawing production. The materials, shapes, sizes, and the like of the respective constituent elements shown in the above embodiments are examples, and are not particularly limited, and various modifications can be made within a range substantially not departing from the effects of the present invention.

Description of the reference numerals

100: a motor driving circuit; 112. 112u, 112v, 112w: a concatemer; 120: a signal generating section; 200: a motor module; AS: connecting pulse groups; ASoff: connecting a disconnection pulse; ASon: connecting a switching-on pulse; AToff: during disconnection; ATon: during connection on; BS: a front pulse group; BSoff: a front off pulse; bson: a front on pulse; toff: during the pre-disconnect period; BTon: a front on period; c: a capacitor; CS: a rear pulse group; CSoff: the pulse is disconnected afterwards; CSon: then switching on the pulse; CToff: during the post-off period; CTon: a post-on period; n: a second input terminal; NS: inverting the PWM signal; p: a first input terminal; PS: a positive phase PWM signal; v1: a first voltage; v2: a second voltage; tsw: phase switching timing.

Claims

1. A motor driving circuit controls driving of a three-phase motor in a two-phase modulation manner, wherein,

the motor driving circuit includes:

a first input terminal to which a first voltage is applied;

a second input terminal to which a second voltage lower than the first voltage is applied;

a capacitor connected between the first input terminal and the second input terminal;

three serial bodies formed by connecting two semiconductor switching elements in series; and

A signal generation unit that generates PWM signals to be input to the three serial bodies,

the PWM signals include a positive phase PWM signal and a negative phase PWM signal,

the phase of the inverted PWM signal is different from the phase of the normal phase PWM signal,

the signal generating section switches the phase of the PWM signal at a phase switching timing,

the PWM signal further has a set of connecting pulses between the positive phase PWM signal and the negative phase PWM signal and before and after the phase switching timing,

the connection pulse group has:

a connection-on pulse having a connection-on period; and

a disconnection pulse, which has a connection disconnection period,

the connection on period is shorter than the on period of 1 period of the PWM period before or after the phase switching.

2. The motor driving circuit according to claim 1, wherein,

the connection pulse group is positioned in a time range within 1 period of PWM before and after the phase switching opportunity.

3. The motor drive circuit according to claim 1 or 2, wherein,

the connection-disconnection period is shorter than a disconnection period of 1 cycle of the PWM cycle before or after the phase switching.

4. A motor drive circuit according to any one of claims 1 to 3, wherein,

The ratio of the connection on period to the connection off period is the same as the ratio of the on period to the off period of 1 cycle of the PWM cycle before or after the phase switching.

5. A motor drive circuit according to any one of claims 1 to 3, wherein,

the connection on period precedes the connection off period, and the ratio of the on period in the period of the connection pulse group and the ratio of the on period in the PWM period before phase switching are the same, and the ratio of the off period in the period of the connection pulse group and the ratio of the off period in the PWM period after phase switching are the same.

6. A motor drive circuit according to any one of claims 1 to 3, wherein,

the connection-off period precedes the connection-on period, and the ratio of the off period in the period of the connection pulse group is the same as the ratio of the off period in the PWM period before phase switching, and the ratio of the on period in the period of the connection pulse group is the same as the ratio of the on period in the PWM period after phase switching.

7. The motor drive circuit according to any one of claims 1 to 6, wherein,

the period of the connection pulse group is 1/2 of the PWM period before or after phase switching.

8. The motor drive circuit according to any one of claims 1 to 7, wherein,

the PWM signal further has:

a front pulse group located before the connection pulse group; and

a post-pulse group, located after the connection pulse group,

the pre-pulse group has:

a front on pulse having a front on period; and

a front off pulse, having a front off period,

the post-pulse group has:

a post-on pulse having a post-on period; and

a post-off pulse, having a post-off period,

the signal generating unit adjusts pulse lengths of at least two of the connection pulse group, the pre-pulse group, and the post-pulse group.

9. The motor driving circuit according to claim 8, wherein,

the signal generating section adjusts at least two of the connection on period, the front on period, and the rear on period,

the sum of the adjustment value of the connection on period, the adjustment value of the preceding on period, and the adjustment value of the following on period is 0.

10. The motor drive circuit according to claim 8 or 9, wherein,

the signal generating section adjusts at least two of the connection disconnection period, the front disconnection period, and the rear disconnection period,

the sum of the adjustment value during the connection disconnection, the adjustment value during the preceding disconnection, and the adjustment value during the following disconnection is 0.

11. The motor drive circuit according to any one of claims 1 to 10, wherein,

the connection-on pulse has a plurality of pulses.

12. The motor drive circuit according to any one of claims 1 to 11, wherein,

the disconnection pulse has a plurality of pulses.

13. A motor module, comprising:

the motor drive circuit of any one of claims 1 to 12; and

a three-phase motor driven by the motor driving circuit.