TWI806784B - Power conversion circuit for driving motor and control method thereof - Google Patents

Abstract

A power conversion circuit for driving motor and a control method thereof are provided. The control method includes: comparing a three-phase control command with a control carrier to obtain a PWM signal for driving switches; detecting whether a phase difference between an output voltage and an output current is in a preset phase range; determining whether a zero-sequence voltage is positive or negative according to the output voltage and current if the phase difference is in the preset phase range; injecting the zero-sequence voltage into the three-phase control command to obtain a three-phase synthesizing command and detecting maximum and minimum values of the three-phase synthesizing command after a time period; choosing the maximum value or the minimum value to process a logic phase reversal operation when the zero-sequence voltage is positive or negative; obtaining a three-phase output expectation value after stopping injecting the zero-sequence voltage; and comparing the three-phase output expectation value with the control carrier for regulating a duty ratio of the PWM signal.

Description

Power conversion circuit for driving motor and control method thereof

This case relates to a power conversion circuit and its control method, especially a power conversion circuit for driving a motor and its control method.

In battery-powered motor drive applications, the DC bus (direct current bus) capacitor ripple is determined by the drive's switching combination. In the prior art, the ripple can be reduced by reorganizing the PWM (pulse width modulation, pulse width modulation) switching vector, but the calculation method is complicated and difficult to implement. Another approach is to use AZSVPWM (active zero state space vector pulse width modulation) with zero-sequence injection based on the triangular carrier wave, so as to achieve the effect of redistributing vectors and minimizing capacitor ripple. However, generally speaking, the PWM modules in the microprocessor do not support the inversion of the triangular wave; in addition, even if the triangular carrier is forcibly inverted, the dead time required for switching the upper and lower arms cannot be generated. For this reason, an additional FPGA (field programmable gate array) must be added outside the microprocessor for special PWM processing, thereby inverting the carrier and introducing dead time. Furthermore, the inversion of the triangular carrier will generate additional switching, which will increase the switching frequency of the switches at high speeds in traction motor applications.

Therefore, how to develop a power conversion circuit for driving a motor and a control method thereof that can improve the above-mentioned conventional technology is an urgent need at present.

The purpose of this case is to provide a power conversion circuit for driving a motor and its control method, which realizes vector reconfiguration by inverting judgment logic instead of carrier. In this way, the capacitor ripple can be effectively reduced, thereby reducing the temperature rise of the capacitor to prolong the life of the capacitor, while reducing the driving loss of the motor and improving the driving efficiency. Furthermore, the control method of this application can be implemented to realize PWM regulation only through an existing controller (such as a microprocessor), and no external hardware (such as FPGA) is required for PWM processing.

To achieve the above purpose, this project provides a control method for a power conversion circuit, including: comparing the three-phase control command and the control carrier to obtain a pulse width modulation signal; providing a pulse width modulation signal to drive multiple switches in the power conversion circuit , so that multiple switches switch the input power to generate a three-phase output power; detect whether the phase difference between the voltage and current of the three-phase output power falls within the predetermined phase range; if it is detected that the phase difference falls within the predetermined phase range, then according to the three-phase The voltage and current of the output power supply determine whether the zero-sequence voltage is positive or negative; inject zero-sequence voltage into the three-phase control command to obtain the three-phase composite command, and detect the maximum voltage value and The minimum voltage value; according to the zero-sequence voltage being determined as positive or negative voltage, select the maximum voltage value or the minimum voltage value for logic inversion operation; after completing the logic inversion operation and stopping the injection of zero-sequence voltage, the expected value of the three-phase output is obtained; And compare the expected value of the three-phase output and control the carrier to adjust the duty cycle of the PWM signal.

In order to achieve the above purpose, the present application further provides a power conversion circuit for driving a motor, including a plurality of switch groups, DC row capacitors and a controller. Each switch group includes an upper-bridge transistor and a lower-bridge transistor, and the first ends of each upper-bridge transistor are electrically connected to each other, and the second ends of each lower-bridge transistor are electrically connected to each other. In each switch group, the second end of the upper bridge transistor is electrically connected to the first end of the lower bridge transistor. The DC row capacitor is used to receive input power, wherein the first end of the DC row capacitor is electrically connected to the first end of each high-bridge transistor, and the second end of the DC row capacitor is electrically connected to the second end of each low-bridge transistor. The controller compares the three-phase control command and the control carrier to obtain multiple pulse width modulation signals. Each switch group correspondingly receives one of the pulse width modulation signals, and in each switch group, according to the corresponding received pulse width modulation signal, the upper bridge transistor is selectively turned on or off, and the lower bridge transistor Selectively cut off or on, so that multiple switch groups switch the input power to generate three-phase output power to drive the motor. If the controller detects that the phase difference between the voltage and current of the three-phase output power supply does not fall within the predetermined phase range, the controller detects the minimum control voltage in the three-phase control command, and the controller performs a logic inversion operation on the minimum control voltage, Get the three-phase output command. The controller compares the three-phase output commands and controls the carrier to adjust the duty cycle of each PWM signal.

Some typical embodiments embodying the features and advantages of the present application will be described in detail in the description in the following paragraphs. It should be understood that this case can have various changes in different aspects without departing from the scope of this case, and the descriptions and diagrams therein are used as illustrations in nature, not to limit this case.

Figure 1 is a schematic diagram of the circuit structure of a power conversion circuit according to an embodiment of the present invention. As shown in FIG. 1 , the power conversion circuit 1 is used to drive the motor 2 , and the power conversion circuit 1 includes a plurality of switch groups 11 (three switch groups 11 are illustrated in FIG. 1 ), a DC capacitor Cdc and a controller 12 . Each switch group 11 includes an upper bridge transistor and a lower bridge transistor, and the first ends of each upper bridge transistor are electrically connected to each other, and the second ends of each lower bridge transistor are electrically connected to each other, wherein in each switch group In 11, the second end of the upper bridge transistor is electrically connected to the first end of the lower bridge transistor. In the embodiment shown in Figure 1, the first switch group 11 includes the upper bridge transistor Sup and the lower bridge transistor Sun, the second switch group 11 includes the upper bridge transistor Svp and the lower bridge transistor Svn, and the third switch group 11 includes the upper bridge transistor Svp and the lower bridge transistor Svn. A switch group 11 includes an upper bridge transistor Swp and a lower bridge transistor Swn, wherein the first ends of the upper bridge transistors Sup, Svp and Swp are electrically connected to each other, and the second ends of the lower bridge transistors Sun, Svn and Swn are connected to each other Electrically connected, the second ends of the upper bridge transistors Sup, Svp and Swp are respectively electrically connected to the first ends of the lower bridge transistors Sun, Svn and Swn.

The DC row capacitor Cdc is used to receive the input power Vin, wherein the first end of the DC row capacitor Cdc is electrically connected to the first end of each high-bridge transistor (Sup, Svp, and Swp), and the second end of the DC row capacitor Cdc is electrically connected to the first end of the DC row capacitor Cdc. Connect to the second terminal of each lower bridge transistor (Sun, Svn and Swn).

The controller 12 compares the three-phase control command and the control carrier to obtain a plurality of PWM signals. Each switch group 11 correspondingly receives a pulse width modulation signal, and in each switch group 11, according to the corresponding received pulse width modulation signal, the upper bridge transistor is selectively turned on or off, and the lower bridge transistor is selectively turned on or off. Selectively cut off or on, so that all switch groups 11 switch the input power Vin to generate three-phase output power to drive the motor 2 . The three-phase output power supply includes three output phases u, v, and w, and the currents in the three output phases u, v, and w are respectively Iu, Iv, and Iw. In addition, the three-phase control command includes three output phases u, v And the voltage command of w.

Please refer to FIG. 1 and FIG. 2 , wherein FIG. 2 is a schematic flowchart of a control method for a power conversion circuit according to an embodiment of the present case. In this case, the controller 12 in FIG. 1 is used to implement the control method in FIG. 2 to realize the control of the power conversion circuit 1 . As shown in Figure 1 and Figure 2, first, in step S1, compare the three-phase control command and the control carrier, obtain the pulse width modulation signal, and provide the pulse width modulation signal to drive all the switches in the power conversion circuit 1 , allowing all switches to switch the input power supply Vin to generate a three-phase output power supply, wherein the switches in the power conversion circuit 1 include the upper bridge transistors (Sup, Svp and Swp) and the lower bridge transistors (Sun, Svn and Swp) in all switch groups 11 Swn). Next, in step S2, it is detected whether the phase difference between the voltage and current of the three-phase output power falls within a predetermined phase range, wherein the predetermined phase range is between -30° to +30° or between 150° to 210° better. If it is detected in step S2 that the phase difference falls within a predetermined phase range, then step S3 is executed. In step S3, the zero-sequence voltage is determined to be positive or negative according to the voltage and current of the three-phase output power supply, and the zero-sequence voltage is injected into the three-phase control command to obtain the three-phase synthesis command, and three phases are detected after a period of time. The maximum voltage value and the minimum voltage value in the composite command. Then, according to whether the zero-sequence voltage is determined as a positive voltage or a negative voltage, the maximum voltage value or the minimum voltage value in the three-phase synthesis command is selected to perform a logic inversion operation. Specifically, if it is determined in step S3 that the zero-sequence voltage is a positive voltage, then step S4 is executed to select the maximum voltage value in the three-phase synthesis command for logic inversion operation; otherwise, if it is determined in step S3 that the zero-sequence voltage is Negative voltage, then execute step S5 to select the minimum voltage value in the three-phase synthesis command to perform logic inversion operation. Finally, in step S6, after the logic inversion operation is completed and zero-sequence voltage injection is stopped, the three-phase output expected value is obtained, and the three-phase output expected value is compared with the control carrier to adjust the duty ratio of the PWM signal.

In addition, if it is detected in step S2 that the phase difference does not fall within the predetermined phase range, then step S7 is executed. In step S7, the minimum control voltage in the three-phase control commands is detected, and a logic inversion operation is performed on the minimum control voltage. Then, in step S8, after completing the logic inversion operation on the minimum control voltage, the three-phase output command is obtained, and the three-phase output command and the control carrier are compared to adjust the duty cycle of the PWM signal.

From the above, it can be seen that the power conversion circuit 1 for driving the motor 2 and its control method in this case achieve vector reconfiguration by reversing the judgment logic instead of the carrier. Thereby, capacitor ripple can be effectively reduced, thereby reducing the temperature rise of the DC row capacitor Cdc to prolong the life of the DC row capacitor Cdc, while reducing the driving loss of the motor 2 and improving the driving efficiency. Furthermore, only the existing controller 12 (such as a microprocessor) can implement the control method of the present application to realize PWM regulation, without additional hardware (such as FPGA) for PWM processing.

The control method used in the power conversion circuit 1 in this case will be described in detail below with an example. It should be noted that the control methods described below are all executed by the controller 12 of the power conversion circuit 1 .

(1) 其中，

為完成邏輯反相運算後的電壓命令。在翻轉後所採用的判斷邏輯N中，若電壓命令

大於控制載波，則切換脈寬調變訊號為低電壓準位，即控制訊號PWM_H為低電壓準位，反之，若電壓命令

小於控制載波，則切換脈寬調變訊號為高電壓準位，即控制訊號PWM_H為高電壓準位。須注意的是，若電壓命令經過邏輯反相運算，則其對應之判斷邏輯亦隨之翻轉，反之，若電壓命令未經邏輯反相運算，則其對應之判斷邏輯則維持不變。 Taking any output phase as an example, Figure 3 is a schematic diagram of the waveform when the control carrier is reversed, and Figure 4 is a schematic diagram of the waveform when the judgment logic is reversed. In Figure 3 and Figure 4, the control carrier is a triangle wave, V* is a voltage command, PWM_H and PWM_L are the control signals of the upper bridge transistor and the lower bridge transistor in the corresponding switch group 11 (included in the pulse width modulated signal). It should be noted that V* can be a voltage command of any output phase u, v or w in the three-phase control commands. In Figure 3, the waveform of the control carrier is reversed, and before and after the reversal, the judgment logic P is used to determine whether the PWM signal is a high voltage level or a low voltage level according to the comparison result of the voltage command V* and the control carrier bit. In the judgment logic P, if the voltage command V* is greater than the control carrier, the pulse width modulation signal is switched to a high voltage level, that is, the control signal PWM_H is a high voltage level; otherwise, if the voltage command V* is smaller than the control carrier, then The PWM signal is switched to a low voltage level, that is, the control signal PWM_H is a low voltage level. In Figure 4, it is the inversion judgment logic and the voltage command V*. Before and after the inversion, the judgment logic P and the judgment logic N are respectively used to determine whether the pulse width modulation signal is a high voltage level or a low voltage level, and when the inversion Perform logic inversion operation on the voltage command V*. The judgment logic P used before inversion is the same as the above, so it will not be repeated. When inverting, the voltage command V* is logically inverted according to the logic inversion relational expression, where the logical inversion relational expression is:

(1) where,

It is the voltage command after the logical inversion operation is completed. In the judgment logic N adopted after inversion, if the voltage command

If it is greater than the control carrier, switch the PWM signal to a low voltage level, that is, the control signal PWM_H is a low voltage level. On the contrary, if the voltage command

If it is less than the control carrier, the PWM signal is switched to a high voltage level, that is, the control signal PWM_H is a high voltage level. It should be noted that if the voltage command undergoes a logic inversion operation, the corresponding judgment logic will also be reversed. On the contrary, if the voltage command has not been logic inversion operation, the corresponding judgment logic will remain unchanged.

As shown in Fig. 3 and Fig. 4, the PWM signal is the same regardless of whether the control carrier is inverted or the judgment logic is inverted. It should be noted that the control signal PWM_L of the low-bridge transistor is approximately complementary to the control signal PWM_H of the high-bridge transistor. There is a dead time between them, and when flipping, the upper bridge transistor and the lower bridge transistor are switched synchronously without dead time.

When the phase difference between the voltage and current of the three-phase output power supply does not fall into the predetermined phase range, then detect the minimum control voltage in the three-phase control command (that is, the voltage command of the three output phases u, v and w minimum value). According to the logical inversion relation shown in equation (1), the minimum control voltage is logically inverted, and the voltage commands in the other two output phases remain unchanged, so as to obtain the three-phase output command. Specifically, the three-phase output command includes the minimum control voltage after logic inversion operation, and the three-phase output command also includes voltage commands in the other two output phases. Then, by comparing the three-phase output command and the control carrier, the duty ratio of the PWM signal is adjusted, wherein the minimum control voltage and the control carrier after the logic inversion operation are compared based on the judgment logic N, and based on the judgment Logic P to compare the voltage command and control carrier of the remaining two output phases.

。最後，於時刻t3停止注入零序電壓，且在時刻t3至t4期間，基於判斷邏輯N，比較未被注入零序電壓的電壓命令

及控制載波，來調節對應開關組11中之脈寬調變訊號的占空比。需注意的是，於第5圖之示例中，時刻t1至t2期間以及時刻t2至t3期間分別具有一個週期的控制載波，然實際上並不以此為限，時刻t1至t2期間以及時刻t2至t3期間可分別具有多個週期的控制載波。 In addition, when the phase difference between the voltage and current of the three-phase output power supply falls within the predetermined phase range, this case injects zero-sequence voltage into the three-phase control command to avoid the influence caused by the absence of dead time during inversion. circuit reliability. Figure 5 is a schematic diagram of the waveform when zero-sequence voltage is injected into the three-phase control command, and in the example in Figure 5, the zero-sequence voltage is a positive voltage, and shows the largest voltage command among the three-phase control commands as an example . As shown in FIG. 5, at time t1, a zero-sequence voltage is injected into the voltage command V*. When the zero-sequence voltage is a positive voltage, the magnitude of the zero-sequence voltage is equal to the difference between the maximum voltage command V* and the peak value of the control carrier wave. Conversely, when the zero-sequence voltage is a negative voltage, the magnitude of the zero-sequence voltage is equal to the difference between the minimum voltage command and the valley value of the control carrier. Then, at time t2, the judgment logic P is reversed to judgment logic N, and the voltage command V* is logically inverted according to the logic inversion relation shown in equation (1) to obtain the voltage command

. Finally, stop injecting the zero-sequence voltage at time t3, and during the period from time t3 to t4, based on the judgment logic N, compare the voltage command that has not been injected with zero-sequence voltage

And control the carrier to adjust the duty ratio of the pulse width modulation signal in the corresponding switch group 11. It should be noted that, in the example shown in FIG. 5 , there is one period of control carrier wave during the period from time t1 to t2 and the period from time t2 to t3 respectively, but it is not limited to this in practice. There may be multiple cycles of control carriers during the period to t3 respectively.

維持等於控制載波的波谷值，故基於判斷邏輯N，上橋電晶體的控制訊號PWM_H持續處於高電壓準位，下橋電晶體的控制訊號PWM_L持續處於低電壓準位。因此，於時刻t2，即在翻轉邏輯和進行邏輯反相運算時，上橋電晶體及下橋電晶體均不會進行切換。藉此，可避免在翻轉邏輯時因上橋電晶體及下橋電晶體同步切換 (即不存在死區時間) 而影響電路可靠性。於一些實施例中，在對三相控制命令注入零序電壓前，調整脈寬調變訊號的占空比為100%或0%。 It can be seen from Figure 5 that during the period from time t1 to t2, the voltage command V* injected into the zero-sequence voltage remains equal to the peak value of the control carrier, so based on the judgment logic P, the control signal PWM_H of the high-bridge transistor is continuously at high Voltage level, the control signal PWM_L of the lower bridge transistor is continuously at the low voltage level. During the period from time t2 to t3, the voltage command injected into the zero-sequence voltage

Keep equal to the valley value of the control carrier, so based on the judgment logic N, the control signal PWM_H of the high-bridge transistor is continuously at the high voltage level, and the control signal PWM_L of the low-bridge transistor is continuously at the low voltage level. Therefore, at time t2, that is, when inverting logic and performing logic inversion operations, neither the high-bridge transistor nor the low-bridge transistor will switch. In this way, it is possible to avoid affecting the reliability of the circuit due to synchronous switching of the high-bridge transistor and the low-bridge transistor (that is, there is no dead time) when the logic is flipped. In some embodiments, before injecting the zero-sequence voltage into the three-phase control command, the duty cycle of the PWM signal is adjusted to 100% or 0%.

The following figure 6 illustrates how to determine whether the zero-sequence voltage is positive or negative according to the voltage and current of the three-phase output power supply.

Fig. 6 is a schematic diagram of the voltage and current waveforms of the three-phase output power supply. In Fig. 6, the phase difference between voltage and current falls within a predetermined phase range, and Vu, Vv, and Vw are voltages of three output phases u, v, and w in a three-phase output power supply, respectively, and are represented by solid lines, Dashed lines and dotted lines indicate the waveforms of the voltages Vu, Vv and Vw. Iu, Iv, and Iw are the currents of the three output phases u, v, and w in the three-phase output power supply, respectively, and the waveforms of the currents Iu, Iv, and Iw are marked by solid lines, dashed lines, and dotted lines, respectively. The "+" or "-" marked next to the waveform represents the use of judgment logic P or judgment logic N respectively. In each voltage section I, II, III, IV, V and VI, the range of the voltage phase angle is different, as shown in Table 1. In each current section A, B, C, D, E, and F, the positive and negative relationships of the currents Iu, Iv, and Iw are different, as shown in Table 2.

Table 1: voltage range Voltage phase angle (degrees) I 0~60 II 60~120 III 120~180 IV 180~240 V 240~300 VI 300~360

Table 2: current section Iu IV Iw A >0 <0 <0 B >0 >0 <0 C <0 >0 <0 D. <0 >0 >0 E. <0 <0 >0 f >0 <0 >0

After knowing the voltage and current section of the current three-phase output power supply through Table 1 and Table 2, you can determine whether the zero-sequence voltage is a positive voltage or a negative voltage according to Table 3. In Table 3, Vz+ means that the zero-sequence voltage is a positive voltage, Vz- means that the zero-sequence voltage is a negative voltage, and Vz0 means that the zero-sequence voltage can be arbitrarily selected as a positive voltage or a negative voltage.

table 3: Zero sequence voltage current section A B C D. E. f voltage range I Vz+ Vz- Vz0 Vz+ Vz- Vz0 II Vz0 Vz- Vz+ Vz0 Vz- Vz+ III Vz- Vz0 Vz+ Vz- Vz0 Vz+ IV Vz- Vz+ Vz0 Vz- Vz+ Vz0 V Vz0 Vz+ Vz- Vz0 Vz+ Vz- VI Vz+ Vz0 Vz- Vz+ Vz0 Vz-

Ideally, the voltages Vu, Vv, and Vw and the currents Iu, Iv, and Iw are consistent with the voltage commands and current commands of each phase in the three-phase control commands, so in some embodiments, the zero-sequence voltage can also be determined by the voltage and current commands be positive or negative voltage.

Figure 7 illustrates the waveform change of the zero-sequence voltage injected into the three-phase control command. In Fig. 7, the three-phase control command includes the voltage commands Vu*, Vv* and Vw* of the three output phases u, v and w, and the maximum value, intermediate value and minimum value in the three-phase control command are sequentially Voltage commands Vu*, Vv* and Vw*. Furthermore, in Fig. 7, the peaks and troughs of the control carrier are illustrated by solid lines and broken lines, respectively. In some embodiments, after the zero-sequence voltage is determined to be a positive voltage, the maximum value of the three-phase control commands (ie, the voltage command Vu*) is detected, and the peak value of the control carrier in the switching period is detected. Next, calculate the first voltage difference between the peak value of the wave and the maximum value of the three-phase control command, and the first voltage difference is the voltage value of the positive voltage (ie, the voltage value of the zero-sequence voltage). Finally, the three-phase control command and the voltage value of the positive voltage are superimposed to form a three-phase composite command. In another embodiment, after the zero-sequence voltage is determined to be a negative voltage, the minimum value of the three-phase control commands (ie, the voltage command Vw*) is detected, and the valley value of the control carrier in the switching cycle is detected. Then, calculate the second voltage difference between the valley value and the minimum value of the three-phase control command, and the second voltage difference is the voltage value of the negative voltage (ie, the voltage value of the zero-sequence voltage). Finally, the three-phase control command and the voltage value of the negative voltage are superimposed to form a three-phase synthesis command.

為對電壓命令Vu*進行邏輯反相運算後所獲得的電壓命令，PWM_u、PWM_v及PWM_w分別為輸出相u、v及w所對應之開關組11的上橋電晶體Sup、Svp及Swp的控制訊號。於第8圖中，以實線標示電壓命令Vu*及

的波形，以虛線標示電壓命令Vv*的波形，以點鏈線標示電壓命令Vw*的波形。如第8圖所示，在三相輸出電源的電壓及電流之間的相位差落入預定相位範圍的情況下，於時刻t1，對三相控制命令 (包含電壓命令Vu*、Vv*及Vw*) 注入零序電壓，於此實施例中，零序電壓為正電壓。被注入零序電壓後的電壓命令Vu*、Vv*及Vw*形成三相合成命令。經過一時間週期後 (即時刻t1至t2之時間段)，檢測三相合成命令中的最大電壓值及最小電壓值，於此實施例中，三相合成命令中的最大電壓值及最小電壓值分別為被注入零序電壓的電壓命令Vu*及Vw*。因零序電壓為正電壓，故於時刻t2選擇三相合成命令中的最大電壓值 (即電壓命令Vu*)，並依據等式 (1) 所示之邏輯反相關係式對最大電壓值進行邏輯反相運算而獲得電壓命令

。於時刻t3，停止注入零序電壓，此時電壓命令

等同於對未被注入零序電壓之電壓命令Vu*進行邏輯反相運算所得之電壓命令。再者，於停止注入零序電壓後，電壓命令

、Vv*及Vw*形成三相輸出期望值。最後，通過比較三相輸出期望值及控制載波，來調節脈寬調變訊號 (即控制訊號PWM_u、PWM_v及PWM_w) 的占空比。 Figure 8 illustrates the waveforms of the PWM signals of each output phase when zero-sequence voltage is injected into the three-phase control command. In the embodiment shown in Figure 8, where

It is the voltage command obtained after performing logic inversion operation on the voltage command Vu*, PWM_u, PWM_v and PWM_w are respectively the control of the upper bridge transistor Sup, Svp and Swp of the switch group 11 corresponding to the output phase u, v and w signal. In Figure 8, the voltage command Vu* and

The waveform of the voltage command Vv* is marked with a dotted line, and the waveform of the voltage command Vw* is marked with a chain line of dots. As shown in Fig. 8, when the phase difference between the voltage and current of the three-phase output power supply falls within the predetermined phase range, at time t1, the three-phase control commands (including voltage commands Vu*, Vv* and Vw *) Inject the zero sequence voltage, in this example, the zero sequence voltage is a positive voltage. The voltage commands Vu*, Vv* and Vw* injected into the zero-sequence voltage form a three-phase composite command. After a period of time (i.e. the time period from time t1 to t2), the maximum voltage value and the minimum voltage value in the three-phase composite command are detected. In this embodiment, the maximum voltage value and the minimum voltage value in the three-phase composite command are the voltage commands Vu* and Vw* injected into the zero-sequence voltage, respectively. Since the zero-sequence voltage is a positive voltage, the maximum voltage value in the three-phase synthesis command (that is, the voltage command Vu*) is selected at time t2, and the maximum voltage value is calculated according to the logical inverse relationship shown in equation (1). The voltage command is obtained by logical inversion operation

. At time t3, stop injecting zero-sequence voltage, at this time the voltage command

It is equivalent to the voltage command obtained by logically inverting the voltage command Vu* that has not been injected with zero-sequence voltage. Furthermore, after stopping the injection of zero-sequence voltage, the voltage command

, Vv* and Vw* form a three-phase output expectation. Finally, the duty cycle of the PWM signal (ie, the control signals PWM_u, PWM_v and PWM_w) is adjusted by comparing the expected value of the three-phase output with the control carrier.

及控制載波來決定控制訊號PWM_u之波形。另外，若電壓命令未經邏輯反相運算，則其對應之判斷邏輯則維持不變。因此，對於輸出相v及w而言，由於其電壓命令Vv*及Vw*均未經邏輯反相運算，故於時刻t0至t4，始終基於判斷邏輯P比較電壓命令Vv*及Vw*與控制載波來決定控制訊號PWM_v及PWM_w之波形。 It should be noted that at any point in time, the current voltage command is compared with the control carrier according to the current judgment logic, so as to determine whether the PWM signal is a high voltage level or a low voltage level according to the comparison result. In the embodiment shown in FIG. 8, since the logic inversion operation is performed on the voltage command Vu* corresponding to the output phase u at time t2, the judgment logic one corresponding to the output phase u is reversed from the judgment logic P to the judgment logic N, so During the period from time t0 to t2, the waveform of the control signal PWM_u is determined based on the judgment logic P comparing the voltage command Vu* and the control carrier, and during the period from time t2 to t4, based on the judgment logic N comparing the voltage command

And control the carrier to determine the waveform of the control signal PWM_u. In addition, if the voltage command has not been logically inverted, its corresponding judgment logic remains unchanged. Therefore, for the output phases v and w, since the voltage commands Vv* and Vw* have not been logically inverted, from time t0 to t4, the voltage commands Vv* and Vw* are always compared with the control based on the judgment logic P The carrier wave determines the waveforms of the control signals PWM_v and PWM_w.

Specifically, during the period from time t0 to t1, the three-phase control command is compared with the control carrier based on the judgment logic P. If the three-phase control command is greater than the control carrier, the PWM signal is switched to a high voltage level. If When the three-phase control command is smaller than the control carrier, the PWM signal is switched to a low voltage level. Take the output phase u as an example, if the voltage command Vu* in the three-phase control command is greater than the control carrier, then switch the control signal PWM_u in the pulse width modulation signal to a high voltage level, if the voltage command in the three-phase control command When Vu* is smaller than the control carrier, the control signal PWM_u in the pulse width modulation signal is switched to a low voltage level. The method of determining the waveform of the PWM signal during the period from time t1 to t2 is similar to that during the period from time t0 to t1 , so it will not be repeated here.

以及未經由邏輯反相運算取得之電壓命令Vv*及Vw*。因此，基於判斷邏輯N對電壓命令

與控制載波進行比較，如果電壓命令

大於控制載波時，則切換脈寬調變訊號中之控制訊號PWM_u為低電壓準位，如果電壓命令

小於控制載波時，則切換脈寬調變訊號中之控制訊號PWM_u為高電壓準位。此外，基於判斷邏輯P對電壓命令Vv與控制載波進行比較，如果電壓命令Vv*大於控制載波時，則切換脈寬調變訊號中之控制訊號PWM_v為高電壓準位，如果電壓命令Vv*小於控制載波時，則切換脈寬調變訊號中之控制訊號PWM_v為低電壓準位。再者，基於判斷邏輯P對電壓命令Vw*與控制載波進行比較，如果電壓命令Vw*大於控制載波時，則切換脈寬調變訊號中之控制訊號PWM_w為高電壓準位，如果電壓命令Vw*小於控制載波時，則切換脈寬調變訊號中之控制訊號PWM_w為低電壓準位。時刻t2至t3期間決定脈寬調變訊號之波形的方式與時刻t3至t4期間相似，故於此不再贅述。 During the period from time t3 to t4, the expected value of three-phase output includes the voltage command obtained through logic inversion operation

And voltage commands Vv* and Vw* obtained without logic inversion operation. Therefore, based on the judgment logic N for the voltage command

compared with the control carrier, if the voltage command

When it is greater than the control carrier, switch the control signal PWM_u in the pulse width modulation signal to a low voltage level. If the voltage command

When it is less than the control carrier, the control signal PWM_u in the pulse width modulation signal is switched to a high voltage level. In addition, based on the judgment logic P, the voltage command Vv is compared with the control carrier. If the voltage command Vv* is greater than the control carrier, the control signal PWM_v in the pulse width modulation signal is switched to a high voltage level. If the voltage command Vv* is less than When controlling the carrier, switch the control signal PWM_v in the pulse width modulation signal to a low voltage level. Furthermore, based on the judgment logic P, the voltage command Vw* is compared with the control carrier. If the voltage command Vw* is greater than the control carrier, the control signal PWM_w in the pulse width modulation signal is switched to a high voltage level. If the voltage command Vw *When it is less than the control carrier, switch the control signal PWM_w in the pulse width modulation signal to a low voltage level. The manner of determining the waveform of the PWM signal during the period from time t2 to t3 is similar to that during the period from time t3 to t4 , so it will not be repeated here.

To sum up, this case provides a power conversion circuit for driving a motor and its control method, which achieves vector reconfiguration by inverting judgment logic instead of carrier. In this way, the capacitor ripple can be effectively reduced, thereby reducing the temperature rise of the capacitor to prolong the life of the capacitor, while reducing the driving loss of the motor and improving the driving efficiency. Furthermore, the control method of this application can be implemented to realize PWM regulation only through an existing controller (such as a microprocessor), and no external hardware (such as FPGA) is required for PWM processing.

It should be noted that the above is only a preferred embodiment proposed to illustrate this case, and this case is not limited to the described embodiment, and the scope of this case is determined by the scope of the attached patent application. Moreover, this case can be modified in various ways by the people who are familiar with this technology with Shi Jiang's thinking, but all of them will not break away from the desired protection of the scope of the attached patent application.

:邏輯反相運算後的電壓命令 t0、t1、t2、t3、t4:時刻 Vu、Vv、Vw:電壓 I、II、III、IV、V、VI:電壓區段 A、B、C、D、E、F:電流區段 Vu*、Vv*、Vw*:電壓命令

:邏輯反相運算後的電壓命令 PWM_u、PWM_v、PWM_w:控制訊號 S1、S2、S3、S4、S5、S6、S7、S8:步驟1: Power conversion circuit 2: Motor 11: Switch group Cdc: DC row capacitor 12: Controller Sup, Svp, Swp: Upper bridge transistors Sun, Svn, Swn: Lower bridge transistors Vin: Input power supply Iu, Iv, Iw : current V*: voltage command PWM_H, PWM_L: control signal

: Voltage command after logic inversion operation t0, t1, t2, t3, t4: Time Vu, Vv, Vw: Voltage I, II, III, IV, V, VI: Voltage section A, B, C, D, E, F: current section Vu*, Vv*, Vw*: voltage command

: Voltage commands PWM_u, PWM_v, PWM_w after logic inversion operation: Control signals S1, S2, S3, S4, S5, S6, S7, S8: Steps

Figure 1 is a schematic diagram of the circuit structure of a power conversion circuit according to an embodiment of the present invention.

FIG. 2 is a schematic flowchart of a control method for a power conversion circuit according to an embodiment of the present invention.

Figure 3 is a schematic diagram of the waveform when inverting the control carrier.

Figure 4 is a schematic diagram of the waveform when the judgment logic is reversed.

FIG. 5 is an example of a waveform diagram when zero-sequence voltage is injected into a three-phase control command.

Fig. 6 is a schematic diagram of the voltage and current waveforms of the three-phase output power supply.

Figure 7 illustrates the waveform changes when zero-sequence voltage is injected into the three-phase control command.

Figure 8 illustrates the waveforms of the PWM signals of each output phase when zero-sequence voltage is injected into the three-phase control command.

S1, S2, S3, S4, S5, S6, S7, S8: steps

Claims (15)

A control method for a power conversion circuit, comprising: Comparing a three-phase control command with a control carrier to obtain a pulse width modulation signal; Providing the pulse width modulation signal to drive a plurality of switches in the power conversion circuit, so that the plurality of switches switch an input power supply to generate a three-phase output power supply; Detecting whether the phase difference between the voltage and current of the three-phase output power falls within a predetermined phase range; If it is detected that the phase difference falls within the predetermined phase range, then determining a zero-sequence voltage as a positive voltage or a negative voltage according to the voltage and the current of the three-phase output power supply; Injecting the zero-sequence voltage into the three-phase control command to obtain a three-phase composite command, and detecting a maximum voltage value and a minimum voltage value in the three-phase composite command after a time period; According to the zero-sequence voltage being determined as the positive voltage or the negative voltage, select the maximum voltage value or the minimum voltage value to perform logic inversion operation; After completing the logic inversion operation and stopping injecting the zero-sequence voltage, a three-phase output expectation value is obtained; and A duty cycle of the PWM signal is adjusted by comparing the expected value of the three-phase output with the control carrier. The control method as described in claim 1 further includes: Before injecting the zero-sequence voltage into the three-phase control command to obtain the three-phase synthesis command, the duty ratio of the PWM signal is adjusted to 100% or 0%. The control method as described in claim 1 further includes: After determining that the zero-sequence voltage is the positive voltage, detecting a maximum value among the three-phase control commands; detecting a peak value of the control carrier in the switching period; calculating a first voltage difference between the peak value and the maximum value of the three-phase control command, and the first voltage difference is a voltage value of the positive voltage; and The three-phase control command is superimposed with the voltage value of the positive voltage to form the three-phase composite command. The control method as described in claim 3, further comprising: selecting the maximum voltage value in the three-phase synthesis command, and performing the logic inversion operation on the maximum voltage value according to a logic inversion relational expression; wherein, the logic The anticorrelation formula is:

in,

is the maximum voltage value;

is the maximum voltage value after the logic inversion operation is completed. The control method as described in claim 1 further includes: After determining that the zero-sequence voltage is the negative voltage, detecting a minimum value among the three-phase control commands; detecting a valley value of the control carrier in the switching period; calculating a second voltage difference between the valley value and the minimum value of the three-phase control command, and the second voltage difference is a voltage value of the negative voltage; and The three-phase control command is superimposed with the voltage value of the negative voltage to form the three-phase composite command. The control method as described in claim item 5, further comprising: selecting the minimum voltage value in the three-phase synthesis command, and performing the logic inversion operation on the minimum voltage value according to a logic inversion relational expression; wherein, the logic The anticorrelation formula is:

in,

is the minimum voltage value;

is the minimum voltage value after the logic inversion operation is completed. The control method as described in claim 1 further includes: If it is detected that the phase difference does not fall within the predetermined phase range, then detecting a minimum control voltage in the three-phase control command; performing the logic inversion operation on the minimum control voltage according to a logic inversion relational expression; obtaining a three-phase output command after performing the logical inversion operation on the minimum control voltage; and Comparing the three-phase output command and the control carrier to adjust the duty ratio of the PWM signal. The control method as described in claim item 7, wherein the logical inversion relational formula:

in,

is the minimum control voltage;

is the minimum control voltage after the logic inversion operation is completed. The control method as described in claim 1 further includes: When the three-phase control command is compared with the control carrier, determine whether the pulse width modulation signal is a high voltage level or a low voltage level according to the comparison result; Wherein if the three-phase control command is greater than the control carrier, switch the pulse width modulation signal to the high voltage level; Wherein if the three-phase control command is smaller than the control carrier, switch the PWM signal to the low voltage level. The control method as described in Claim 9, further comprising: When the expected value of the three-phase output is compared with the control carrier, the pulse width modulation signal is determined to be the high voltage level or the low voltage level according to the comparison result, wherein the expected value of the three-phase output includes the value obtained through the logical inversion operation a first voltage value and a plurality of second voltage values obtained without logic inversion operation; Wherein, if the first voltage value is greater than the control carrier, switch the corresponding PWM signal to the low voltage level; if the first voltage value is lower than the control carrier, switch the corresponding PWM signal Change the signal to the high voltage level; Wherein, if the second voltage value is greater than the control carrier, switch the corresponding PWM signal to the high voltage level; if the second voltage value is lower than the control carrier, switch the corresponding PWM signal Change the signal to the low voltage level. The control method according to claim 1, wherein the predetermined phase range is -30° to +30° or 150° to 210°, and the control carrier is a triangular wave. A power conversion circuit for driving a motor, comprising: A plurality of switch groups, wherein each of the switch groups includes an upper bridge transistor and a lower bridge transistor, and a first end of each of the upper bridge transistors is electrically connected to each other, and a first end of each of the lower bridge transistors The two terminals are electrically connected to each other, wherein in each switch group, one of the second terminals of the upper bridge transistor is electrically connected to one of the first terminals of the lower bridge transistor; A DC row capacitor for receiving an input power supply, wherein a first end of the DC row capacitor is electrically connected to the first end of each of the high-bridge transistors, and a second end of the DC row capacitor is electrically connected to each the second terminal of the lower bridge transistor; and A controller compares a three-phase control command and a control carrier to obtain multiple pulse width modulation signals; Each of the switch groups correspondingly receives one of the plurality of pulse width modulation signals, and in each of the switch groups, the upper bridge transistor is selectively turned on according to the corresponding received pulse width modulation signal or cut off, and the lower bridge transistor is selectively cut off or turned on, so that the plurality of switch groups switch the input power to generate a three-phase output power to drive the motor; Wherein if the controller detects that the phase difference between the voltage and current of the three-phase output power supply does not fall within a predetermined phase range, the controller detects a minimum control voltage in the three-phase control command; Wherein the controller performs logic inversion operation on the minimum control voltage to obtain a three-phase output command; Wherein the controller compares the three-phase output command and the control carrier to adjust a duty cycle of each of the PWM signals. The power conversion circuit according to claim 12, wherein the controller also performs the logic inversion operation on the minimum control voltage according to a logic inversion relational expression, and the logical inversion relational expression is:

in,

is the minimum control voltage;

is the minimum control voltage after the logic inversion operation is completed. The power conversion circuit as described in Claim 12, wherein: If the controller detects that the phase difference between the voltage and current of the three-phase output power falls within a predetermined phase range, the controller compares the three-phase control command with the control carrier to determine a zero-sequence voltage as a positive voltage or a negative voltage; The controller injects the zero-sequence voltage into the three-phase control command to obtain a three-phase composite command, and detects a maximum voltage value and a minimum voltage value in the three-phase composite command after a time period; According to the zero-sequence voltage being determined as the positive voltage or the negative voltage, the controller selects the maximum voltage value or the minimum voltage value to perform logic inversion operation; The controller obtains a three-phase output expectation value after completing the logic inversion operation and stopping injecting the zero-sequence voltage; and The controller compares the expected value of the three-phase output with the control carrier to adjust a duty cycle of the PWM signal. The power conversion circuit as described in claim 14, wherein before the controller injects the zero-sequence voltage into the three-phase control command to obtain the three-phase synthesis command, the controller adjusts the duty of the pulse width modulation signal The ratio is 100% or 0%.

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