CN105450063A - Half-bridge cascaded multi-level inverter and control method - Google Patents
Half-bridge cascaded multi-level inverter and control method Download PDFInfo
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- CN105450063A CN105450063A CN201510925223.3A CN201510925223A CN105450063A CN 105450063 A CN105450063 A CN 105450063A CN 201510925223 A CN201510925223 A CN 201510925223A CN 105450063 A CN105450063 A CN 105450063A
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Abstract
The invention discloses a half-bridge cascaded multi-level inverter and a control method. The half-bridge cascaded multi-level inverter is formed by connecting a fore converter and a post converter in series, wherein the fore converter is formed by cascading n half-bridge units; one end, between two direct current buses, of each half-bridge unit, is bridged with a direct current power supply or a capacitor and the other end is bridged with a half-bridge circuit; each half-bridge circuit is formed by connecting an insulated gate bipolar transistor and an uncontrolled diode in series; the connection point of the insulated gate bipolar transistor and the uncontrolled diode of the first half-bridge unit leads out an input side endpoint A of the post converter; a negative terminal of the direct current power supply or the capacitor of the nth bridge unit leads out an input side endpoint B of the post converter; and a negative terminal of the direct current power supply or the capacitor of the previous half-bridge unit is connected with the connection point of the next insulated gate bipolar transistor and the next uncontrolled diode. According to the half-bridge cascaded multi-level inverter, the usage quantity of the insulated gate transistors is reduced; and the implementation cost is saved.
Description
Technical field
The present invention relates to power electronics and field of non-linear control, be specifically related to a kind of half-bridge cascade multilevel inverter and control method.
Background technology
Along with the development of power electronic technology, the application of inverter is more and more extensive.And multi-electrical level inverter is because output capacity is large, output voltage current harmonic content is few, switching tube bears the advantages such as reverse voltage is low, in field extensive uses such as mesohigh speed governing and generations of electricity by new energy.Multi-electrical level inverter has various topological structures, mainly contains diode-clamped multi-electrical level inverter, capacitor-clamped type multi-electrical level inverter, cascade multilevel inverter etc. at present.Compare with capacitor-clamped type multi-electrical level inverter with diode-clamped, H bridge cascaded multilevel inverter because of its do not exist DC capacitor dividing potential drop, voltage-sharing, switch tube voltage stress low, be easy to the advantages such as modularization and be widely used in high voltage and high power inverter.But the use of large number of insulated gate bipolar transistor makes cost greatly increase, how to reduce usage quantity and become study hotspot.
Although multi-electrical level inverter has multiple different topological structure, but its conventional modulator approach is general: many level carrier SPWM, space vector SVPW, Staircase wave method etc., under the application conditions of desirable constant dc source, these conventional modulated strategies can reach the control effects of many level, export good waveform quality, meet the needs of converter applications.But these conventional modulated strategies are when there is the non-ideality such as imbalance or low frequency pulsating of input voltage in DC power supply, can cause the distortion of output voltage waveforms, no longer can meet normal need of work.
Summary of the invention
In order to overcome the deficiency of existing cascade connection multi-level topology and control strategy, the invention provides a kind of half-bridge cascade multilevel inverter and control method.
Control strategy of the present invention adopts Cycle Control mode, realizes the superposition of output level thus produce the output of many level by the dislocation of clock pulse.
A kind of half-bridge cascade multilevel inverter, by front, rear class converter is in series, described front stage converter is made up of n half-bridge cells cascade, one end cross-over connection DC power supply or electric capacity between two DC buss of each half-bridge cells, other end cross-over connection half-bridge circuit, described half-bridge circuit is by insulated gate bipolar transistor and do not control Diode series and form, the insulated gate bipolar transistor of described first half-bridge cells and the tie point not controlling diode draw rear class converter input side terminal A, the DC power supply of the n-th half-bridge cells or electric capacity negative terminal draw the input side terminal B of rear class converter, the DC power supply of upper level half-bridge cells or electric capacity negative terminal and next stage insulated gate bipolar transistor and do not control diode tie point be connected.
Described rear class converter is single-phase full bridge inverter circuit.
Described single-phase full bridge inverter circuit is specifically made up of four full-control type power electronic switches.
Also comprise LC filter, described LC filter is connected with rear class converter.
A kind of control method of half-bridge cascade multilevel inverter, each half-bridge cells of front stage converter is by independently single cycle controller control, realized the superposition of level by clock pulse dislocation, rear class converter is by judging that the positive and negative of given voltage makes four full-control type power electronic switch alternate conduction realize replacing of the positive-negative half-cycle of output voltage electric current.
Described clock pulse dislocation is specially: the half-bridge cells clock pulse of each cascade differs T successively
s/ n the time, described T
sfor switch periods.
Described single cycle controller comprises sample circuit, clock pulse generator, reset integrator and rest-set flip-flop.
Beneficial effect of the present invention:
(1) compared with H bridge cascade connection multi-level topology, 2 stage converter be connected on the complexity simplifying power cell system topological structure to a certain extent, decrease the usage quantity of gated transistor, saved implementation cost.
(2) One-Cycle Control Strategy is without the need to high-precision sampling element, and except accurate stable state controls, input voltage uneven at input voltage occurs still can normally work during the unstable situation such as low frequency pulsating in scope by a small margin.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention;
Fig. 2 is the control structure figure of front stage converter of the present invention;
Fig. 3 is the control schematic diagram of rear class converter of the present invention;
Figure 4 shows that the present embodiment is under the application conditions of desirable constant dc source, based on the output voltage waveform of the two-stage type multi-electrical level inverter of Cycle Control;
Fig. 5 (a) and Fig. 5 (b) is depicted as the multi-electrical level inverter of the present invention when DC source contains low frequency pulsating and adopts the output voltage V of Cycle Control
cDoutput waveform figure and LC filtering back loading output voltage V
o;
Fig. 6 (a) and Fig. 6 (b) is depicted as the output voltage V that the multi-electrical level inverter of the present invention when DC source contains low frequency pulsating adopts traditional SPWM to control
cDoutput waveform figure and LC filtering back loading output voltage V
o;
When Fig. 7 (a) and Fig. 7 (b) is depicted as DC source imbalance (only the direct voltage of concatenation unit 1 contains low frequency pulsating), multi-electrical level inverter of the present invention adopts the output voltage V of Cycle Control
cDoutput waveform figure and LC filtering back loading output voltage V
o;
The output voltage V that when Fig. 8 (a) and Fig. 8 (b) is depicted as DC source imbalance (only the direct voltage of concatenation unit 1 contains low frequency pulsating), multi-electrical level inverter of the present invention adopts traditional SPWM to control
cDoutput waveform figure and LC filtering back loading output voltage V
o.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
As shown in Figure 1, a kind of half-bridge cascade multilevel inverter, by front, rear class converter is in series, described front stage converter is made up of n half-bridge cells cascade, one end cross-over connection DC power supply or electric capacity between two DC buss of each half-bridge cells, other end cross-over connection half-bridge circuit, described half-bridge circuit is by insulated gate bipolar transistor and do not control Diode series and form, the insulated gate bipolar transistor of described first half-bridge cells and the tie point not controlling diode draw rear class converter input side terminal A, the DC power supply of the n-th half-bridge cells or electric capacity negative terminal draw the input side terminal B of rear class converter, the DC power supply of upper level half-bridge cells or electric capacity negative terminal and next stage insulated gate bipolar transistor and do not control diode tie point be connected.
Described half-bridge circuit is specially full-control type power electronic switch S
i1do not control type diode D
i1be in series, wherein full-control type power electronic switch S
i1anti-paralleled diode D'
i1.
Described rear class converter is single-phase full bridge inverter circuit, is specially the single-phase full bridge inverter circuit be made up of 4 full-control type power electronic switches, by full-control type power electronic switch S
1, S
2series connection obtains brachium pontis B
1, and switch S
1anti-paralleled diode D
1, switch S
2anti-paralleled diode D
2; By full-control type power electronic switch S
3, S
4be in series brachium pontis B
2, and switch S
3anti-paralleled diode D
3, switch S
4anti-paralleled diode D
4.Exit point C and D of inverter is connected in series LC filter.
Control method of the present invention, comprising:
Each half-bridge cells of front stage converter is by independently single cycle controller control, the superposition of level is realized by clock pulse dislocation, rear class converter is by judging that the positive and negative of given voltage makes four insulated gate bipolar transistor alternate conduction realize replacing of the positive-negative half-cycle of output voltage electric current, described clock pulse dislocation is specially, and the half-bridge cells clock pulse of each cascade differs T successively
s/ n the time, described T
sfor switch periods.
Detailed process is:
(1) adopt the one-cycle control technique, each concatenation unit of front stage converter all adopts independently one-cycle controller, comprises sample circuit, clock pulse generator, reset integrator and rest-set flip-flop.In each concatenation unit, clock pulse misplaces T successively
s/ n time, wherein T
sfor switch periods.For concatenation unit 1, the clock pulse phase shift of one-cycle controller is set to 0, and the Q of rest-set flip-flop holds output to be switch S
11switching signal g (S
11); For concatenation unit 2, the clock pulse phase shift of one-cycle controller is set to T
s/ n, the Q of rest-set flip-flop holds output to be switch S
21switching signal g (S
21); For concatenation unit i, the clock pulse phase shift of one-cycle controller is set to (i-1) T
s/ n, the Q of rest-set flip-flop holds output to be switch S
i1switching signal g (S
i1).
(2) control of rear class inverter is by judging to the positive and negative modulation signal obtaining each switching tube of the complementary conducting of the upper and lower switching tube of the same brachium pontis of inverter of determining voltage signal, wherein S
1switching signal be g (S
1), S
2switching signal be g (S
2), S
3switching signal be g (S
3), S
4switching signal be g (S
4).When being timing to determining voltage signal, switch S
1, S
4conducting and S
2, S
3turn off, now output voltage V
odirection and the output voltage V of front stage converter
gidentical; When being negative to determining voltage signal, switch S
2, S
3conducting and S
1, S
4turn off, now output voltage V
odirection and the output voltage V of front stage converter
gon the contrary.Replacing of output voltage positive-negative half-cycle is achieved by the alternate conduction of switch.
Shown in Fig. 2, single cycle controller comprises sample circuit, clock pulse generator, reset integrator and rest-set flip-flop, makes the present invention be convenient to realize modularization.When clock signal arrives, integrator starts the voltage signal (V to gathering
o1, V
o2v
oiv
on) carry out integration, when arriving set-point, integrator is reset to zero, until restart to carry out integration when next clock signal arrives.Each concatenation unit all adopts independently one-cycle controller to control, and in each concatenation unit, clock pulse misplaces T successively
s/ n time, wherein T
sfor switch periods.For concatenation unit 1, the clock pulse phase shift of one-cycle controller is set to 0, and the Q of rest-set flip-flop holds output to be switch S
11switching signal g (S
11); For concatenation unit 2, the clock pulse phase shift of one-cycle controller is set to T
s/ n, the Q of rest-set flip-flop holds output to be switch S
21switching signal g (S
21); For concatenation unit i, the clock pulse phase shift of one-cycle controller is set to (i-1) T
s/ n, the Q of rest-set flip-flop holds output to be switch S
i1switching signal g (S
i1).N=3 in the present embodiment, realizes four level inverse conversion effects, and in control, three cascade half-bridge cells clock pulse stagger T successively
sthe time of/3.
Figure 3 shows that the control of rear class converter, by judging to the positive and negative modulation signal obtaining each switching tube of the complementary conducting of the upper and lower switching tube of the same brachium pontis of inverter of determining voltage signal, wherein S
1switching signal be g (S
1), S
2switching signal be g (S
2), S
3switching signal be g (S
3), S
4switching signal be g (S
4).Replacing of output voltage positive-negative half-cycle is achieved by the alternate conduction of switch.
Be illustrated in figure 4 the present embodiment under the application conditions of desirable constant dc source, based on the output voltage waveform of the two-stage type multi-electrical level inverter of Cycle Control.V in the present embodiment
cDfor rear class inverter output voltage; V
ofor LC filtering back loading output voltage.
Fig. 5 (a) Fig. 5 (b)-Fig. 8 (a) Fig. 8 (b) is under DC power supply non-ideality: as low frequency pulsating, (it is 5Hz that each concatenation unit DC power supply all adds a frequency, amplitude be 7V sinusoidal cycles interference) or the imbalance of input voltage (only the DC power supply of concatenation unit 1 adds a frequency is 5Hz, amplitude is the sinusoidal cycles interference of 7V) time, multi-electrical level inverter of the present invention adopts the output voltage waveforms of Cycle Control.In order to embody the advantage of Cycle Control, choosing traditional SPWM and controlling as a comparison.Can see at any non-ideality from result, Cycle Control all can the sinusoidal voltage of stable output, and the amplitude of the output voltage that traditional SPWM controls can fluctuate.
The output voltage V of Cycle Control is adopted as Fig. 5 (a) and Fig. 5 (b) is depicted as the multi-electrical level inverter of the present invention when DC source contains low frequency pulsating
cDoutput waveform figure and LC filtering back loading output voltage V
o.
As Fig. 6 (a) and Fig. 6 (b) is depicted as the output voltage V that the multi-electrical level inverter of the present invention when DC source contains low frequency pulsating adopts traditional SPWM to control
cDoutput waveform figure and LC filtering back loading output voltage V
o.
As multi-electrical level inverter of the present invention when Fig. 7 (a) and Fig. 7 (b) is depicted as DC source imbalance (only the direct voltage of concatenation unit 1 contains low frequency pulsating) adopts the output voltage V of Cycle Control
cDoutput waveform figure and LC filtering back loading output voltage V
o.
As the output voltage V that multi-electrical level inverter of the present invention when Fig. 8 (a) and Fig. 8 (b) is depicted as DC source imbalance (only the direct voltage of concatenation unit 1 contains low frequency pulsating) adopts traditional SPWM to control
cDoutput waveform figure and LC filtering back loading output voltage V
o.
The result display of embodiment, under desirable DC power supply condition, Cycle Control and traditional SPWM control the control effects that can reach many level, after LC filtering, obtain stable sinusoidal voltage waveform, and waveform quality is good, meets the needs of converter applications.But when DC power supply exists non-ideality, the output voltage waveforms that traditional SPWM controls can instability even distort, and no longer can meet normal need of work.
Prime cascade half-bridge converter of the present invention is connected with rear class inverter circuit, well can realize many level staircase waveform of near sinusoidal, simplify the complexity of power cell system topological structure, decrease the usage quantity of insulated gate bipolar transistor, thus reduce cost, save cost;
Cycle Control of the present invention is used for the control of each half-bridge cells of prime, without the need to high-precision sampling element, except accurately controlling, to the disturbance of DC side input voltage, comprise Voltage unbalance and voltage low frequency pulsating etc. and there is good rejection ability, effectively solve the wave distortion problem existed in conventional modulated.
Above-described embodiment is the present invention's preferably execution mode; but embodiments of the present invention are not limited by the examples; change, the modification done under other any does not deviate from Spirit Essence of the present invention and principle, substitute, combine, simplify; all should be the substitute mode of equivalence, be included within protection scope of the present invention.
Claims (7)
1. a half-bridge cascade multilevel inverter, it is characterized in that, by front, rear class converter is in series, described front stage converter is made up of n half-bridge cells cascade, one end cross-over connection DC power supply or electric capacity between two DC buss of each half-bridge cells, other end cross-over connection half-bridge circuit, described half-bridge circuit is by insulated gate bipolar transistor and do not control Diode series and form, the insulated gate bipolar transistor of described first half-bridge cells and the tie point not controlling diode draw rear class converter input side terminal A, the DC power supply of the n-th half-bridge cells or electric capacity negative terminal draw the input side terminal B of rear class converter, the DC power supply of upper level half-bridge cells or electric capacity negative terminal and next stage insulated gate bipolar transistor and do not control diode tie point be connected.
2. a kind of half-bridge cascade multilevel inverter according to claim 1, is characterized in that, described rear class converter is single-phase full bridge inverter circuit.
3. a kind of half-bridge cascade multilevel inverter according to claim 2, is characterized in that, described single-phase full bridge inverter circuit is specifically made up of four full-control type power electronic switches.
4. a kind of half-bridge cascade multilevel inverter according to claim 1, is characterized in that, also comprise LC filter, and described LC filter is connected with rear class converter.
5. a kind of control method of half-bridge cascade multilevel inverter according to any one of claim 1-4, it is characterized in that, each half-bridge cells of front stage converter is by independently single cycle controller control, realized the superposition of level by clock pulse dislocation, rear class converter is by judging that the positive and negative of given voltage makes four full-control type power electronic switch alternate conduction realize replacing of the positive-negative half-cycle of output voltage electric current.
6. control method according to claim 5, is characterized in that, described clock pulse dislocation is specially: the half-bridge cells clock pulse of each cascade differs T successively
s/ n the time, described T
sfor switch periods.
7. control method according to claim 5, is characterized in that, described single cycle controller comprises sample circuit, clock pulse generator, reset integrator and rest-set flip-flop.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105811795A (en) * | 2016-05-10 | 2016-07-27 | 浙江大学 | Master-slave hybrid cascaded multilevel inverter |
| CN106385189A (en) * | 2016-10-13 | 2017-02-08 | 华南理工大学 | Two-level cascaded multilevel inverter |
| CN106787899A (en) * | 2016-12-20 | 2017-05-31 | 南京航空航天大学 | A kind of many level power inversion systems of new two-stage type |
| CN109149980A (en) * | 2017-06-19 | 2019-01-04 | 华北电力大学 | A kind of change submodule output voltage polar circuit |
| CN109599855A (en) * | 2018-12-24 | 2019-04-09 | 华北电力大学（保定） | Cascade direct current inversion of direct current collects grid connection topology and phase-shifting control method |
| CN110677068A (en) * | 2019-10-23 | 2020-01-10 | 西安交通大学 | High-voltage high-frequency waveform generator |
| WO2020223830A1 (en) | 2019-05-09 | 2020-11-12 | Universidad De Talca | Multilevel power converter circuit |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105811795A (en) * | 2016-05-10 | 2016-07-27 | 浙江大学 | Master-slave hybrid cascaded multilevel inverter |
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| CN109599855A (en) * | 2018-12-24 | 2019-04-09 | 华北电力大学（保定） | Cascade direct current inversion of direct current collects grid connection topology and phase-shifting control method |
| CN109599855B (en) * | 2018-12-24 | 2022-04-29 | 华北电力大学（保定） | Cascaded direct current-to-direct current collection grid-connected topology and phase-shifting control method |
| WO2020223830A1 (en) | 2019-05-09 | 2020-11-12 | Universidad De Talca | Multilevel power converter circuit |
| US12003194B2 (en) | 2019-05-09 | 2024-06-04 | Universidad De Talca | Multilevel power converter circuit |
| CN110677068A (en) * | 2019-10-23 | 2020-01-10 | 西安交通大学 | High-voltage high-frequency waveform generator |
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