CN205336145U - Half -bridge cascades many inverter of type - Google Patents

Abstract

The utility model discloses a half-bridge cascaded multi-level inverter, which is composed of a front-stage converter and a rear-stage converter connected in series. The front-stage converter is composed of n half-bridge units cascaded, and each half-bridge unit One end of the two DC buses is connected to a DC power supply or a capacitor, and the other end is connected to a half-bridge circuit. The half-bridge circuit is composed of an insulated gate bipolar transistor and an uncontrolled diode connected in series. The first half-bridge unit The connection point of the insulated gate bipolar transistor and the uncontrolled diode leads to the input side terminal A of the subsequent stage converter, and the DC power supply or the negative terminal of the capacitor of the nth half-bridge unit leads to the input side terminal B of the subsequent stage converter; The DC power supply or the negative terminal of the capacitor of the bridge unit is connected to the connection point of the next-stage insulated gate bipolar transistor and the uncontrolled diode. The utility model reduces the number of insulating gate transistors used and saves the implementation cost.

Description

A half-bridge cascaded multilevel inverter

technical field

The utility model relates to the field of power electronics and nonlinear control, in particular to a half-bridge cascaded multilevel inverter.

Background technique

With the development of power electronics technology, inverters are used more and more widely. The multi-level inverter is widely used in the fields of medium and high voltage speed regulation and new energy power generation due to its advantages of large output capacity, low harmonic content of output voltage and current, and low reverse voltage of the switching tube. Multi-level inverters have a variety of topological structures, and currently there are mainly diode-clamped multi-level inverters, capacitor-clamped multi-level inverters, and cascaded multi-level inverters. Compared with diode-clamped and capacitor-clamped multi-level inverters, H-bridge cascaded multi-level inverters do not have the problem of DC capacitor voltage division and voltage equalization, and the voltage stress of switch tubes is low. It is widely used in high-voltage and large-capacity converters. However, the use of a large number of insulated gate bipolar transistors has greatly increased the cost, and how to reduce the number of used has become a research hotspot.

Although multilevel inverters have many different topological structures, their commonly used modulation methods are common: multilevel carrier SPWM, space vector SVPW, ladder wave modulation methods, etc., under ideal constant DC power application conditions, These traditional modulation strategies can achieve multi-level control effects, output good waveform quality, and meet the needs of converter applications. However, these traditional modulation strategies will lead to distortion of the output voltage waveform when the DC power supply has unbalanced input voltage or non-ideal conditions such as low-frequency fluctuations, which can no longer meet the normal working needs.

Utility model content

In order to overcome the shortcomings of the existing cascaded multi-level topology and control strategy, the utility model provides a half-bridge cascaded multi-level inverter.

The control strategy of the utility model adopts a single-cycle control method, and the superposition of output levels is realized through the dislocation of clock pulses to generate multi-level outputs.

A half-bridge cascaded multilevel inverter, which is composed of front-end and rear-stage converters connected in series, the front-end converter is composed of n half-bridge units cascaded, and two DC buses of each half-bridge unit One end of the bridge is connected to a DC power supply or a capacitor, and the other end is connected to a half-bridge circuit. The half-bridge circuit is composed of an insulated gate bipolar transistor and an uncontrolled diode connected in series. The insulated gate bipolar of the first half-bridge unit The connection point of the transistor and the uncontrolled diode leads to the terminal A of the input side of the subsequent stage converter, and the DC power supply or the negative terminal of the capacitor of the nth half-bridge unit leads to the terminal B of the input side of the subsequent stage converter; the DC power of the upper half-bridge unit The negative terminal of the power supply or the capacitor is connected to the connection point of the next-stage IGBT and the uncontrolled diode.

The latter converter is a single-phase full-bridge inverter circuit.

The single-phase full-bridge inverter circuit is specifically composed of four fully-controlled power electronic switches.

An LC filter is also included, and the LC filter is connected to the post-stage converter.

A control method for a half-bridge cascaded multi-level inverter. Each half-bridge unit of the front-stage converter is controlled by an independent single-cycle controller, and the superposition of the levels is realized through clock pulse dislocation, and the subsequent stage is converted. By judging the positive and negative of the given voltage, the four fully-controlled power electronic switches are alternately turned on to realize the alternation of the positive and negative half cycles of the output voltage and current.

The clock pulse misalignment is specifically: the clock pulses of each cascaded half-bridge unit are sequentially different by T _s /n time, and the T _s is a switching period.

The single-cycle controller includes a sampling circuit, a clock pulse generator, a reset integrator and an RS flip-flop.

The beneficial effects of the utility model:

(1) Compared with the H-bridge cascaded multilevel topology, the series connection of two-stage converters simplifies the complexity of the power unit system topology to a certain extent, reduces the number of insulated gate transistors used, and saves implementation costs.

(2) The single-cycle control strategy does not require a high-precision sampling link. In addition to precise steady-state control, it can still work normally when the input voltage is unbalanced and the input voltage has low-frequency fluctuations in a small range.

Description of drawings

Fig. 1 is the structural representation of the utility model;

Fig. 2 is a control structure diagram of the front-stage converter of the present utility model;

Fig. 3 is a schematic diagram of the control of the rear stage converter of the present invention;

Figure 4(a) and Figure 4(b) show the output voltage waveforms of the two-stage multilevel inverter based on single-cycle control under the application conditions of the ideal constant DC power supply in this embodiment, and V _CD is the latter stage inverter output voltage; V _o is the load output voltage after LC filtering;

Figure 5(a) and Figure 5(b) show the output waveform diagram of the output voltage V _CD and the load output after LC filtering when the multilevel inverter of the present invention adopts single-cycle control when the DC source contains low-frequency pulsation voltage V _o ;

Figure 6(a) and Figure 6(b) show the output waveform diagram of the output voltage V _CD and the load output after LC filtering when the multi-level inverter of the present invention adopts traditional SPWM control when the DC source contains low-frequency pulsation voltage V _o ;

Figure 7(a) and Figure 7(b) show that when the DC source is unbalanced (only the DC voltage of the cascaded unit 1 contains low-frequency ripples), the output voltage V of the multilevel inverter of the present invention adopts single-cycle control The output waveform diagram of _CD and the load output voltage V _o after LC filtering;

Figure 8(a) and Figure 8(b) show the output voltage V of the multilevel inverter of the present invention using traditional SPWM control when the DC source is unbalanced (only the DC voltage of the cascaded unit 1 contains low-frequency ripples). The output waveform diagram of _CD and the load output voltage V _o after LC filtering.

detailed description

The utility model will be described in further detail below in conjunction with the embodiments and accompanying drawings, but the implementation of the utility model is not limited thereto.

Example

As shown in Figure 1, a half-bridge cascaded multilevel inverter is composed of a front-stage converter and a rear-stage converter connected in series. The front-stage converter is composed of n half-bridge units cascaded. One end of the two DC buses of the unit is connected to a DC power supply or a capacitor, and the other end is connected to a half-bridge circuit. The half-bridge circuit is composed of an insulated gate bipolar transistor and an uncontrolled diode in series. The first half-bridge unit The connection point of the insulated gate bipolar transistor and the uncontrolled diode leads to the input side terminal A of the subsequent stage converter, and the DC power supply or the negative terminal of the capacitor of the nth half-bridge unit leads to the input side terminal B of the subsequent stage converter; The DC power supply or the negative terminal of the capacitor of the half-bridge unit is connected to the connection point of the next-stage IGBT and the uncontrolled diode.

The half-bridge circuit is specifically composed of a fully-controlled power electronic switch S _i1 connected in series with an uncontrolled diode D _i1 , wherein the fully-controlled power electronic switch S _i1 is connected in antiparallel with a diode D' _i1 .

The post-stage converter is a single-phase full-bridge inverter circuit, specifically a single-phase full-bridge inverter circuit composed of four fully _- controlled power electronic switches, which are connected in series by fully _- controlled power electronic switches S1 and S2 _The bridge arm B ₁ is obtained, and the switch _{S 1} is connected in antiparallel with the diode D ₁ , and the switch _{S 2} is connected in antiparallel with the diode D _{2 ;} Diode D ₃ is connected in parallel, and switch S ₄ is connected in antiparallel with diode D ₄ . The output terminals C and D of the inverter are connected in series with LC filters.

The control method of the present utility model comprises:

Each half-bridge unit of the front-end converter is controlled by an independent single-cycle controller, and the level superposition is realized through the dislocation of the clock pulse, and the post-stage converter makes the four insulated gate bipolar Transistors are turned on alternately to realize the alternation of the positive and negative half cycles of the output voltage and current. The clock pulse misalignment is specifically that the clock pulses of each cascaded half-bridge unit are sequentially different by T _s /n time, and the T _s is the switching period.

The specific process is:

(1) Single-cycle control technology is adopted. Each cascaded unit of the pre-converter adopts an independent single-cycle controller, including a sampling circuit, a clock pulse generator, a reset integrator and an RS flip-flop. The clock pulses in each cascaded unit are sequentially shifted by T _s /n time, where T _s is the switching period. For cascade unit 1, the clock pulse phase shift of the single-cycle controller is set to 0, and the output of the Q terminal of the RS flip-flop is the switching signal g(S ₁₁ ) of switch S ₁₁ ; for cascade unit 2, the single-cycle controller The clock phase shift of the clock pulse is set to T _s /n, and the output of the Q terminal of the RS flip-flop is the switching signal g(S ₂₁ ) of the switch S ₂₁ ; for the cascaded unit i, the clock pulse phase shift of the single-cycle controller is set to (i-1)T _s /n, the output of the Q terminal of the RS flip-flop is the switching signal g(S _i1 ) of the switch S _i1 .

(2) The control of the post-stage inverter obtains the modulation signal of each switching tube of the upper and lower switching tubes of the same bridge arm of the inverter by judging the positive and negative of the given voltage signal, where the switching signal _of S1 is g( S ₁ ), the switch signal of S ₂ is g(S ₂ ), the switch signal of S ₃ is g(S ₃ ), and the switch signal of S ₄ is g(S ₄ ). When the given voltage signal is positive, the switches S ₁ and S ₄ are turned on and S ₂ and S ₃ are turned off. At this time, the direction of the output voltage V _o is the same as the output voltage V _g of the previous stage converter; when the given voltage When the signal is negative, the switches S ₂ and S ₃ are turned on and S ₁ and S ₄ are turned off. At this time, the direction of the output voltage V _o is opposite to the output voltage V _g of the previous stage converter. The alternation of the positive and negative half cycles of the output voltage is realized through the alternate conduction of the switches.

The single-cycle controller shown in Fig. 2 includes a sampling circuit, a clock pulse generator, a reset integrator and an RS flip-flop, which makes the utility model easy to realize modularization. When the clock signal arrives, the integrator starts to integrate the collected voltage signal (V _o1 ,V _o2 …V _oi …V _on ), and when it reaches a given value, the integrator resets to zero and restarts when the next clock signal arrives Make points. Each cascaded unit is controlled by an independent single-cycle controller, and the clock pulses in each cascaded unit are sequentially shifted by T _s /n time, where T _s is the switching period. For cascade unit 1, the clock pulse phase shift of the single-cycle controller is set to 0, and the output of the Q terminal of the RS flip-flop is the switching signal g(S ₁₁ ) of switch S ₁₁ ; for cascade unit 2, the single-cycle controller The clock phase shift of the clock pulse is set to T _s /n, and the output of the Q terminal of the RS flip-flop is the switching signal g(S ₂₁ ) of the switch S ₂₁ ; for the cascaded unit i, the clock pulse phase shift of the single-cycle controller is set to (i-1)T _s /n, the output of the Q terminal of the RS flip-flop is the switching signal g(S _i1 ) of the switch S _i1 . In this embodiment, n=3 to achieve a four-level inverter effect, and the clock pulses of the three cascaded half-bridge units in the control are sequentially staggered by T _s /3.

Figure 3 shows the control of the post-stage converter. By judging the positive and negative of the given voltage signal, the modulation signals of the switching tubes of the upper and lower switching tubes of the same bridge arm of the inverter are obtained. _The switching signal of S1 is g(S ₁ ), the switch signal of S ₂ is g(S ₂ ), the switch signal of S ₃ is g(S ₃ ), and the switch signal of S ₄ is g(S ₄ ). The alternation of the positive and negative half cycles of the output voltage is realized through the alternate conduction of the switches.

FIG. 4( a ) and FIG. 4( b ) show the output voltage waveforms of the two-stage multilevel inverter based on single-cycle control under the application condition of ideal constant DC power supply in this embodiment. In this embodiment, V _CD is the output voltage of the subsequent inverter; V _o is the output voltage of the load after LC filtering.

Figure 5(a) Figure 5(b)-Figure 8(a) Figure 8(b) is in the case of non-ideal DC power supply: such as low-frequency pulsation (the DC power supply of each cascaded unit is added with a frequency of 5Hz, and the amplitude is 7V sinusoidal cycle interference) or input voltage imbalance (only the DC power supply of cascade unit 1 adds a sinusoidal cycle interference with a frequency of 5Hz and an amplitude of 7V), the multilevel inverter of the present invention adopts a single Cycle controlled output voltage waveform. In order to reflect the advantages of one-week control, the traditional SPWM control is selected as a comparison. It can be seen from the results that in any non-ideal situation, the single-cycle control can output a stable sinusoidal voltage, while the amplitude of the output voltage of the traditional SPWM control will fluctuate.

As shown in Figure 5(a) and Figure 5(b), when the DC source contains low-frequency pulsation, the multilevel inverter of the present invention adopts the output waveform diagram of the output voltage V _CD of single-cycle control and the load after LC filtering output voltage V _o .

As shown in Figure 6(a) and Figure 6(b), when the DC source contains low-frequency pulsation, the multilevel inverter of the present invention adopts the output waveform diagram of the output voltage V _CD controlled by traditional SPWM and the load after LC filtering output voltage V _o .

As shown in Figure 7(a) and Figure 7(b), when the DC source is unbalanced (only the DC voltage of the cascade unit 1 contains low-frequency ripples), the multilevel inverter of the present invention adopts the output voltage of single-cycle control The output waveform diagram of V _CD and the load output voltage V _o after LC filtering.

As shown in Figure 8(a) and Figure 8(b), when the DC source is unbalanced (only the DC voltage of the cascaded unit 1 contains low-frequency ripples), the multilevel inverter of the present invention adopts the output voltage controlled by traditional SPWM The output waveform diagram of V _CD and the load output voltage V _o after LC filtering.

The results of the embodiment show that under the ideal DC power supply conditions, both single-cycle control and traditional SPWM control can achieve multi-level control effects, and a stable sinusoidal voltage waveform can be obtained after LC filtering, and the waveform quality is good, which meets the needs of converter applications. needs. However, when there are non-ideal conditions in the DC power supply, the output voltage waveform of the traditional SPWM control will be unstable or even distorted, which can no longer meet the needs of normal work.

The series connection of the front-stage cascaded half-bridge converter and the rear-stage inverter circuit of the utility model can well realize a multi-level ladder wave approximately sinusoidal, simplifies the complexity of the topology structure of the power unit system, and reduces the double The number of pole-type transistors used reduces the cost of manufacturing and saves costs;

The single-cycle control of the utility model is used for the control of each half-bridge unit of the previous stage, and does not require high-precision sampling links. In addition to precise control, it has good suppression of the disturbance of the input voltage on the DC side, including voltage imbalance and low-frequency voltage fluctuations. Ability to effectively solve the problem of waveform distortion in traditional modulation.

The above-mentioned embodiment is a preferred implementation mode of the present utility model, but the implementation mode of the present utility model is not limited by the described embodiment, and any other changes, modifications, modifications, Substitution, combination, and simplification should all be equivalent replacement methods, and are all included in the protection scope of the present utility model.

Claims (4)

1. A half-bridge cascaded multilevel inverter is characterized in that, it is formed in series by front and rear stage converters, and said front-stage converter is formed by cascading n half-bridge units, and each half-bridge One end of the two DC buses of the unit is connected to a DC power supply or a capacitor, and the other end is connected to a half-bridge circuit. The half-bridge circuit is composed of an insulated gate bipolar transistor and an uncontrolled diode in series. The first half-bridge unit The connection point of the insulated gate bipolar transistor and the uncontrolled diode leads to the input side terminal A of the post-stage converter, and the DC power supply or the negative terminal of the capacitor of the nth half-bridge unit leads to the input side terminal B of the post-stage converter; The direct current power supply or the negative terminal of the capacitor of the half-bridge unit of the first stage is connected with the connection point of the IGBT and the uncontrolled diode of the next stage. 2 . A half-bridge cascaded multilevel inverter according to claim 1 , wherein the rear-stage converter is a single-phase full-bridge inverter circuit. 3 . The half-bridge cascaded multilevel inverter according to claim 2 , wherein the single-phase full-bridge inverter circuit is specifically composed of four fully-controlled power electronic switches. 4 . 4 . The half-bridge cascaded multilevel inverter according to claim 1 , further comprising an LC filter connected to a subsequent converter. 5 .