CN205336145U - Half -bridge cascades many inverter of type - Google Patents
Half -bridge cascades many inverter of type Download PDFInfo
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- CN205336145U CN205336145U CN201521035748.1U CN201521035748U CN205336145U CN 205336145 U CN205336145 U CN 205336145U CN 201521035748 U CN201521035748 U CN 201521035748U CN 205336145 U CN205336145 U CN 205336145U
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Abstract
The utility model discloses a half -bridge cascades many inverter of type, it constitutes to be established ties by preceding, back level converter, the preceding stage converter is cascaded by a n half -bridge unit and constitutes, one end cross -over connection DC power supply or electric capacity between two dc buss of every half -bridge unit, and other end cross -over connection half -bridge circuit, the half -bridge circuit is by insulated gate bipolar nature transistor and do not control the diode and establish ties and to constitute, the insulated gate bipolar nature transistor of first half -bridge unit reaches the tie point of not controlling the diode and draws back level converter inlet side extreme point A, and the inlet side extreme point B of back level converter is drawn to the DC power supply or the electric capacity negative terminal of n half -bridge unit, DC power supply or the electric capacity negative terminal of going up one -level half -bridge unit and next stage insulated gate bipolar nature transistor and the tie point of not controlling the diode link to each other. The utility model discloses reduce gated transistor's use quantity, practiced thrift implementation cost.
Description
Technical field
This utility model relates to power electronics and field of non-linear control, is specifically related to a kind of half-bridge cascade multilevel inverter。
Background technology
Along with the development of Power Electronic Technique, the application of inverter is more and more extensive。And multi-electrical level inverter is owing to output capacity is big, output voltage current harmonic content is few, switching tube bears the advantages such as backward voltage is low, in field extensive uses such as mesohigh speed governing and generations of electricity by new energy。Multi-electrical level inverter has various topological structures, currently mainly has diode-clamped multi-electrical level inverter, capacitor-clamped type multi-electrical level inverter, cascade multilevel inverter etc.。Compared with diode-clamped and capacitor-clamped type multi-electrical level inverter, H bridge cascaded multilevel inverter because of its be absent from DC capacitor dividing potential drop, voltage-sharing, switch tube voltage stress is low, be prone to the advantages such as modularity is widely used in high voltage and high power inverter。But, the use of large number of insulated gate bipolar transistor makes cost be greatly increased, and how to reduce usage quantity and becomes study hotspot。
Although multi-electrical level inverter has multiple different topological structure, but its conventional modulator approach is general: many level carrier SPWM, space vector SVPW, Staircase wave method etc., under the application conditions of desirable constant dc source, these conventional modulated strategies can reach the control effect of many level, exports good waveform quality, meets the needs of converter applications。But these conventional modulated strategies are when existing the non-idealities such as imbalance or the low frequency pulsating of input voltage at DC source, the distortion of output voltage waveforms can be caused, be no longer able to meet normal job demand。
Utility model content
In order to overcome the deficiency of existing cascade connection multi-level topology and control strategy, this utility model provides a kind of half-bridge cascade multilevel inverter。
This utility model control strategy adopts Cycle Control mode, realizes the superposition of output level by the dislocation of clock pulses thus producing the output of many level。
A kind of half-bridge cascade multilevel inverter, by front, rear class changer is in series, described front stage converter is made up of n half-bridge cells cascade, one end bridging DC source or electric capacity between two dc bus of each half-bridge cells, other end bridging half-bridge circuit, described half-bridge circuit is by insulated gate bipolar transistor and does not control Diode series and constitutes, the insulated gate bipolar transistor of described first half-bridge cells and do not control the junction point of diode and draw rear class changer input side terminal A, the DC source of the n-th half-bridge cells or electric capacity negative terminal draw the input side terminal B of rear class changer；The DC source of upper level half-bridge cells or electric capacity negative terminal and next stage insulated gate bipolar transistor and do not control diode junction point be connected。
Described rear class changer is single-phase full bridge inverter circuit。
Described single-phase full bridge inverter circuit is specifically made up of four full-control type power electronic switches。
Also including LC wave filter, described LC wave filter is connected with rear class changer。
A kind of control method of half-bridge cascade multilevel inverter, each half-bridge cells of front stage converter controls by independent single cycle controller, being misplaced by clock pulses and realize the superposition of level, rear class changer is by judging replacing of the positive and negative positive-negative half-cycle making four full-control type power electronics switch alternate conduction realize output voltage electric current of given voltage。
Described clock pulses misplaces particularly as follows: the half-bridge cells clock pulses of each cascade differs T successivelys/ n the time, described TsFor switch periods。
Described single cycle controller includes sample circuit, clock pulse generator, reset integrator and rest-set flip-flop。
The beneficial effects of the utility model:
(1) compared with H bridge cascade connection multi-level topology, 2 stage converter be connected on the complexity simplifying power cell system topological structure to a certain extent, decrease the usage quantity of gated transistor, saved implementation cost。
(2) One-Cycle Control Strategy is without high-precision sampling element, and except accurate homeostatic control, input voltage uneven at input voltage occurs by a small margin still can normal operation during the unstable situation such as low frequency pulsating in scope。
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model；
Fig. 2 is the control structure figure of front stage converter of the present utility model；
Fig. 3 is the control schematic diagram of rear class changer of the present utility model；
Fig. 4 (a) and Fig. 4 (b) show the present embodiment under the application conditions of desirable constant dc source, based on the output voltage waveform of the two-stage type multi-electrical level inverter of Cycle Control, VCDFor rear class inverter output voltage；VoBack loading output voltage is filtered for LC；
Fig. 5 (a) and Fig. 5 (b) show the multi-electrical level inverter of the present utility model when DC source contains low frequency pulsating and adopts the output voltage V of Cycle ControlCDOutput waveform figure and LC filter back loading output voltage Vo；
Fig. 6 (a) and Fig. 6 (b) show the multi-electrical level inverter of the present utility model when DC source contains low frequency pulsating and adopts the tradition SPWM output voltage V controlledCDOutput waveform figure and LC filter back loading output voltage Vo；
Fig. 7 (a) and Fig. 7 (b) show multi-electrical level inverter of the present utility model during DC source imbalance (only the DC voltage of concatenation unit 1 contains low frequency pulsating) and adopts the output voltage V of Cycle ControlCDOutput waveform figure and LC filter back loading output voltage Vo；
Fig. 8 (a) and Fig. 8 (b) show multi-electrical level inverter of the present utility model during DC source imbalance (only the DC voltage of concatenation unit 1 contains low frequency pulsating) and adopts the tradition SPWM output voltage V controlledCDOutput waveform figure and LC filter back loading output voltage Vo。
Detailed description of the invention
Below in conjunction with embodiment and accompanying drawing, this utility model is described in further detail, but embodiment of the present utility model is not limited to this。
Embodiment
As shown in Figure 1, a kind of half-bridge cascade multilevel inverter, by front, rear class changer is in series, described front stage converter is made up of n half-bridge cells cascade, one end bridging DC source or electric capacity between two dc bus of each half-bridge cells, other end bridging half-bridge circuit, described half-bridge circuit is by insulated gate bipolar transistor and does not control Diode series and constitutes, the insulated gate bipolar transistor of described first half-bridge cells and do not control the junction point of diode and draw rear class changer input side terminal A, the DC source of the n-th half-bridge cells or electric capacity negative terminal draw the input side terminal B of rear class changer；The DC source of upper level half-bridge cells or electric capacity negative terminal and next stage insulated gate bipolar transistor and do not control diode junction point be connected。
Described half-bridge circuit is specially full-control type power electronic switch Si1Do not control type diode Di1It is in series, wherein full-control type power electronic switch Si1Anti-paralleled diode D'i1。
Described rear class changer is single-phase full bridge inverter circuit, is specially and is switched, by 4 full-control type power electronics, the single-phase full bridge inverter circuit formed, full-control type power electronic switchs S1、S2Series connection obtains brachium pontis B1, and switch S1Anti-paralleled diode D1, switch S2Anti-paralleled diode D2；S is switched by full-control type power electronic3、S4Be in series brachium pontis B2, and switch S3Anti-paralleled diode D3, switch S4Anti-paralleled diode D4。Exit point C and the D of inverter concatenates LC wave filter。
Control method of the present utility model, including:
Each half-bridge cells of front stage converter controls by independent single cycle controller, the superposition of level is realized by clock pulses dislocation, rear class changer is by judging replacing of the positive and negative positive-negative half-cycle making four insulated gate bipolar transistor alternate conduction realize output voltage electric current of given voltage, described clock pulses misplaces specifically, the half-bridge cells clock pulses of each cascade differs T successivelys/ n the time, described TsFor switch periods。
Detailed process is:
(1) adopting the one-cycle control technique, each concatenation unit of front stage converter all adopts independent one-cycle controller, including sample circuit, clock pulse generator, reset integrator and rest-set flip-flop。In each concatenation unit, clock pulses misplaces T successivelys/ n time, wherein TsFor switch periods。For concatenation unit 1, the clock pulses phase shift of one-cycle controller is set to 0, and the Q end output of rest-set flip-flop is switch S11Switching signal g (S11)；For concatenation unit 2, the clock pulses phase shift of one-cycle controller is set to Ts/ n, the Q end output of rest-set flip-flop is switch S21Switching signal g (S21)；For concatenation unit i, the clock pulses phase shift of one-cycle controller is set to (i-1) Ts/ n, the Q end output of rest-set flip-flop is switch Si1Switching signal g (Si1)。
(2) control of rear class inverter is by judging to the modulation signal of the positive and negative each switching tube obtaining the same brachium pontis of inverter upper and lower switching tube complementation conducting of determining voltage signal, wherein S1Switching signal be g (S1), S2Switching signal be g (S2), S3Switching signal be g (S3), S4Switching signal be g (S4)。When being timing to determining voltage signal, switch S1、S4Turn on and S2、S3Turn off, now output voltage VoThe output voltage V of direction and front stage convertergIdentical；When to determining voltage signal for bearing, switch S2、S3Turn on and S1、S4Turn off, now output voltage VoThe output voltage V of direction and front stage convertergOn the contrary。Replacing of output voltage positive-negative half-cycle is achieved by the alternate conduction switched。
Single cycle controller shown in Fig. 2 includes sample circuit, clock pulse generator, reset integrator and rest-set flip-flop so that this utility model facilitates implementation modularity。When clock signal arrives, integrator starts the voltage signal (V gatheredo1,Vo2…Voi…Von) be integrated, when arriving set-point, integrator is reset to zero, until restarting to be integrated when next clock signal arrives。Each concatenation unit all adopts independent one-cycle controller to be controlled, and in each concatenation unit, clock pulses misplaces T successivelys/ n time, wherein TsFor switch periods。For concatenation unit 1, the clock pulses phase shift of one-cycle controller is set to 0, and the Q end output of rest-set flip-flop is switch S11Switching signal g (S11)；For concatenation unit 2, the clock pulses phase shift of one-cycle controller is set to Ts/ n, the Q end output of rest-set flip-flop is switch S21Switching signal g (S21)；For concatenation unit i, the clock pulses phase shift of one-cycle controller is set to (i-1) Ts/ n, the Q end output of rest-set flip-flop is switch Si1Switching signal g (Si1)。N=3 in the present embodiment, it is achieved four level inverse conversion effects, in control, three cascade half-bridge cells clock pulses stagger T successivelysThe time of/3。
Fig. 3 show the control of rear class changer, by judging to the modulation signal of the positive and negative each switching tube obtaining the same brachium pontis of inverter upper and lower switching tube complementation conducting of determining voltage signal, wherein S1Switching signal be g (S1), S2Switching signal be g (S2), S3Switching signal be g (S3), S4Switching signal be g (S4)。Replacing of output voltage positive-negative half-cycle is achieved by the alternate conduction switched。
As Fig. 4 (a) and Fig. 4 (b) show the present embodiment under the application conditions of desirable constant dc source, based on the output voltage waveform of the two-stage type multi-electrical level inverter of Cycle Control。V in the present embodimentCDFor rear class inverter output voltage；VoBack loading output voltage is filtered for LC。
Fig. 5 (a) Fig. 5 (b)-Fig. 8 (a) Fig. 8 (b) is under DC source non-ideality: such as low frequency pulsating, (it is 5Hz that each concatenation unit DC source all adds a frequency, amplitude be 7V sinusoidal cycles interference) or input voltage imbalance (only concatenation unit 1 DC source add a frequency be 5Hz, amplitude is the sinusoidal cycles interference of 7V) time, multi-electrical level inverter of the present utility model adopts the output voltage waveforms of Cycle Control。In order to embody the advantage of Cycle Control, choose traditional SPWM and control as a comparison。From result it can be seen that at any non-ideality, Cycle Control all can export stable sinusoidal voltage, and the amplitude of the output voltage that traditional SPWM controls can fluctuate。
The output voltage V of Cycle Control is adopted as Fig. 5 (a) and Fig. 5 (b) show the multi-electrical level inverter of the present utility model when DC source contains low frequency pulsatingCDOutput waveform figure and LC filter back loading output voltage Vo。
The tradition SPWM output voltage V controlled is adopted as Fig. 6 (a) and Fig. 6 (b) show the multi-electrical level inverter of the present utility model when DC source contains low frequency pulsatingCDOutput waveform figure and LC filter back loading output voltage Vo。
As when Fig. 7 (a) and Fig. 7 (b) show DC source imbalance (only the DC voltage of concatenation unit 1 contains low frequency pulsating), multi-electrical level inverter of the present utility model adopts the output voltage V of Cycle ControlCDOutput waveform figure and LC filter back loading output voltage Vo。
As when Fig. 8 (a) and Fig. 8 (b) show DC source imbalance (only the DC voltage of concatenation unit 1 contains low frequency pulsating), multi-electrical level inverter of the present utility model adopts the tradition SPWM output voltage V controlledCDOutput waveform figure and LC filter back loading output voltage Vo。
The result of embodiment shows, when desirable DC source, Cycle Control and traditional SPWM control to reach the control effect of many level, obtain stable sinusoidal voltage waveform after LC filters, and waveform quality is good, meets the needs of converter applications。But when DC source exists non-ideality, the output voltage waveforms that traditional SPWM controls can instability even distort, and is no longer able to meet normal job demand。
This utility model prime cascade half-bridge converter is connected with rear class inverter circuit, can well realize many level staircase waveform of near sinusoidal, simplify the complexity of power cell system topological structure, decrease the usage quantity of insulated gate bipolar transistor, thus reducing cost, save cost；
This utility model Cycle Control is for the control of each half-bridge cells of prime, without high-precision sampling element, except accurately controlling, disturbance to DC side input voltage, including Voltage unbalance and voltage low frequency pulsating etc., there is good rejection ability, effectively solve the wave distortion problem existed in conventional modulated。
Above-described embodiment is this utility model preferably embodiment; but embodiment of the present utility model is also not restricted by the embodiments; other any without departing from the change made under spirit of the present utility model and principle, modification, replacement, combination, simplification; all should be the substitute mode of equivalence, be included within protection domain of the present utility model。
Claims (4)
1. a half-bridge cascade multilevel inverter, it is characterized in that, by front, rear class changer is in series, described front stage converter is made up of n half-bridge cells cascade, one end bridging DC source or electric capacity between two dc bus of each half-bridge cells, other end bridging half-bridge circuit, described half-bridge circuit is by insulated gate bipolar transistor and does not control Diode series and constitutes, the insulated gate bipolar transistor of described first half-bridge cells and do not control the junction point of diode and draw rear class changer input side terminal A, the DC source of the n-th half-bridge cells or electric capacity negative terminal draw the input side terminal B of rear class changer；The DC source of upper level half-bridge cells or electric capacity negative terminal and next stage insulated gate bipolar transistor and do not control diode junction point be connected。
2. a kind of half-bridge cascade multilevel inverter according to claim 1, it is characterised in that described rear class changer is single-phase full bridge inverter circuit。
3. a kind of half-bridge cascade multilevel inverter according to claim 2, it is characterised in that described single-phase full bridge inverter circuit is specifically made up of four full-control type power electronic switches。
4. a kind of half-bridge cascade multilevel inverter according to claim 1, it is characterised in that also including LC wave filter, described LC wave filter is connected with rear class changer。
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| CN201521035748.1U CN205336145U (en) | 2015-12-11 | 2015-12-11 | Half -bridge cascades many inverter of type |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105450063A (en) * | 2015-12-11 | 2016-03-30 | 华南理工大学 | Half-bridge cascaded multi-level inverter and control method |
| CN109149980A (en) * | 2017-06-19 | 2019-01-04 | 华北电力大学 | A kind of change submodule output voltage polar circuit |
| CN111464064A (en) * | 2020-05-09 | 2020-07-28 | 湖南人文科技学院 | Multilevel DC link inverter and harmonic suppression method thereof |
-
2015
- 2015-12-11 CN CN201521035748.1U patent/CN205336145U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105450063A (en) * | 2015-12-11 | 2016-03-30 | 华南理工大学 | Half-bridge cascaded multi-level inverter and control method |
| CN109149980A (en) * | 2017-06-19 | 2019-01-04 | 华北电力大学 | A kind of change submodule output voltage polar circuit |
| CN111464064A (en) * | 2020-05-09 | 2020-07-28 | 湖南人文科技学院 | Multilevel DC link inverter and harmonic suppression method thereof |
| CN111464064B (en) * | 2020-05-09 | 2021-06-04 | 湖南人文科技学院 | Harmonic suppression method of multilevel DC link inverter |
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