CN204216795U - For the elementary cell of multi-level converter, three level and m level topological structure - Google Patents

Abstract

The utility model discloses a kind of elementary cell for multi-level converter, comprise insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, between insulated gate bipolar transistor both sides and two diodes, draw three terminals.This elementary cell possesses three terminals, can form three kinds of dissimilar bidirectional current paths, can solve the problem that in existing structure elementary cell, current path is single, more easily form many level.Also disclose a kind of three-level topology structure, this structure number of devices used is few, and output level number is many, has the voltage stress that traditional T-shaped three-level structure is identical, can solve traditional two level block for the low problem of large-power occasions switching frequency.The m level topological structure also disclosed, this structure eliminates clamping devices a large amount of in the many level block of diode clamp, and can solve the unbalanced problem of loss in Clamp many level topological structure.

Description

Basic cell, three-level and m-level topologies for multilevel converters

technical field

The utility model belongs to the technical field of electric engineering, power electronics and motor application, and specifically relates to a basic unit, a three-level and an m-level topological structure for a multilevel converter.

Background technique

At present, the voltage source two-level topology inverter system has been widely used in many industrial fields such as motor drive, rail transit, and electric energy conversion. However, this topology inverter system withstands high voltage stress and large dv/dt , High harmonic distortion rate of output current, large volume of output filter and other limitations.

Using the voltage source type multi-level topology inverter system can well solve the shortcomings brought about by the two-level converter. However, in several types of traditional multi-level inverter systems, different multi-level topologies not only have the maximum number of output levels that can only be odd, but also have specific disadvantages: (1) Diode-clamped multi-level topology Although the structure uses fewer switching devices, the loss of different power devices in the same bridge arm is uneven, and the degree of modularization is weak, requiring a large number of clamping diodes. (2) Flying-capacitor-type multilevel topology uses fewer switching devices, but requires a large number of flying-capacitors. (3) The cascaded H-bridge multi-level topology requires many switching devices and an isolated DC voltage source. (4) Active clamp type and P2 general-purpose multilevel topology: Although it can solve the power loss imbalance problem of the diode clamp type multilevel converter, and has the advantages of modularization, but it contains many switching devices .

In medium and low voltage applications, considering the multiplication of cost, two-level topology is usually adopted, and the corresponding performance index is achieved by increasing the switching frequency and adopting output filtering measures. This method has the advantages of large loss, low efficiency, and size Big and other shortcomings.

In medium-high voltage and high-power applications, when using the topologies (1)-(3) above, problems caused by a large number of flying capacitors, a large number of clamping diodes, and a large number of isolated DC power supplies have to be solved. However, if the active clamp type or P2 general-purpose multi-level topology is adopted, the increase of switching devices will not only increase the complexity of system control, but also lead to an increase in the number of driving circuits and buffer circuits, as well as an increase in cost.

Compared with the traditional two-level inverter topology, the new simplified diode-clamped three-level topology reduces the complexity of the system, but has the traditional I-type three-level inverter output current harmonic distortion rate is small, dv /dt is small, and has the same voltage stress as the traditional T-type three-level. The simplified diode-clamped three-level topology has two optional evolution topologies, both of which use active commutation, which can be used to solve the power loss imbalance problem.

Compared with the traditional multi-level converter topology, the general-purpose multi-level converter topology proposed by the utility model has a high degree of modularization, good scalability, a small number of switching devices, and a simple structure, which can solve the problem of power loss. Balance issues, and retain the advantages of traditional multilevel converters.

Utility model content

Technical problem: The technical problem to be solved by this utility model is: to provide a basic unit for a multilevel converter, the basic unit has three terminals, which can form three different types of bidirectional current paths, which can solve the existing The problem of a single current path in the basic unit of the structure makes it easier to form multiple levels. It also provides a three-level topology based on the above-mentioned basic unit. This structure uses a small number of devices and a large number of output levels. It has the same voltage stress as the traditional T-type three-level structure, and can solve the traditional two-level structure for large Low switching frequency, high current harmonic distortion rate, large output filter, unbalanced loss and other issues in power applications; and provide an m-level topology based on the above-mentioned basic unit, which eliminates the need for a diode-clamped multi-level structure There are a large number of clamping devices in it, and it can solve the problem of unbalanced loss in the clamping multilevel topology, and has higher fault tolerance. This structure can also solve the problem of a large number of independent power supplies and flying capacitors in the flying capacitor type and the cascaded multilevel structure. Due to the modular design of the structure, maintenance and installation costs can be reduced. Since the structure uses few power devices, the design of the modulation strategy can be simplified.

Technical solution: In order to solve the above-mentioned technical problems, the technical solution adopted in the utility model is:

A basic unit for a multilevel converter, the basic unit includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in series and antiparallel to both sides of the insulated gate bipolar transistor. Three terminals are drawn from both sides of the polar transistor and between the two diodes.

A three-level topology using the above-mentioned basic unit, the topology includes a first DC voltage source, a bus capacitor component and a first converter bridge arm; the bus capacitor component includes two bus capacitors connected in series, and the bus capacitor components are connected in parallel To the two ends of the first DC voltage source, the first DC voltage source is divided into three potentials: P potential, O potential and N potential by the bus capacitor component, wherein the O potential is located in the middle of the two bus capacitors, and the P potential is located in the DC voltage The positive pole of the source, the N potential is located at the negative pole of the DC voltage source; the bridge arm of the converter includes a P level unit, an O level unit and an N level unit, and the P level unit, O level unit and N level unit The basic unit structure is respectively adopted. The basic unit includes an insulated gate bipolar transistor and two diodes. The two diodes are connected in series and antiparallel to both sides of the IGBT. There are a first terminal and a second terminal, and a third terminal is provided between the two diodes; the first terminal of the O level unit is connected to the third terminal of the P level unit, and the third terminal of the O level unit The second terminal is connected to the third terminal of the N level unit, the third terminal of the O level unit is connected to the O potential; the first terminal of the P level unit is connected to the P potential, and the second terminal of the P level unit is connected to the O potential. The terminal is connected to the first terminal of the N level unit, and the second terminal of the N level unit is connected to the N potential; the output end of the first converter bridge arm is connected by the second terminal of the P level unit to the N potential. Lead out from the first terminal connection of the flat unit.

Further, the O-level unit also includes an IGBT; two IGBTs are connected in series to form a first IGBT assembly, and the two diodes in the O-level unit are connected in series Then reverse parallel to both sides of the first insulated gate bipolar transistor assembly, lead out the first terminal and the second terminal on both sides of the first insulated gate bipolar transistor component, and lead out the third connection between the two diodes The fourth terminal is drawn between the two IGBTs; the fourth terminal of the O-level unit is connected to the output terminal of the first converter bridge arm.

Further, the O-level unit also includes an IGBT; two IGBTs are connected in series to form a second IGBT component, and the two diodes in the O-level unit are connected in series Then reversely connect to both sides of the second insulated gate bipolar transistor assembly, draw the first terminal and the second terminal on both sides of the second insulated gate bipolar transistor assembly, and draw the third wiring between the two diodes The fourth terminal is drawn between the two insulated gate bipolar transistors; the fourth terminal of the O level unit is connected to the O potential.

An m-level topological structure containing the above basic unit, the topological structure includes a second converter bridge arm, a second diode series assembly, a second bus capacitor series assembly and a second DC voltage source; the second bus capacitor The series component is composed of m-1 bus capacitors connected in series, and the second bus capacitor series component is connected in parallel to both ends of the second DC voltage source, and the DC power is divided into m potential nodes, and the first to m potentials are located in the second bus capacitor series The connection point of the components, and the first potential is located at the positive pole of the second DC voltage source, and the mth potential is located at the negative pole of the second DC voltage source; the second diode series assembly includes 2m diodes, in the second diode series assembly The odd-numbered nodes of the second busbar capacitance series components are connected in turn to the 1st~m potential nodes; the second converter bridge arm includes m level layers, the first level layer contains a basic unit, and the mth level layer Contains m basic units, and the number of basic units contained in each level layer gradually increases by 1 as the number of layers increases; the basic unit includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in series and antiparallel to the insulated On both sides of the gate bipolar transistor, the first terminal and the second terminal are drawn on both sides of the insulated gate bipolar transistor, and the third terminal is drawn between the two diodes; in each level layer, the basic unit The first terminal of the basic unit is connected to the third terminal of a basic unit located in the next level layer, and the second terminal of the basic unit is connected to the third terminal of another basic unit located in the next level layer , the third terminal of the basic unit is connected to the first or second terminal of the basic unit in the previous level layer; the third terminal of the basic unit in the first level layer is connected to the first converter The output end of the bridge arm is connected; the first terminal and the second connection of the basic unit located at the mth level layer are respectively connected to the even-numbered potential nodes in the second diode series assembly; the value range of m is greater than 2 an integer of .

An m-level topological structure containing the above basic unit, the topological structure includes a third converter bridge arm, a third diode series assembly, a third bus capacitor series assembly and a third DC voltage source; the third bus capacitor The series component is composed of m-1 bus capacitors connected in series. The third bus capacitor series component is connected in parallel to both ends of the third DC voltage source, and the DC power is divided into m potential nodes. The first to m potentials are located in the third bus capacitor series connection. The connection point of the component, and the first potential is located at the positive pole of the third DC voltage source, and the mth potential is located at the negative pole of the third DC voltage source; the third diode series assembly includes 2m-4 diodes, located at the third diode The odd-numbered nodes in the series components are sequentially connected to the 2nd~m-1 potential nodes in the third bus capacitor series components; the third converter bridge arm includes m level layers, and the first level layer contains a basic unit, The mth level layer contains m basic units, and the number of basic units contained in each level layer gradually increases by one as the number of layers increases; the basic unit includes an insulated gate bipolar transistor and two diodes, and the two After two diodes are connected in series, they are antiparallel connected to both sides of the insulated gate bipolar transistor, the first terminal and the second terminal are drawn out on both sides of the insulated gate bipolar transistor, and the third terminal is drawn between the two diodes; In each level layer, the first terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer, and the second terminal of the basic unit is connected to another terminal in the next level layer. The third terminal of a basic unit is connected, the third terminal of the basic unit is connected to the first terminal or the second terminal of the basic unit in the previous level layer; the basic unit in the first level layer The third terminal is connected to the output terminal of the third converter bridge arm; the first terminal of the first basic unit located at the mth level layer is connected to the positive pole of the third DC voltage source, located at the mth level The second terminal of the mth basic unit of the layer is connected to the negative pole of the third DC voltage source, the second terminal of the first basic unit of the mth level layer, the first connection of the mth basic unit terminals, and the first terminal and the second connection of the 2nd to m-1 basic units are respectively connected to the even-numbered potential nodes in the third diode series assembly; the value range of m is an integer greater than 2.

An m-level topological structure containing the above basic unit, the topological structure includes a fourth converter bridge arm, a fourth diode series assembly, a fourth bus capacitor series assembly and a fourth DC voltage source; the fourth bus capacitor The series component is composed of m-1 bus capacitors connected in series, the fourth bus capacitor series component is connected in parallel to both ends of the fourth DC voltage source, and the DC power is divided into m potential nodes, and the 1st to m potentials are located in the fourth bus capacitor series The connection point of the components, and the first potential is located at the positive pole of the fourth DC voltage source, and the mth potential is located at the negative pole of the fourth DC voltage source; the fourth diode series assembly includes 2m diodes, and in the fourth diode series assembly The odd-numbered nodes of the fourth busbar capacitance series component are connected in turn to the 1st~m potential nodes; the fourth converter bridge arm includes m level layers, the first level layer contains a basic unit, and the mth level layer Contains m basic units, the number of basic units contained in each level layer gradually increases by 1 as the number of layers increases, and the 2nd to k-1 basic units in the 3rd to m-1 level layers The insulated gate bipolar transistor is removed, and k represents the number of level layers; the basic unit includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in parallel to the two insulated gate bipolar transistors in series. On the side of the IGBT, the first terminal and the second terminal are drawn on both sides of the IGBT, and the third terminal is drawn between the two diodes; in each level layer, the first terminal of the basic unit and the The third terminal of a basic unit located in the next level layer is connected, the second terminal of the basic unit is connected with the third terminal of another basic unit located in the next level layer, and the third terminal of the basic unit The terminal is connected to the first terminal or the second terminal of the basic unit located in the upper level layer; the third terminal of the basic unit located in the first level layer is connected to the output terminal of the fourth converter bridge arm ; The first connection terminal and the second connection of the basic unit located in the mth level layer are respectively connected to the even-numbered potential nodes in the fourth diode series assembly; the value range of m is an integer greater than 2.

An m-level topology structure containing the above-mentioned basic unit, the topology structure includes a fifth converter bridge arm, a fifth diode series assembly, a fifth bus capacitor series assembly, and a fifth DC voltage source; the fifth bus capacitor The series component is composed of m-1 bus capacitors connected in series, the fifth bus capacitor series component is connected in parallel to both ends of the fifth DC voltage source, and the DC power is divided into m potential nodes, and the first to m potentials are located in the fifth bus capacitor series The connection point of the component, and the first potential is located at the positive pole of the fifth DC voltage source, and the mth potential is located at the negative pole of the fifth DC voltage source; the fifth diode series assembly includes 2m diodes, and in the fifth diode series assembly The odd-numbered nodes of the fifth bus capacitor series components are connected in turn to the 1st~m potential nodes; the fifth converter bridge arm includes m-1 level layers, and the first and second level layers are two-level basic units. The third level layer contains 3 basic units, and the mth level layer contains m basic units. From the 4th to m level layers, the number of basic units contained in each level layer increases with the number of layers Gradually increase by 1; the basic unit includes an IGBT and two diodes, the two diodes are connected in series and antiparallel to both sides of the IGBT, and are drawn out on both sides of the IGBT The first connection terminal and the second connection terminal lead out the third connection terminal between the two diodes; the two-level basic unit includes two insulated gate bipolar transistors and two diodes, and the two diodes are connected in series to reverse connected in parallel to both sides of the two insulated gate bipolar transistors in series, the first terminal and the second terminal are drawn out on both sides of the insulated gate bipolar transistor, the third terminal is drawn between the two diodes, and the The middle connection point of the series diode is connected to the middle connection point of the series insulated gate bipolar transistor; the first terminal of the two-level basic unit is connected to the third terminal of the first basic unit of the third level layer, and the two The second terminal of the level basic unit is connected to the third terminal of the second basic unit of the third level layer, and the third terminal of the two-level basic unit is connected to the third basic unit of the third level layer The third terminal of the converter bridge arm is connected to the third terminal of the two-level basic unit; in the 4th to m level layers, the first terminal of the basic unit is located at the next level The third terminal of a basic unit in the layer is connected, the second terminal of the basic unit is connected to the third terminal of another basic unit in the next level layer, the third terminal of the basic unit is connected to the The first connection terminal or the second connection terminal of the basic unit in a level layer is connected; Potential node connection; the value range of m is an integer greater than 2.

Beneficial effects: compared with the prior art, the utility model has the following beneficial effects:

1. Since the utility model adopts an insulated gate bipolar transistor and a double anti-parallel diode as basic components, it constitutes a bidirectional current flow path and has bidirectional power transmission capability.

2. The new simplified diode-clamped three-level converter topology in the utility model has fewer switching devices, and has the same performance as the traditional three-level converter, and has a lower output current THD than the traditional two-level converter topology .

3. In this utility model, the topology structure of the novel active clamp type three-level converter evolved from the topology structure of the new simplified diode clamp type three-level converter has the ability to balance the distribution of power loss, reducing the impact of harsh working conditions on the system adverse effects, improve system utilization and maximum output capacity.

4. The topology of the general-purpose multilevel converter in the utility model is only composed of a basic unit, a series diode assembly, a series bus capacitor assembly, and a DC power supply. The topology is simple, the expansion performance is good, and the degree of modularization is high.

5. The general-purpose multilevel converter topology of the present invention has system self-redundancy, and can be used for equalizing power loss distribution and fault-tolerant processing after a fault. In the multilevel converter topology that can achieve the same function, the topology uses fewer switching devices.

6. The general-purpose multilevel converter topology of the present invention can further reduce the number of switching devices and diodes through optimization, reducing cost and system complexity.

Description of drawings

Fig. 1 is the structural representation of basic unit in the utility model.

Fig. 2 is a structural schematic diagram of the first three-level topology proposed by the present invention.

FIG. 3 is a schematic diagram of the current path at P level in the first three-level topology proposed by the present invention.

FIG. 4 is a schematic diagram of the current path at O level in the first three-level topology proposed by the present invention. Schematic diagram of the structure.

FIG. 5 is a schematic diagram of the current path at N level in the first three-level topology proposed by the present invention. Schematic diagram of the structure.

FIG. 6 is a schematic structural diagram of the second three-level topology proposed by the present invention.

FIG. 7 is a schematic structural diagram of the third three-level topology proposed by the present invention.

FIG. 8 is a schematic diagram of the current path when outputting O level in the second three-level topology proposed by the present invention.

FIG. 9 is a schematic diagram of the current path when outputting O level in the third three-level topology proposed by the present invention.

FIG. 10 is a diagram of the modulation method based on the stacked dual carrier of the first three-level topology of the present invention.

FIG. 11 is a schematic diagram of the first m-level converter topology of the present invention.

FIG. 12 is a schematic diagram of the second m-level converter topology of the present invention.

FIG. 13 is a schematic diagram of the third m-level converter topology of the present invention.

FIG. 14 is a schematic diagram of the fourth m-level converter topology of the present invention.

FIG. 15 is a schematic diagram of the current path at P+ level in the topology of the first m-level converter of the present invention.

FIG. 16 is a schematic diagram of the current path at P-level in the topology of the first m-level converter of the present invention.

FIG. 17 is a schematic diagram of the current path at N+ level in the topology of the first m-level converter of the present invention.

FIG. 18 is a schematic diagram of the current path at N-level in the topology of the first m-level converter of the present invention.

FIG. 19 is a schematic diagram of the current path at the O1 level in the topology of the first m-level converter of the present invention.

FIG. 20 is a schematic diagram of the current path at the O2 level in the topology of the first m-level converter of the present invention.

Fig. 21 is a diagram of the first modulation method based on the stacked dual-carrier topology of the first m-level converter of the present invention.

Fig. 22 is a diagram of the second modulation method based on the stacked dual-carrier topology of the first m-level converter of the present invention.

Detailed ways

The utility model is described in detail below in conjunction with specific examples. The following examples will help those skilled in the art to further understand the utility model, but do not limit the utility model in any form. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present utility model. These all belong to the protection domain of the present utility model.

Referring to Fig. 1, the basic unit used for the multilevel converter of the present invention includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in series and antiparallel to both sides of the insulated gate bipolar transistor. Three terminals are drawn out from both sides of the insulated gate bipolar transistor and between the two diodes.

The working process of the basic unit is: when the basic unit and the IGBTs in the basic unit connected to its first terminal are all turned on, the current from the unit connected to its first terminal will flow from the first terminal The terminal flows into the insulated gate bipolar transistor, and flows out of the third terminal through the lower diode to form a forward path of current; the current flows from the third terminal into the upper diode, and flows from the first terminal into its first terminal Connected cells form a reverse path for current flow. Similarly, when both the basic unit and the IGBT in the basic unit connected to the second terminal are turned on, the current will form a bidirectional path between the second and third terminals. In addition, if there is no current flowing in and out of the third terminal, the basic unit can degenerate into a basic unit of the existing structure, forming a bidirectional path of current between the first and second terminals. Compared with the single current path in the basic unit of the existing structure, the basic unit has three kinds of current paths, and it is easier to realize multi-level output.

Referring to FIG. 2 , the first three-level topology of the present invention includes a first DC voltage source 11 , a bus capacitor assembly 12 and a first converter bridge arm 13 . The bus capacitor assembly 12 includes two bus capacitors connected in series. The bus capacitor assembly 12 is connected in parallel to the two ends of the first DC voltage source 11. The first DC voltage source 11 is divided into P potential, O potential and N potential by the bus capacitor assembly 12. Among them, the O potential is located in the middle of the two bus capacitors, the P potential is located at the positive pole of the DC voltage source 11, and the N potential is located at the negative pole of the DC voltage source 12; the converter bridge arm 13 includes a P level unit 14, an O level unit The unit 15 and the N level unit 16, the P level unit 14, the O level unit 15 and the N level unit 16 respectively adopt a basic unit structure, and the basic unit includes an insulated gate bipolar transistor and two diodes , two diodes are connected in series and antiparallel to both sides of the IGBT, a first terminal and a second terminal are provided on both sides of the IGBT, and a third terminal is provided between the two diodes end. The first terminal of the O level unit 15 is connected to the third terminal of the P level unit 14, the second terminal of the O level unit 15 is connected to the third terminal of the N level unit 16, and the O level unit The third terminal of 15 is connected to O potential; the first terminal of P level unit 14 is connected to P potential, the second terminal of P level unit 14 is connected to the first terminal of N level unit 16, N The second terminal of the level unit 16 is connected to the N potential; the output terminal of the first converter bridge arm 13 is drawn from the connection between the second terminal of the P level unit 14 and the first terminal of the N level unit 16 .

Referring to Figure 3-Figure 5, the working process of the above-mentioned three-level topology is as follows: as shown in Figure 3, when the IGBT S2 in the P-level unit is turned on, the current will flow through its first and second wirings. A bidirectional path is formed between the terminals, and the output potential of the bridge arm will therefore be equal to the P potential. As shown in Figure 4, when the insulated gate bipolar transistor S1 in the O-level unit is turned on, the current will form a bidirectional path between its third terminal and the output terminal of the bridge arm, and the output potential of the bridge arm will therefore be equal to O potential. As shown in FIG. 5 , when the IGBT S3 in the N-level unit is turned on, the current will form a bidirectional path between its first and second terminals, and the output potential of the bridge arm will therefore be equal to the N potential. By controlling the different switching states of S1, S2, and S3, the output of the bridge arm can have three different potential states. While reducing the number of power devices, the three-level basic function is realized, the harmonic distortion rate of the output current is reduced, and the equivalent switching frequency is increased.

The first stacked dual-carrier modulation method with a three-level topology is shown in FIG. 10 . The modulated wave signal 43 is compared with the two carrier signals of the upper and lower carrier signals 41 and 42 . When the modulated wave signal 43 is greater than the upper carrier signal 41, the control S2 is turned on. When the modulating wave signal 43 is smaller than the downloading wave signal 42, the control S3 is turned on. The state of S1 is obtained by the state of S2 and S3 through the NOR gate. All devices follow the principle of "turn off first and then turn on" to set the dead zone. In the implementation, the rising edge delay method can be used to realize the dead zone function.

Referring to Fig. 6, the second three-level topological structure provided by the utility model is the same as the first three-level topological structure, the difference is that the O level unit 15 also includes an insulated gate bipolar Transistor: two insulated gate bipolar transistors are connected in series to form a first insulated gate bipolar transistor assembly 17, and the two diodes in the O-level unit 15 are connected in series and antiparallel to the first insulated gate bipolar transistor assembly 17 On both sides of the first insulated gate bipolar transistor assembly 17, the first terminal and the second terminal are drawn out, the third terminal is drawn between the two diodes, and the second terminal is drawn between the two insulated gate bipolar transistors. Fourth connection terminal: The fourth connection terminal of the O level unit 15 is connected to the output terminal of the first converter bridge arm 13 .

8, the working process of the second three-level topology is: when the two IGBTs S1 _H and S1 _L in the first IGBT assembly 17 are turned on, the current will be at A bidirectional path is formed between the second and fourth terminals. Since the output terminal of the bridge arm is connected to the second terminal, the output potential of the bridge arm will be equal to O potential. Compared with the first three-level topology structure, when this structure outputs O level, the current will no longer pass through the P and N level unit devices, thus reducing the conduction and switching losses of the P and N level unit devices. Loss distribution is more even.

Referring to Fig. 7, the third three-level topological structure provided by the utility model is the same as the first three-level topological structure, the difference is that the O level unit 15 also includes an insulated gate bipolar Transistor: two insulated gate bipolar transistors are connected in series to form a second insulated gate bipolar transistor assembly 18, and the two diodes in the O-level unit 15 are connected in series and antiparallel to the second insulated gate bipolar transistor assembly 18 On both sides of the second insulated gate bipolar transistor assembly 18, the first terminal and the second terminal are drawn out, the third terminal is drawn between the two diodes, and the second terminal is drawn between the two insulated gate bipolar transistors. Fourth terminal; O level The fourth terminal of the unit 15 is connected to the O potential.

9, the working process of the third three-level topology is: when the two IGBTs S1 _H and S1 _L in the second IGBT assembly 18 are turned on, the current will be at A bidirectional path is formed between the second terminal and the output terminal of the bridge arm, and the output potential of the bridge arm will be equal to O potential. Compared with the first three-level topology, when this structure outputs O level, the current will no longer pass through the diode device in the O level unit, thus reducing the conduction and reverse recovery loss of the O level unit device , which will make the losses more evenly distributed when the converter is at low output voltage.

Referring to Fig. 11, the first m-level topology provided by the present invention includes a second converter bridge arm 501, a second diode series assembly 502, a second bus capacitor series assembly 503 and a second DC voltage source 504 ; The second bus capacitor series component 503 is composed of m-1 bus capacitors in series, the second bus capacitor series component 503 is connected in parallel to both ends of the second DC voltage source 504, and the DC power is divided into m potential nodes, the first to The m potential is located at the connection point of the second bus capacitor series assembly 503, and the first potential is located at the positive pole of the second DC voltage source 504, and the mth potential is located at the negative pole of the second DC voltage source 504; the second diode series assembly 502 includes 2m diodes, the odd-numbered nodes in the second diode series component 502 are sequentially connected to the 1st to m potential nodes of the second bus capacitor series component 503; the second converter bridge arm 501 includes m level layers, the 1st The first level layer contains one basic unit, the mth level layer contains m basic units, and the number of basic units contained in each level layer gradually increases by one as the number of layers increases. The basic unit includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in antiparallel to both sides of the insulated gate bipolar transistor in series, and the first terminal and the The second connection terminal leads out the third connection terminal between the two diodes. In each level layer, the first terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer, and the second terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer. The third terminal of another basic unit is connected, and the third terminal of the basic unit is connected to the first or second terminal of the basic unit in the previous level layer; the basic unit located in the first level layer The third connection end of the first converter bridge arm 501 is connected to the output end of the first converter bridge arm 501; Potential node connection; the value range of m is an integer greater than 2.

The working process of the above-mentioned m-level topology is: taking three-level as an example (m=3), as shown in Figure 15, when the IGBTs S1, S2, and S4 in the topology are turned on, the current The first diode of the diode series assembly (502) from the first potential node flows into the first terminal of the first basic unit of the third level layer, and then, the current flows out of the first basic unit of the third level layer in sequence The third terminal flows into the first terminal of the first basic unit of the second level layer, and the current flows out of the third terminal of the first basic unit of the second level layer and flows into the first terminal of the first basic unit of the first level layer. A terminal. Finally, the current flows out from the third terminal of the first basic unit of the first level layer, forming a forward path of the current. As shown in Figure 16, when the current flows into the third terminal of the first basic unit of the first level layer, the current will pass through the first terminal of the first basic unit of the first level layer, the first terminal of the first basic unit of the second level layer, and the second terminal of the second level layer. The first terminal of a basic unit and the second terminal of the first basic unit of the third level flow through the diode series component 502 and flow into the first potential, forming a reverse path of current. Therefore, when the IGBTs S1 , S2 , and S4 are turned on, the output potential of the bridge arm is equal to the first potential. Similarly, as shown in FIGS. 17-18 , when the IGBTs S1 , S3 , and S6 are turned on, the output potential of the bridge arm is equal to the third potential. As shown in FIG. 19 , when the IGBTs S2 , S3 , and S5 are turned on, the output potential of the bridge arm is equal to the second potential. As shown in FIG. 20 , when the IGBTs S1 and S5 are turned on, the output potential of the bridge arm is equal to the second potential. The structure is simple and compact, the number of components used is small, there is no clamping device, independent power supply and flying capacitor, and there are two ways to output the second potential, which can be used to solve the problem of unbalanced loss and fault tolerance under fault conditions. In addition, the structure adopts a modular design, which can reduce the cost of installation and maintenance.

Referring to Fig. 12, the second m-level topology structure includes a third converter bridge arm 601, a third diode series component 602, a third bus capacitor series component 603, and a third DC voltage source 604; the third bus capacitor The series component 603 is composed of m-1 busbar capacitors connected in series. The third busbar capacitor series component 603 is connected in parallel to both ends of the third DC voltage source 604, and divides the DC power supply into m kinds of potential nodes. The first to m potentials are located in the third The connection point of the bus capacitor series assembly 603, and the first potential is located at the positive pole of the third DC voltage source 604, and the mth potential is located at the negative pole of the third DC voltage source 604; the third diode series assembly 602 includes 2m-4 diodes , the odd-numbered nodes in the third diode series assembly 602 are sequentially connected to the 2nd~m-1 potential nodes in the third bus capacitor series assembly 503;

The third converter bridge arm 601 includes m level layers, the first level layer contains one basic unit, the mth level layer contains m basic units, and the number of basic units contained in each level layer varies with the layer The number increases gradually by 1. The basic unit includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in antiparallel to both sides of the insulated gate bipolar transistor in series, and the first terminal and the The second connection terminal leads out the third connection terminal between the two diodes. In each level layer, the first terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer, and the second terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer. The third terminal of another basic unit is connected, and the third terminal of the basic unit is connected to the first or second terminal of the basic unit in the previous level layer; the basic unit located in the first level layer The third connection terminal of the third converter bridge arm 601 is connected to the output terminal of the third converter bridge arm 601; the first connection terminal of the first basic unit located in the mth level layer is connected to the positive pole of the third DC voltage source 604, and is located in the mth level layer. The second terminal of the mth basic unit of the first level layer is connected to the negative pole of the third DC voltage source 604, and is located at the second terminal of the first basic unit of the mth level layer, the mth basic unit The first terminal of the , and the first terminal and the second connection of the 2nd to m−1 basic units are respectively connected to the even-numbered potential nodes in the third diode series assembly 602 . The value range of m is an integer greater than 2.

The working process of the above-mentioned second m-level topology structure is: similar to the working process of the first m-level topology structure, controlling the switch state of the IGBT in the bridge arm of the converter can make the output of the bridge arm corresponding potential. Different from the first m-level topology structure, when the bridge arm outputs the first potential, the current no longer passes through the first and second diodes of the series diode assembly 502, but directly flows from the first basic unit of the m-th level layer. The first terminal flows into or out of a first potential. Similarly, when the bridge arm outputs the first potential, the current no longer passes through the 2m-1, 2m-th diodes of the series diode assembly 502, but directly flows into or out of the second terminal of the m-th basic unit of the m-th level layer. m potential. This topology further reduces the number of components, and maintains all the functions of the first structure, and can also be used to solve the problem of wear leveling and fault tolerance under faults. Different from the first m-level topology, the four outermost diodes in the series diode assembly in the second m-level topology are removed, and the outermost of the bus capacitor series assembly is directly connected to the first bridge arm of the converter. The outermost basic structural units of the m-level layer are connected.

Referring to FIG. 13, the third m-level topology structure includes a fourth converter bridge arm 701, a fourth diode series assembly 702, a fourth bus capacitor series assembly 703, and a fourth DC voltage source 704; the fourth bus capacitor The series component 703 is composed of m-1 busbar capacitors connected in series. The fourth busbar capacitor series component 703 is connected in parallel to both ends of the fourth DC voltage source 704, and divides the DC power supply into m kinds of potential nodes. The first to m potentials are located in the fourth The connection point of the bus capacitor series assembly 703, and the first potential is located at the positive pole of the fourth DC voltage source 704, and the mth potential is located at the negative pole of the fourth DC voltage source 704; the fourth diode series assembly 702 includes 2m diodes, and the mth potential is located at the negative pole of the fourth DC voltage source 704; The odd-numbered nodes in the four-diode series assembly 702 are sequentially connected to the 1st~m potential nodes of the fourth bus capacitor series assembly 703; the fourth converter bridge arm 701 includes m level layers, and the first level layer includes A basic unit, the mth level layer contains m basic units, the number of basic units contained in each level layer gradually increases by 1 as the number of layers increases, and the 3rd to m-1th level layers The insulated gate bipolar transistors in the basic units from 2 to k-1 are removed, and k represents the number of level layers where they are located. The basic unit includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in antiparallel to both sides of the insulated gate bipolar transistor in series, and the first terminal and the The second connection terminal leads out the third connection terminal between the two diodes. In each level layer, the first terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer, and the second terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer. The third terminal of another basic unit is connected, and the third terminal of the basic unit is connected to the first or second terminal of the basic unit in the previous level layer; the basic unit located in the first level layer The third connection end of the fourth converter bridge arm 701 is connected to the output end of the fourth converter bridge arm 701; Potential node connections. The value range of m is an integer greater than 3.

The working process of the above-mentioned third m-level topology structure is: similar to the working process of the first m-level topology structure, controlling the switch state of the IGBT in the bridge arm of the converter can make the output of the bridge arm corresponding potential. Different from the first m-level topology, this structure has a unique way of outputting the intermediate potential. The topological structure adopts the least number of devices, and can realize the most basic requirement of m-level while reducing the cost. Due to the reduction in the number of components, the structure will no longer have the function of wear leveling and fault tolerance under fault. In this structure the inner IGBTs (S5, S8, S9) of the converter legs are removed. This structure will not have wear leveling function.

Referring to Fig. 14, the fourth m-level topology structure includes the fifth converter bridge arm 801, the fifth diode series component 802, the fifth bus capacitor series component 803 and the fifth DC voltage source 804; the fifth bus capacitor The series component 803 is composed of m-1 bus capacitors connected in series. The fifth bus capacitor series component 803 is connected in parallel to both ends of the fifth DC voltage source 804, and divides the DC power supply into m potential nodes. The first to m potentials are located at the fifth The connection point of the bus capacitor series component 803, and the first potential is located at the positive pole of the fifth DC voltage source 804, and the mth potential is located at the negative pole of the fifth DC voltage source 804; the fifth diode series component 802 includes 2m diodes, and the The odd-numbered nodes in the five-diode series component 802 are sequentially connected to the 1st~m potential nodes of the fifth bus capacitor series component 803; the fifth converter bridge arm 801 includes m-1 level layers, the first and second The level layer is a two-level basic unit 81, the third level layer contains 3 basic units, the m level layer contains m basic units, and from the 4th to m level layers, each level The number of basic units contained in a layer gradually increases by 1 as the number of layers increases. The basic unit includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in antiparallel to both sides of the insulated gate bipolar transistor in series, and the first terminal and the The second connection terminal leads out the third connection terminal between the two diodes. The two-level basic unit 81 includes two insulated gate bipolar transistors and two diodes, and the two diodes are connected in antiparallel to both sides of the two insulated gate bipolar transistors in series. The first terminal and the second terminal are drawn from both sides of the type transistor, the third terminal is drawn between the two diodes, and the middle connection point of the series diode is connected with the middle connection point of the series insulated gate bipolar transistor. The first terminal of the two-level basic unit 81 is connected to the third terminal of the first basic unit of the third level layer, and the second terminal of the two-level basic unit 81 is connected to the third terminal of the third level layer. 2. The third terminal of the basic unit is connected, and the third terminal of the two-level basic unit 81 is connected to the third terminal of the third basic unit of the third level layer; The third terminal of the flat basic unit 81 leads out. In the 4th to m level layers, the first terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer, and the second terminal of the basic unit is connected to the second terminal of the basic unit in the next level. The third terminal of another basic unit in the layer is connected, and the third terminal of the basic unit is connected to the first or second terminal of the basic unit in the previous level layer; located in the mth level layer The first connection terminal and the second connection of the basic unit are respectively connected to the even-numbered potential nodes in the fifth diode series assembly 802 . The value range of m is an integer greater than 2.

The working process of the fourth m-level topology above is: similar to the working process of the first m-level topology, controlling the switch state of the IGBT in the bridge arm of the converter can make the output of the bridge arm corresponding potential. Different from the first m-level topology structure, when the current flows from the third level layer to the second level layer, the current will pass through the traditional cell structure 81 to form a forward path of the current. At the same time, when the current flows into the bridge arm from the output terminal, the current will flow into the third level layer through the traditional unit structure 81, forming a reverse path of the current. This topology reduces the number of IGBT devices, and retains all the functions of the first structure while reducing costs and simplifying control, and can also be used to solve the problem of wear leveling and fault tolerance under faults. In this structure, the insulated gate bipolar transistor (S1) in the bridge arm 501 of the "pyramid" type converter is removed, and the basic structural unit of the second layer is replaced with an ordinary "IGBT+antiparallel diode" unit. This fabric wear-leveling functionality will be reduced.

Figure 21 and Figure 22 show the stacked dual-carrier modulation strategy when the first m-level topology converter outputs O level in two different ways: (1) As shown in Figure 21, in the first working mode Next, the modulated wave signal 1203 is compared with the two carrier signals of the upper and lower carrier signals 1201 and 1202 . When the modulated wave signal 1203 is greater than the upper carrier signal 1201, the IGBT S4 is controlled to be turned on and S3 is turned off. When the modulating wave signal 1203 is smaller than the downloading wave signal 1202, control S6 to turn on and S2 to turn off. The state of S1 is obtained by taking the exclusive OR of the states of S2 and S3, and S5 and S1 are complementary to conduction. The insulated gate bipolar transistors S1-S6 output corresponding levels according to the switching states shown in Table 1 ("1" means on, "0" means off). (2) As shown in FIG. 22 , in the second working mode, the modulated wave signal 1206 is compared with two carrier signals, the upper and lower carrier signals 1204 and 1205 . When the modulated wave signal 1206 is greater than the upper carrier signal 1204, control S2 and S4 to be turned on. When the modulating wave signal 1206 is smaller than the downloading wave signal 1205, control S3 and S6 to be turned on. The state of S5 is obtained by NORing the states of S2 and S3, and S1 is always in the conducting state. The insulated gate bipolar transistors S1-S6 output corresponding levels according to the switching states shown in Table 2. All devices follow the principle of "turn off first and then turn on" to set the dead zone. In the implementation, the rising edge delay method can be used to realize the dead zone function.

Table 1 Switching states of the first m-level topology when outputting different levels in the first working mode

S1 S2 S3 S4 S5 S6 output level 1 1 0 1 0 0 P 1 0 1 0 0 1 N 0 1 1 0 1 0 O2

Table 2 Switching states of the first m-level topology when outputting different levels in the second working mode

S1 S2 S3 S4 S5 S6 output level 1 1 0 1 0 0 P 1 0 1 0 0 1 N 1 0 0 0 1 0 O1

The specific implementation of the utility model has been described above. It should be understood that the utility model is not limited to the above-mentioned specific embodiments, and those skilled in the art can make various deformations or modifications within the scope of all requirements, which does not affect the essence of the utility model.

Claims (8)

1. A basic unit for a multilevel converter, characterized in that the basic unit includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in parallel to the two insulated gate bipolar transistors in series On the side, three terminals are drawn between both sides of the IGBT and the two diodes. 2. A three-level topology using the basic unit according to claim 1, characterized in that the topology comprises a first DC voltage source (11), a bus capacitor assembly (12) and a first converter bridge arm (13); the bus capacitor assembly (12) comprises two bus capacitors connected in series, the bus capacitor assembly (12) is connected in parallel to the two ends of the first DC voltage source (11), and the first DC voltage source (11) is composed of the bus capacitor assembly (12) Separate three potentials of P potential, O potential and N potential, wherein, O potential is located in the middle of the two bus capacitors, P potential is located at the positive pole of the DC voltage source (11), and N potential is located at the DC voltage source (12) The negative pole of the converter bridge arm (13) comprises P level unit (14), O level unit (15) and N level unit (16), and described P level unit (14), O level unit (15) and N-level unit (16) respectively adopt a basic unit structure, the basic unit includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in antiparallel to both sides of the insulated gate bipolar transistor in series , a first terminal and a second terminal are provided on both sides of the insulated gate bipolar transistor, and a third terminal is provided between the two diodes; The first terminal of the O level unit (15) is connected to the third terminal of the P level unit (14), and the second terminal of the O level unit (15) is connected to the third terminal of the N level unit (16). The terminals are connected, the third terminal of the O level unit (15) is connected to the O potential; the first terminal of the P level unit (14) is connected to the P potential, and the second terminal of the P level unit (14) It is connected with the first terminal of the N level unit (16), and the second terminal of the N level unit (16) is connected with the N potential; the output end of the first converter bridge arm (13) is controlled by the P level unit ( 14) and the first connection terminal of the N-level unit (16) are connected. 3. according to the described three-level topological structure of claim 2, it is characterized in that, described O level unit (15) also comprises an insulated gate bipolar transistor; Two insulated gate bipolar transistors are connected in series to form In the first insulated gate bipolar transistor assembly (17), the two diodes in the O level unit (15) are connected in series and antiparallel to both sides of the first insulated gate bipolar transistor assembly (17), in the first The first terminal and the second terminal are drawn from both sides of the insulated gate bipolar transistor assembly (17), the third terminal is drawn between the two diodes, and the fourth terminal is drawn between the two insulated gate bipolar transistors; The fourth terminal of the O level unit (15) is connected to the output terminal of the first converter bridge arm (13). 4. according to the described three-level topological structure of claim 2, it is characterized in that, described O level unit (15) also comprises an insulated gate bipolar transistor; Two insulated gate bipolar transistors are connected in series to form In the second insulated gate bipolar transistor assembly (18), two diodes in the O level unit (15) are connected in series and antiparallel to both sides of the second insulated gate bipolar transistor assembly (18). The first terminal and the second terminal are drawn from both sides of the insulated gate bipolar transistor assembly (18), the third terminal is drawn between the two diodes, and the fourth terminal is drawn between the two insulated gate bipolar transistors; The fourth terminal of the O level unit (15) is connected to the O potential. 5. An m-level topological structure containing the basic unit according to claim 1, characterized in that the topological structure comprises a second converter bridge arm (501), a second diode series assembly (502), a first Two bus capacitor series components (503) and the second DC voltage source (504); the second bus capacitor series component (503) is composed of m-1 bus capacitors in series, and the second bus capacitor series component (503) is connected in parallel with the second The two ends of the DC voltage source (504) divide the DC power supply into m types of potential nodes, the first to m potentials are located at the connection point of the second bus capacitor series assembly (503), and the first potential is located at the second DC voltage source ( 504), the mth potential is located at the negative pole of the second DC voltage source (504); the second diode series assembly (502) includes 2m diodes, and the odd nodes in the second diode series assembly (502) are connected to The 1st~m potential nodes of the second bus capacitor series assembly (503) are connected in sequence; the second converter bridge arm (501) includes m level layers, the first level layer contains a basic unit, and the mth electric potential layer The flat layer contains m basic units, and the number of basic units contained in each level layer gradually increases by 1 as the number of layers increases; The basic unit includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in antiparallel to both sides of the insulated gate bipolar transistor in series, and the first terminal and the The second connection terminal leads the third connection terminal between the two diodes; In each level layer, the first terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer, and the second terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer. The third terminal of another basic unit is connected, and the third terminal of the basic unit is connected to the first or second terminal of the basic unit in the previous level layer; the basic unit located in the first level layer The third connection end of the first converter bridge arm (501) is connected to the output end; ) in the even-numbered potential nodes are connected; the value range of m is an integer greater than 2. 6. An m-level topological structure containing the basic unit according to claim 1, characterized in that the topological structure comprises a third converter bridge arm (601), a third diode series assembly (602), a first Three bus capacitor series components (603) and the third DC voltage source (604); the third bus capacitor series component (603) is composed of m-1 bus capacitors in series, and the third bus capacitor series component (603) is connected in parallel with the third The two ends of the DC voltage source (604) divide the DC power supply into m types of potential nodes, the first to m potentials are located at the connection point of the third bus capacitor series assembly (603), and the first potential is located at the third DC voltage source ( 604), the mth potential is located at the negative pole of the third DC voltage source (604); the third diode series assembly (602) includes 2m-4 diodes, located in the third diode series assembly (602) The odd-numbered nodes are sequentially connected to the 2nd to m-1 potential nodes in the third bus capacitor series assembly (603); The third converter bridge arm (601) includes m level layers, the first level layer contains a basic unit, the mth level layer contains m basic units, and the number of basic units contained in each level layer Gradually increase by 1 as the number of layers increases; The basic unit includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in antiparallel to both sides of the insulated gate bipolar transistor in series, and the first terminal and the The second connection terminal leads the third connection terminal between the two diodes; In each level layer, the first terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer, and the second terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer. The third terminal of another basic unit is connected, and the third terminal of the basic unit is connected to the first or second terminal of the basic unit in the previous level layer; the basic unit located in the first level layer The third connection terminal of the third converter bridge arm (601) is connected to the output terminal; the first connection terminal of the first basic unit located in the mth level layer is connected to the positive pole of the third DC voltage source (604) , the second terminal of the mth basic unit located at the mth level layer is connected to the negative pole of the third DC voltage source (604), and the second terminal of the first basic unit located at the mth level level , the first terminal of the m-th basic unit, and the first terminal and the second connection of the 2nd to m-1 basic units are respectively connected to the even-numbered potential nodes in the third diode series assembly (602); The value range of m is an integer greater than 2. 7. An m-level topological structure containing the basic unit according to claim 1, characterized in that the topological structure comprises a fourth converter bridge arm (701), a fourth diode series assembly (702), a fourth Four bus capacitor series components (703) and the fourth DC voltage source (704); the fourth bus capacitor series component (703) is composed of m-1 bus capacitors in series, and the fourth bus capacitor series component (703) is connected in parallel to the fourth The two ends of the DC voltage source (704) divide the DC power supply into m types of potential nodes, the first to m potentials are located at the connection point of the fourth bus capacitor series assembly (703), and the first potential is located at the fourth DC voltage source ( 704), the mth potential is located at the negative pole of the fourth DC voltage source (704); the fourth diode series assembly (702) includes 2m diodes, and the odd nodes in the fourth diode series assembly (702) are connected to The 1st to m potential nodes of the fourth bus capacitor series assembly (703) are connected in sequence; the fourth converter bridge arm (701) includes m level layers, the first level layer contains a basic unit, and the mth electric potential layer The flat layer contains m basic units, and the number of basic units contained in each level layer gradually increases by 1 as the number of layers increases, and the 2nd to k-1 basic units in the 3rd to m-1 level layers The insulated gate bipolar transistor in is removed, and k represents the number of level layers where it is located; The basic unit includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in antiparallel to both sides of the insulated gate bipolar transistor in series, and the first terminal and the The second connection terminal leads the third connection terminal between the two diodes; In each level layer, the first terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer, and the second terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer. The third terminal of another basic unit is connected, and the third terminal of the basic unit is connected to the first or second terminal of the basic unit in the previous level layer; the basic unit located in the first level layer The third connection end of the third connection terminal is connected with the output end of the fourth converter bridge arm (701); the first connection terminal and the second connection connection of the basic unit located at the mth level layer are respectively connected with the fourth diode series assembly (702 ) in the even-numbered potential nodes are connected; the value range of m is an integer greater than 2. 8. An m-level topological structure containing the basic unit according to claim 1, characterized in that the topological structure comprises a fifth converter bridge arm (801), a fifth diode series assembly (802), a first Five bus capacitor series components (803) and the fifth DC voltage source (804); the fifth bus capacitor series components (803) are composed of m-1 bus capacitors in series, and the fifth bus capacitor series components (803) are connected in parallel to the fifth The two ends of the DC voltage source (804) divide the DC power supply into m types of potential nodes, the first to m potentials are located at the connection point of the fifth bus capacitor series assembly (803), and the first potential is located at the fifth DC voltage source ( 804), the mth potential is located at the negative pole of the fifth DC voltage source (804); the fifth diode series assembly (802) includes 2m diodes, and the odd nodes in the fifth diode series assembly (802) are connected to The 1st~m potential nodes of the fifth bus capacitor series assembly (803) are connected in sequence; the fifth converter bridge arm (801) includes m-1 level layers, and the first and second level layers are two-level basic Unit (81), the third level layer contains 3 basic units, the mth level layer contains m basic units, from the 4th to m level layers, the basic units contained in each level layer The number gradually increases by 1 as the number of layers increases; The basic unit includes an insulated gate bipolar transistor and two diodes, and the two diodes are connected in antiparallel to both sides of the insulated gate bipolar transistor in series, and the first terminal and the The second connection terminal leads the third connection terminal between the two diodes; The two-level basic unit (81) includes two insulated gate bipolar transistors and two diodes, and the two diodes are connected in antiparallel to both sides of the two insulated gate bipolar transistors in series. The first terminal and the second terminal are drawn on both sides of the bipolar transistor, and the third terminal is drawn between the two diodes, and the middle connection point of the series diode is connected with the middle connection point of the series insulated gate bipolar transistor ; The first terminal of the two-level basic unit (81) is connected to the third terminal of the first basic unit of the third level layer, and the second terminal of the two-level basic unit (81) is connected to the third terminal of the third electrical level. The third terminal of the second basic unit of the flat layer is connected, and the third terminal of the two-level basic unit (81) is connected with the third terminal of the third basic unit of the third level layer; the bridge arm of the converter The third connection terminal of the output end two-level basic unit (81) of (801) is drawn; In the 4th to m level layers, the first terminal of the basic unit is connected to the third terminal of a basic unit in the next level layer, and the second terminal of the basic unit is connected to the second terminal of the basic unit in the next level. The third terminal of another basic unit in the layer is connected, and the third terminal of the basic unit is connected to the first or second terminal of the basic unit in the previous level layer; located in the mth level layer The first terminal and the second connection of the basic unit are respectively connected to the even-numbered potential nodes in the fifth diode series assembly (802); the value range of m is an integer greater than 2.