CN204216795U - For the elementary cell of multi-level converter, three level and m level topological structure - Google Patents
For the elementary cell of multi-level converter, three level and m level topological structure Download PDFInfo
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- CN204216795U CN204216795U CN201420741268.6U CN201420741268U CN204216795U CN 204216795 U CN204216795 U CN 204216795U CN 201420741268 U CN201420741268 U CN 201420741268U CN 204216795 U CN204216795 U CN 204216795U
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Abstract
The utility model discloses a kind of elementary cell for multi-level converter, comprise insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, between insulated gate bipolar transistor both sides and two diodes, draw three terminals.This elementary cell possesses three terminals, can form three kinds of dissimilar bidirectional current paths, can solve the problem that in existing structure elementary cell, current path is single, more easily form many level.Also disclose a kind of three-level topology structure, this structure number of devices used is few, and output level number is many, has the voltage stress that traditional T-shaped three-level structure is identical, can solve traditional two level block for the low problem of large-power occasions switching frequency.The m level topological structure also disclosed, this structure eliminates clamping devices a large amount of in the many level block of diode clamp, and can solve the unbalanced problem of loss in Clamp many level topological structure.
Description
Technical field
The utility model belongs to the technical field of electrician, power electronics, motor application, specifically, relates to for the elementary cell of multi-level converter, three level and m level topological structure.
Background technology
Current, voltage-source type two level topological structure inversion system has been widely used in numerous industrial circles such as motor driving, track traffic, electric energy conversion, but the limitation such as the inversion system of this topological structure bears that voltage stress is high, dv/dt is comparatively large, output current harmonics aberration rate is high, output filter volume is large.
Employing voltage-source type many level topological structure inversion system can solve the deficiency that two level converters bring well.But in several class multi-level inverse conversion of tradition system, different many level topological structures can only for except odd number except having the maximum level number of output, also there is specific shortcoming: (1) is although the switching device of diode-clamped many level topological structure employing is few, but same brachium pontis different capacity device loss is unbalanced, the degree of modularity is weak, needs a large amount of clamping diode.(2) switching device of striding capacitance type many level topological structure employing is few, but needs a large amount of striding capacitances.(3) Cascade H bridge type many level topological structure needs switching device many, and needs the direct voltage source of isolation.(4) active-clamp type and the universal many level topological structure of P2: although can solve the power loss imbalance problem of diode-clamped multi-level converter, and have the advantages such as modularization, contained switching device is many.
In mesolow application scenario, consider being multiplied of cost, usual employing two level topological structure, and by increasing switching frequency, adopting output filtering measure to reach corresponding performance index, this mode has the shortcomings such as loss is large, efficiency is low, volume is large.
In mesohigh high-power applications occasion, when adopting above-mentioned (1)-(3) class topological structure, then the problem solving a large amount of striding capacitance, a large amount of clamping diode, in a large number isolated DC power supply bring of having to.And adopt active-clamp type or the universal many level topological structure of P2, switching device increase while increase Systematical control complexity, also can cause the increase of drive circuit and buffering circuit quantity and the increase of cost.
Compared with traditional two-level inverter topological structure, novel simplification diode-clamped three-level topology structure reduces system complex type, but it is little to have conventional I type three-level inverter output current harmonics aberration rate, the advantage that dv/dt is little, and has the identical voltage stress of traditional T-shaped three level.Simplify diode-clamped three-level topology structure and have two kinds of optional differentiation type topological structures, they all adopt active commutation mode, can be used for solving power loss imbalance problem.
Compared with traditional multi-level converter topological structure, the universal multi-level converter topological structure degree of modularity that the utility model proposes is high, extensibility good, switching device quantity is few, structure is simple, the unbalanced problem of power loss can be solved, and remain the advantage of traditional multi-level converter.
Utility model content
Technical problem: technical problem to be solved in the utility model is: a kind of elementary cell for multi-level converter is provided, this elementary cell possesses three terminals, three kinds of dissimilar bidirectional current paths can be formed, the problem that in existing structure elementary cell, current path is single can be solved, more easily form many level.Three-level topology structure based on above-mentioned elementary cell is also provided, this structure number of devices used is few, output level number is many, there is the voltage stress that traditional T-shaped three-level structure is identical, and can solve that traditional two level block are low for large-power occasions switching frequency, Current harmonic distortion rate is high, output filter volume is large, the problems such as loss is unbalanced; And m level topological structure based on above-mentioned elementary cell is provided, this structure eliminates clamping devices a large amount of in the many level block of diode clamp, and the unbalanced problem of loss that can solve in Clamp many level topological structure, and possesses higher fault-tolerant ability.This structure can also solve striding capacitance type and a large amount of independent current source of cascading multiple electrical level structure and striding capacitance problem.Because this structure adopts modularized design, the cost safeguarded and install can be reduced.Because this structure adopts power device few, the design of modulation strategy can be simplified.
Technical scheme: for solving the problems of the technologies described above, the technical solution adopted in the utility model is:
A kind of elementary cell for multi-level converter, this elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, between insulated gate bipolar transistor both sides and two diodes, draw three terminals.
Adopt a three-level topology structure for above-mentioned elementary cell, this topological structure comprises the first direct voltage source, bus capacitor assembly and the first converter brachium pontis; Bus capacitor assembly comprises the bus capacitor of two series connection, bus capacitor modules in parallel is to the two ends of the first direct voltage source, first direct voltage source separates P current potential, O current potential and N current potential three kinds of current potentials by bus capacitor assembly, wherein, O current potential is positioned at the centre of two bus capacitors, P current potential is positioned at the positive pole of direct voltage source, and N current potential is positioned at the negative pole of direct voltage source; Converter brachium pontis comprises P level-cell, O level-cell and N level-cell, described P level-cell, O level-cell and N level-cell adopt basic cell structure to form respectively, this elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, be provided with the first terminals and the second terminals in insulated gate bipolar transistor both sides, between two diodes, be provided with the 3rd terminals; First terminals of O level-cell are connected with the 3rd terminals of P level-cell, and the second terminals of O level-cell are connected with the 3rd terminals of N level-cell, and the 3rd terminals of O level-cell are connected with O current potential; First terminals of P level-cell are connected with P current potential, and the second terminals of P level-cell are connected with the first terminals of N level-cell, and the second terminals of N level-cell are connected with N current potential; The output of the first converter brachium pontis is drawn by the second terminals of P level-cell and the first terminals junction of N level-cell.
Further, described O level-cell also comprises an insulated gate bipolar transistor; Two insulated gate bipolar transistor series connection, form the first insulated gate bipolar transistor assembly, the both sides of reverse parallel connection to the first insulated gate bipolar transistor assembly after two Diode series in O level-cell, the first terminals and the second terminals are drawn in the first insulated gate bipolar transistor assembly both sides, draw the 3rd terminals between two diodes, between two insulated gate bipolar transistors, draw the 4th terminals; 4th terminals of O level-cell are connected with the output of the first converter brachium pontis.
Further, described O level-cell also comprises an insulated gate bipolar transistor; Two insulated gate bipolar transistor series connection, form the second insulated gate bipolar transistor assembly, the both sides of reverse parallel connection to the second insulated gate bipolar transistor assembly after two Diode series in O level-cell, the first terminals and the second terminals are drawn in the second insulated gate bipolar transistor assembly both sides, draw the 3rd terminals between two diodes, between two insulated gate bipolar transistors, draw the 4th terminals; 4th terminals of O level-cell are connected with O current potential.
A m level topological structure containing above-mentioned elementary cell, this topological structure comprises the second converter brachium pontis, the second Diode series assembly, the second bus capacitor series component and the second direct voltage source; Second bus capacitor series component is composed in series by m-1 bus capacitor, second bus capacitor series component is parallel to the two ends of the second direct voltage source, DC power supply is separated m kind potential nodes, 1 to m current potential is positioned at the tie point of the second bus capacitor series component, and the 1st current potential is positioned at the positive pole of the second direct voltage source, m current potential is positioned at the negative pole of the second direct voltage source; Second Diode series assembly comprises 2m diode, and the odd node in the second Diode series assembly is connected successively with 1st ~ m potential nodes of the second bus capacitor series component; Second converter brachium pontis comprises m level layer, and the 1st level layer comprises an elementary cell, and m level layer comprises m elementary cell, and the elementary cell quantity comprised in each level layer increases by 1 gradually with number of plies increase; Elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, draw the first terminals and the second terminals in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes; In each level layer, first terminals of elementary cell are connected with the 3rd terminals of the elementary cell being arranged in next level layer, second terminals of elementary cell are connected with the 3rd terminals of another elementary cell being arranged in next level layer, and the 3rd terminals of elementary cell are connected with the first terminals or the second terminals being arranged in a upper level layer elementary cell; The 3rd terminals being positioned at the elementary cell of the 1st level layer are connected with the output of the first converter brachium pontis; The first terminals being arranged in the elementary cell of m level layer are connected with the even number potential nodes of the second Diode series assembly respectively with the second wiring; The span of m be greater than 2 integer.
A m level topological structure containing above-mentioned elementary cell, this topological structure comprises the 3rd converter brachium pontis, the 3rd Diode series assembly, triple bus-bar capacitances in series assembly and the 3rd direct voltage source; Triple bus-bar capacitances in series assembly is composed in series by m-1 bus capacitor, triple bus-bar capacitances in series modules in parallel is in the two ends of the 3rd direct voltage source, DC power supply is separated m kind potential nodes, 1 to m current potential is positioned at the tie point of triple bus-bar capacitances in series assembly, and the 1st current potential is positioned at the positive pole of the 3rd direct voltage source, m current potential is positioned at the negative pole of the 3rd direct voltage source; 3rd Diode series assembly comprises 2m-4 diode, and the odd node being arranged in the 3rd Diode series assembly is connected successively with 2nd ~ m-1 potential nodes of triple bus-bar capacitances in series assembly; 3rd converter brachium pontis comprises m level layer, and the 1st level layer comprises an elementary cell, and m level layer comprises m elementary cell, and the elementary cell quantity comprised in each level layer increases by 1 gradually with number of plies increase; Described elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, draw the first terminals and the second terminals in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes; In each level layer, first terminals of elementary cell are connected with the 3rd terminals of the elementary cell being arranged in next level layer, second terminals of elementary cell are connected with the 3rd terminals of another elementary cell being arranged in next level layer, and the 3rd terminals of elementary cell are connected with the first terminals or the second terminals being arranged in a upper level layer elementary cell; The 3rd terminals being positioned at the elementary cell of the 1st level layer are connected with the output of the 3rd converter brachium pontis; The first terminals being positioned at first elementary cell of m level layer are connected with the positive pole of the 3rd direct voltage source, the second terminals being positioned at m elementary cell of m level layer are connected with the negative pole of the 3rd direct voltage source, be positioned at the second terminals of first elementary cell of m level layer, the first terminals of a m elementary cell, and the first terminals of 2nd ~ m-1 elementary cell are connected with the even number potential nodes in the 3rd Diode series assembly respectively with the second wiring; The span of m be greater than 2 integer.
A m level topological structure containing above-mentioned elementary cell, this topological structure comprises the 4th converter brachium pontis, the 4th Diode series assembly, the 4th bus capacitor series component and the 4th direct voltage source; 4th bus capacitor series component is composed in series by m-1 bus capacitor, 4th bus capacitor series component is parallel to the two ends of the 4th direct voltage source, DC power supply is separated m kind potential nodes, 1 to m current potential is positioned at the tie point of the 4th bus capacitor series component, and the 1st current potential is positioned at the positive pole of the 4th direct voltage source, m current potential is positioned at the negative pole of the 4th direct voltage source; 4th Diode series assembly comprises 2m diode, and the odd node in the 4th Diode series assembly is connected successively with 1st ~ m potential nodes of the 4th bus capacitor series component; 4th converter brachium pontis comprises m level layer, 1st level layer comprises an elementary cell, m level layer comprises m elementary cell, the elementary cell quantity comprised in each level layer increases by 1 gradually with number of plies increase, and the insulated gate bipolar transistor in the elementary cell of 2 to k-1 in 3 to m-1 level layer is removed, k represents the level number layer by layer at place; Elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, draw the first terminals and the second terminals in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes; In each level layer, first terminals of elementary cell are connected with the 3rd terminals of the elementary cell being arranged in next level layer, second terminals of elementary cell are connected with the 3rd terminals of another elementary cell being arranged in next level layer, and the 3rd terminals of elementary cell are connected with the first terminals or the second terminals being arranged in a upper level layer elementary cell; The 3rd terminals being positioned at the elementary cell of the 1st level layer are connected with the output of the 4th converter brachium pontis; The first terminals being arranged in the elementary cell of m level layer are connected with the even number potential nodes of the 4th Diode series assembly respectively with the second wiring; The span of m be greater than 2 integer.
A m level topological structure containing above-mentioned elementary cell, this topological structure comprises the 5th converter brachium pontis, the 5th Diode series assembly, the 5th bus capacitor series component and the 5th direct voltage source; 5th bus capacitor series component is composed in series by m-1 bus capacitor, 5th bus capacitor series component is parallel to the two ends of the 5th direct voltage source, DC power supply is separated m kind potential nodes, 1 to m current potential is positioned at the tie point of the 5th bus capacitor series component, and the 1st current potential is positioned at the positive pole of the 5th direct voltage source, m current potential is positioned at the negative pole of the 5th direct voltage source; 5th Diode series assembly comprises 2m diode, and the odd node in the 5th Diode series assembly is connected successively with 1st ~ m potential nodes of the 5th bus capacitor series component; 5th converter brachium pontis comprises m-1 level layer, 1st and 2 level layers be two level elementary cells, 3rd level layer comprises 3 elementary cells, m level layer comprises m elementary cell, from 4th ~ m level layer, the elementary cell quantity comprised in each level layer increases by 1 gradually with number of plies increase; Described elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, draw the first terminals and the second terminals in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes; Two described level elementary cells comprise two insulated gate bipolar transistors and two diodes, the insulated gate bipolar transistor both sides of reverse parallel connection to two series connection after two Diode series, the first terminals and the second terminals are drawn in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes, and the intermediate connection point of the intermediate connection point of series diode with series connection insulated gate bipolar transistor is connected; First terminals of two level elementary cells are connected with the 3rd terminals of the 1st elementary cell of the 3rd level layer, second terminals of two level elementary cells are connected with the 3rd terminals of the 2nd elementary cell of the 3rd level layer, and the 3rd terminals of two level elementary cells are connected with the 3rd terminals of the 3rd elementary cell of the 3rd level layer; 3rd terminals of the output two level elementary cell of converter brachium pontis are drawn; In 4 to m level layer, first terminals of elementary cell are connected with the 3rd terminals of the elementary cell being arranged in next level layer, second terminals of elementary cell are connected with the 3rd terminals of another elementary cell being arranged in next level layer, and the 3rd terminals of elementary cell are connected with the first terminals or the second terminals being arranged in a upper level layer elementary cell; The first terminals being arranged in the elementary cell of m level layer are connected with the even number potential nodes of the 5th Diode series assembly respectively with the second wiring; The span of m be greater than 2 integer.
Beneficial effect: compared with prior art, the utility model has following beneficial effect:
1, because the utility model adopts insulated gate bipolar transistor and two anti-paralleled diode as basic composition unit, form the path of two-way circulating of electric current, possess the two-way transmission capabilities of power.
2, the novel simplification diode-clamped three-level converter topological structure switching device in the utility model is few, and possesses the same performance of traditional three level, has the output current THD lower than traditional two level converter topological structures.
3, the New Active Clamp three-level converter topological structure developed by novel simplification diode-clamped three-level converter topological structure in the utility model possesses equal power loss distribution capability, reduce bad working environments to the adverse effect of system, elevator system utilance and maximum output capacity.
4, the universal multi-level converter topological structure in the utility model is only made up of elementary cell, series diode assembly, series bus capacitance component, DC power supply, and topological structure is simple, and scalability is good, and the degree of modularity is high.
5, the universal multi-level converter topological structure in the utility model possesses system from redundancy, may be used for power loss distribution equilibrium and fault after fault-tolerant processing.In the multi-level converter topological structure that can realize said function, this topological structure adopts less switching device.
6, the universal multi-level converter topological structure in the utility model can also reduce switching device and diode number further by optimizing, and reduces costs and system complexity.
Accompanying drawing explanation
Fig. 1 is the structural representation of elementary cell in the utility model.
Fig. 2 is the structural representation of the first the three-level topology structure that the utility model proposes.
Fig. 3 is in the first the three-level topology structure that the utility model proposes, current path schematic diagram during P level.
Fig. 4 is in the first the three-level topology structure that the utility model proposes, current path schematic diagram during O level.Structural representation.
Fig. 5 is in the first the three-level topology structure that the utility model proposes, current path schematic diagram during N level.Structural representation.
Fig. 6 is the structural representation of the second three-level topology structure that the utility model proposes.
Fig. 7 is the structural representation of the third three-level topology structure that the utility model proposes.
Fig. 8 is in the second three-level topology structure that the utility model proposes, and exports current path schematic diagram during O level.
Fig. 9 is in the third three-level topology structure that the utility model proposes, and exports current path schematic diagram during O level.
Figure 10 is the modulator approach figure of the first three-level topology structure of the utility model based on stacked pair of carrier wave.
Figure 11 is the schematic diagram of the first m level converter topological structure of the present utility model.
Figure 12 is the schematic diagram of the second m level converter topological structure of the present utility model.
Figure 13 is the schematic diagram of the third m level converter topological structure of the present utility model.
Figure 14 is the schematic diagram of the 4th kind of m level converter topological structure of the present utility model.
Figure 15 is in the first m level converter topological structure of the utility model, current path schematic diagram during P+ level.
Figure 16 is in the first m level converter topological structure of the utility model, current path schematic diagram during P-level.
Figure 17 is in the first m level converter topological structure of the utility model, current path schematic diagram during N+ level.
Figure 18 is in the first m level converter topological structure of the utility model, current path schematic diagram during N-level.
Figure 19 is in the first m level converter topological structure of the utility model, current path schematic diagram during O1 level.
Figure 20 is in the first m level converter topological structure of the utility model, current path schematic diagram during O2 level.
Figure 21 is the first m level converter topological structure of the utility model the first modulator approach figure based on stacked pair of carrier wave.
Figure 22 is the second modulator approach figure of the first m level converter topological structure of the utility model based on stacked pair of carrier wave.
Embodiment
Below in conjunction with instantiation, the utility model is described in detail.Following instance will contribute to those skilled in the art and understand the utility model further, but not limit the utility model in any form.It should be pointed out that to those skilled in the art, without departing from the concept of the premise utility, some distortion and improvement can also be made.These all belong to protection range of the present utility model.
With reference to Fig. 1, elementary cell for multi-level converter of the present utility model, comprise insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, between insulated gate bipolar transistor both sides and two diodes, draw three terminals.
The course of work of this elementary cell is: when the insulated gate bipolar transistor in this elementary cell and the elementary cell that is connected with its first terminals all conducting time, to flow into insulated gate bipolar transistor from the first terminals from the electric current with its first terminals contiguous location, the diode through below flows out the forward path that the 3rd terminals form electric current; Electric current flows into the diode of top from the 3rd terminals, and is flowed into the unit be connected with its first terminals by the first terminals, forms the reverse path of electric current.In like manner, when the insulated gate bipolar transistor in this elementary cell and the elementary cell that is connected with its second terminals all conducting time, electric current will form the two-way approach of electric current between the two or three terminals.In addition, if during the 3rd terminals no current inflow and outflow, this elementary cell can be degenerated to the elementary cell of existing structure, between the one or two terminals, the two-way approach of electric current is formed.Relative to the single current path in the elementary cell of existing structure, this elementary cell possesses three kinds of current paths, more easily realizes many level and exports.
With reference to Fig. 2, the first three-level topology structure of the present utility model, comprises the first direct voltage source 11, bus capacitor assembly 12 and the first converter brachium pontis 13.Bus capacitor assembly 12 comprises the bus capacitor of two series connection, bus capacitor assembly 12 is parallel to the two ends of the first direct voltage source 11, first direct voltage source 11 separates P current potential, O current potential and N current potential three kinds of current potentials by bus capacitor assembly 12, wherein, O current potential is positioned at the centre of two bus capacitors, P current potential is positioned at the positive pole of direct voltage source 11, and N current potential is positioned at the negative pole of direct voltage source 12; Converter brachium pontis 13 comprises P level-cell 14, O level-cell 15 and N level-cell 16, described P level-cell 14, O level-cell 15 and N level-cell 16 adopt basic cell structure to form respectively, this elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, be provided with the first terminals and the second terminals in insulated gate bipolar transistor both sides, between two diodes, be provided with the 3rd terminals.First terminals of O level-cell 15 are connected with the 3rd terminals of P level-cell 14, and the second terminals of O level-cell 15 are connected with the 3rd terminals of N level-cell 16, and the 3rd terminals of O level-cell 15 are connected with O current potential; First terminals of P level-cell 14 are connected with P current potential, and the second terminals of P level-cell 14 are connected with the first terminals of N level-cell 16, and the second terminals of N level-cell 16 are connected with N current potential; The output of the first converter brachium pontis 13 is drawn by the second terminals of P level-cell 14 and the first terminals junction of N level-cell 16.
With reference to Fig. 3-Fig. 5, the course of work of above-mentioned three-level topology structure is: as shown in Figure 3, when insulated gate bipolar transistor S2 conducting in P level-cell, electric current will form two-way approach between its one or two terminals, and therefore brachium pontis output potential will equal P current potential.As shown in Figure 4, when insulated gate bipolar transistor S1 conducting in O level-cell, electric current will form two-way approach between its 3rd terminals and brachium pontis output, and therefore brachium pontis output potential will equal O current potential.As shown in Figure 5, when insulated gate bipolar transistor S3 conducting in N level-cell, electric current will form two-way approach between its one or two terminals, and therefore brachium pontis output potential will equal N current potential.Brachium pontis can be made to export by the different on off states of control S1, S2, S3 and there are three kinds of different potential states.While minimizing power device quantity, the basic function of three level should be achieved, reduces the percent harmonic distortion of output current, improve equivalent switching frequency.
Stacked pair of carrier modulating method of the first three-level topology structure as shown in Figure 10.The carrier signal 41 of modulation wave signal 43 and stacked on top of one another and lower carrier signal 42 two carrier signals are compared.When modulation wave signal 43 is greater than carrier signal 41, control S2 conducting.When modulation wave signal 43 is less than lower carrier signal 42, control S3 conducting.The state of S1 is obtained through NOR gate by the state of S2, S3.The principle that all devices are followed " first closing conducting of having no progeny " arranges dead band, and the method for rising edge time delay can be adopted in force to realize dead band function.
With reference to Fig. 6, the second three-level topology structure that the utility model provides, identical with the first three-level topology structure, difference is: described O level-cell 15 also comprises an insulated gate bipolar transistor; Two insulated gate bipolar transistor series connection, form the first insulated gate bipolar transistor assembly 17, the both sides of reverse parallel connection to the first insulated gate bipolar transistor assembly 17 after two Diode series in O level-cell 15, the first terminals and the second terminals are drawn in the first insulated gate bipolar transistor assembly 17 both sides, draw the 3rd terminals between two diodes, between two insulated gate bipolar transistors, draw the 4th terminals; 4th terminals of O level-cell 15 are connected with the output of the first converter brachium pontis 13.
Composition graphs 8, the course of work of the second three-level topology structure is: as two insulated gate bipolar transistor S1 in the first insulated gate bipolar transistor assembly 17
h, S1
lduring conducting, electric current the second, will form two-way approach between four terminals, and because brachium pontis output is connected with its second terminals, brachium pontis output potential will equal O current potential.Compared with the first three-level topology structure, this structure is when exporting O level, and electric current will no longer through P, N level-cell device, and because this reducing conducting and the switching loss of P, N level-cell device, loss distribution is more even.
With reference to Fig. 7, the third three-level topology structure that the utility model provides, identical with the first three-level topology structure, difference is: described O level-cell 15 also comprises an insulated gate bipolar transistor; Two insulated gate bipolar transistor series connection, form the second insulated gate bipolar transistor assembly 18, the both sides of reverse parallel connection to the second insulated gate bipolar transistor assembly 18 after two Diode series in O level-cell 15, the first terminals and the second terminals are drawn in the second insulated gate bipolar transistor assembly 18 both sides, draw the 3rd terminals between two diodes, between two insulated gate bipolar transistors, draw the 4th terminals; 4th terminals of O level-cell 15 are connected with O current potential.
Composition graphs 9, the course of work of the third three-level topology structure is: as two insulated gate bipolar transistor S1 in the second insulated gate bipolar transistor assembly 18
h, S1
lduring conducting, electric current will form two-way approach between its second terminals and brachium pontis output, and brachium pontis output potential will equal O current potential.Compared with the first three-level topology structure, this structure export O level time, electric current by the diode component no longer in O level-cell, because this reducing conducting and the reverse recovery loss of O level-cell device, when converter is in low pressure output, it is more even that this will make loss distribute.
See Figure 11, the first m level topological structure that the utility model provides, comprises the second converter brachium pontis 501, second Diode series assembly 502, second bus capacitor series component 503 and the second direct voltage source 504; Second bus capacitor series component 503 is composed in series by m-1 bus capacitor, second bus capacitor series component 503 is parallel to the two ends of the second direct voltage source 504, DC power supply is separated m kind potential nodes, 1 to m current potential is positioned at the tie point of the second bus capacitor series component 503, and the 1st current potential is positioned at the positive pole of the second direct voltage source 504, m current potential is positioned at the negative pole of the second direct voltage source 504; Second Diode series assembly 502 comprises 2m diode, and the odd node in the second Diode series assembly 502 is connected successively with 1st ~ m potential nodes of the second bus capacitor series component 503; Second converter brachium pontis 501 comprises m level layer, and the 1st level layer comprises an elementary cell, and m level layer comprises m elementary cell, and the elementary cell quantity comprised in each level layer increases by 1 gradually with number of plies increase.Described elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, draw the first terminals and the second terminals in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes.In each level layer, first terminals of elementary cell are connected with the 3rd terminals of the elementary cell being arranged in next level layer, second terminals of elementary cell are connected with the 3rd terminals of another elementary cell being arranged in next level layer, and the 3rd terminals of elementary cell are connected with the first terminals or the second terminals being arranged in a upper level layer elementary cell; The 3rd terminals being positioned at the elementary cell of the 1st level layer are connected with the output of the first converter brachium pontis 501; The first terminals being arranged in the elementary cell of m level layer are connected with the even number potential nodes of the second Diode series assembly 502 respectively with the second wiring; The span of m be greater than 2 integer.
The course of work of above-mentioned m level topological structure is: for three level (m=3), as shown in figure 15, as the insulated gate bipolar transistor S1 in topological structure, S2, during S4 conducting, electric current is flow to the first terminals of three level layer first elementary cell through the first diode of Diode series assembly (502) by the first potential nodes, then, electric current flows out the 3rd terminals of three level layer first elementary cell successively and flows into the first terminals of second electrical level layer first elementary cell, 3rd terminals of outflow of bus current second electrical level layer first elementary cell also flow into the first terminals of the first level layer first elementary cell.Finally, electric current is flowed out by the 3rd terminals of the first level layer first elementary cell, defines the forward path of electric current.As shown in figure 16, when electric current flows into the 3rd terminals of the first level layer first elementary cell, the first terminals successively through the first level layer first elementary cell, the first terminals of second electrical level layer first elementary cell, the second terminals of three level layer first elementary cell are flowed through Diode series assembly 502 and flow into the first current potential by electric current, form the reverse path of electric current.Therefore, when insulated gate bipolar transistor S1, S2, S4 conducting, brachium pontis output potential equals the first current potential.In like manner, as shown in figs. 17-18, when insulated gate bipolar transistor S1, S3, S6 conducting, brachium pontis output potential equals the 3rd current potential.As shown in figure 19, when insulated gate bipolar transistor S2, S3, S5 conducting, brachium pontis output potential equals the second current potential.As shown in figure 20, when insulated gate bipolar transistor S1, S5 conducting, brachium pontis output potential equals the second current potential.This is simple for structure compact, and the number of devices of use is few, without clamping device, independent current source and striding capacitance, and has the mode that two kinds export the second current potential, may be used for the Fault-Tolerant Problems under the solution unbalanced problem of loss and malfunction.This structure adopts modularized design in addition, can reduce the Cost Problems in installation and maintenance.
See Figure 12, the second m level topological structure, comprises the 3rd converter brachium pontis 601, the 3rd Diode series assembly 602, triple bus-bar capacitances in series assembly 603 and the 3rd direct voltage source 604; Triple bus-bar capacitances in series assembly 603 is composed in series by m-1 bus capacitor, triple bus-bar capacitances in series assembly 603 is parallel to the two ends of the 3rd direct voltage source 604, DC power supply is separated m kind potential nodes, 1 to m current potential is positioned at the tie point of triple bus-bar capacitances in series assembly 603, and the 1st current potential is positioned at the positive pole of the 3rd direct voltage source 604, m current potential is positioned at the negative pole of the 3rd direct voltage source 604; 3rd Diode series assembly 602 comprises 2m-4 diode, and the odd node being arranged in the 3rd Diode series assembly 602 is connected successively with 2nd ~ m-1 potential nodes of triple bus-bar capacitances in series assembly 503;
3rd converter brachium pontis 601 comprises m level layer, and the 1st level layer comprises an elementary cell, and m level layer comprises m elementary cell, and the elementary cell quantity comprised in each level layer increases by 1 gradually with number of plies increase.Described elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, draw the first terminals and the second terminals in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes.In each level layer, first terminals of elementary cell are connected with the 3rd terminals of the elementary cell being arranged in next level layer, second terminals of elementary cell are connected with the 3rd terminals of another elementary cell being arranged in next level layer, and the 3rd terminals of elementary cell are connected with the first terminals or the second terminals being arranged in a upper level layer elementary cell; The 3rd terminals being positioned at the elementary cell of the 1st level layer are connected with the output of the 3rd converter brachium pontis 601; The first terminals being positioned at first elementary cell of m level layer are connected with the positive pole of the 3rd direct voltage source 604, the second terminals being positioned at m elementary cell of m level layer are connected with the negative pole of the 3rd direct voltage source 604, be positioned at the second terminals of first elementary cell of m level layer, the first terminals of a m elementary cell, and the first terminals of 2nd ~ m-1 elementary cell are connected with the even number potential nodes in the 3rd Diode series assembly 602 respectively with the second wiring.The span of m be greater than 2 integer.
The course of work of above-mentioned the second m level topological structure is: similar with the first m level topological structure course of work, controls the on off state of the insulated gate bipolar transistor in converter brachium pontis, brachium pontis can be made to export corresponding current potential.With the first m level topological structure unlike, when brachium pontis exports the first current potential, electric current no longer through first and second diode of series diode assembly 502, and is directly flowed into by the first terminals of m level layer first elementary cell or flows out the first current potential.In like manner, when brachium pontis exports the first current potential, electric current no longer through 2m-1,2m diode of series diode assembly 502, and is directly flowed into by m elementary cell second terminals of m level layer or flows out m current potential.This topological structure further reduces number of devices, and maintains all functions of the first structure, can be used for the Fault-Tolerant Problems under solution wear leveling problem and fault equally.Different from the first m level topological structure, outermost four diodes in series diode assembly in the second m level topological structure are removed, and the outermost of bus capacitor series component is directly connected with converter brachium pontis m level layer outermost essential structure unit.
See Figure 13, the third m level topological structure, comprises the 4th converter brachium pontis 701, the 4th Diode series assembly 702, the 4th bus capacitor series component 703 and the 4th direct voltage source 704; 4th bus capacitor series component 703 is composed in series by m-1 bus capacitor, 4th bus capacitor series component 703 is parallel to the two ends of the 4th direct voltage source 704, DC power supply is separated m kind potential nodes, 1 to m current potential is positioned at the tie point of the 4th bus capacitor series component 703, and the 1st current potential is positioned at the positive pole of the 4th direct voltage source 704, m current potential is positioned at the negative pole of the 4th direct voltage source 704; 4th Diode series assembly 702 comprises 2m diode, and the odd node in the 4th Diode series assembly 702 is connected successively with 1st ~ m potential nodes of the 4th bus capacitor series component 703; 4th converter brachium pontis 701 comprises m level layer, 1st level layer comprises an elementary cell, m level layer comprises m elementary cell, the elementary cell quantity comprised in each level layer increases by 1 gradually with number of plies increase, and the insulated gate bipolar transistor in the elementary cell of 2 to k-1 in 3 to m-1 level layer is removed, k represents the level number layer by layer at place.Described elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, draw the first terminals and the second terminals in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes.In each level layer, first terminals of elementary cell are connected with the 3rd terminals of the elementary cell being arranged in next level layer, second terminals of elementary cell are connected with the 3rd terminals of another elementary cell being arranged in next level layer, and the 3rd terminals of elementary cell are connected with the first terminals or the second terminals being arranged in a upper level layer elementary cell; The 3rd terminals being positioned at the elementary cell of the 1st level layer are connected with the output of the 4th converter brachium pontis 701; The first terminals being arranged in the elementary cell of m level layer are connected with the even number potential nodes of the 4th Diode series assembly 702 respectively with the second wiring.The span of m be greater than 3 integer.
The course of work of the third m level topological structure above-mentioned is: similar with the first m level topological structure course of work, controls the on off state of the insulated gate bipolar transistor in converter brachium pontis, brachium pontis can be made to export corresponding current potential.With the first m level topological structure unlike, the mode of this structure output intermediate potential is unique.This topological structure adopts number of devices minimum, can realize the most basic demand of m level while reducing costs.Due to the minimizing of number of devices, the fault tolerance that this structure will no longer possess under wear leveling function and fault.In this structure, the inner side insulated gate bipolar transistor (S5, S8, S9) of converter brachium pontis is removed.This structure will not have wear leveling function.
See Figure 14, the 4th kind of m level topological structure, comprises the 5th converter brachium pontis 801, the 5th Diode series assembly 802, the 5th bus capacitor series component 803 and the 5th direct voltage source 804; 5th bus capacitor series component 803 is composed in series by m-1 bus capacitor, 5th bus capacitor series component 803 is parallel to the two ends of the 5th direct voltage source 804, DC power supply is separated m kind potential nodes, 1 to m current potential is positioned at the tie point of the 5th bus capacitor series component 803, and the 1st current potential is positioned at the positive pole of the 5th direct voltage source 804, m current potential is positioned at the negative pole of the 5th direct voltage source 804; 5th Diode series assembly 802 comprises 2m diode, and the odd node in the 5th Diode series assembly 802 is connected successively with 1st ~ m potential nodes of the 5th bus capacitor series component 803; 5th converter brachium pontis 801 comprises m-1 level layer, 1st and 2 level layers be two level elementary cells 81,3rd level layer comprises 3 elementary cells, m level layer comprises m elementary cell, from 4th-m level layer, the elementary cell quantity comprised in each level layer increases by 1 gradually with number of plies increase.Described elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, draw the first terminals and the second terminals in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes.Two described level elementary cells 81 comprise two insulated gate bipolar transistors and two diodes, the insulated gate bipolar transistor both sides of reverse parallel connection to two series connection after two Diode series, the first terminals and the second terminals are drawn in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes, and the intermediate connection point of the intermediate connection point of series diode with series connection insulated gate bipolar transistor is connected.First terminals of two level elementary cells 81 are connected with the 3rd terminals of the 1st elementary cell of the 3rd level layer, second terminals of two level elementary cells 81 are connected with the 3rd terminals of the 2nd elementary cell of the 3rd level layer, and the 3rd terminals of two level elementary cells 81 are connected with the 3rd terminals of the 3rd elementary cell of the 3rd level layer; 3rd terminals of the output two level elementary cell 81 of converter brachium pontis 501 are drawn.In 4 to m level layer, first terminals of elementary cell are connected with the 3rd terminals of the elementary cell being arranged in next level layer, second terminals of elementary cell are connected with the 3rd terminals of another elementary cell being arranged in next level layer, and the 3rd terminals of elementary cell are connected with the first terminals or the second terminals being arranged in a upper level layer elementary cell; The first terminals being arranged in the elementary cell of m level layer are connected with the even number potential nodes of the 5th Diode series assembly 802 respectively with the second wiring.The span of m be greater than 2 integer.
The course of work of above-mentioned 4th kind of m level topological structure is: similar with the first m level topological structure course of work, controls the on off state of the insulated gate bipolar transistor in converter brachium pontis, brachium pontis can be made to export corresponding current potential.With the first m level topological structure unlike, when electric current enters second electrical level layer by three level laminar flow, electric current will form the forward path of electric current through conventional cell structure 81.Meanwhile, when electric current flows into brachium pontis by output, electric current will flow into three level layer through conventional cell structure 81, form the reverse path of electric current.This topological structure decreases the quantity of insulated-gate bipolar transistor device, is reducing costs and remaining while simplifying control all functions of the first structure, can be used for solving the Fault-Tolerant Problems under wear leveling problem and fault equally.Insulated gate bipolar transistor (S1) in " pyramid " code converter brachium pontis 501 in this structure is removed, and second layer essential structure unit is replaced to common " IGBT+ anti-paralleled diode " unit.This structural loss equalization function will decrease.
Figure 21 and Figure 22 gives the stacked pair carrier modulation strategy of the first m level topological structure converter when exporting O level in two different ways: (1) as shown in figure 21, under the first working method, the carrier signal 1201 of modulation wave signal 1203 and stacked on top of one another and lower carrier signal 1,202 two carrier signals are compared.When modulation wave signal 1203 is greater than carrier signal 1201, control insulated gate bipolar transistor S4 conducting, S3 shutoff.When modulation wave signal 1203 is less than lower carrier signal 1202, control S6 conducting, S2 turn off.The state of S1 is got XOR by the state of S2, S3 and is obtained, the complementary conducting of S5 and S1.Insulated gate bipolar transistor S1-S6 exports corresponding level according on off state shown in table 1 (" 1 " represents conducting, and " 0 " represents shutoff).(2) as shown in figure 22, under the second working method, the carrier signal 1204 of modulation wave signal 1206 and stacked on top of one another and lower carrier signal 1,205 two carrier signals are compared.When modulation wave signal 1206 is greater than carrier signal 1204, control S2, S4 conducting.When modulation wave signal 1206 is less than lower carrier signal 1205, control S3, S6 conducting.The state of S5 is got by the state of S2, S3 maybe have to be to, and S1 is in conducting state all the time.Insulated gate bipolar transistor S1-S6 exports corresponding level according on off state shown in table 2.The principle that all devices are followed " first closing conducting of having no progeny " arranges dead band, and the method for rising edge time delay can be adopted in force to realize dead band function.
The first m level topological structure of table 1 exports on off state during varying level under the first working method
| S1 | S2 | S3 | S4 | S5 | S6 | Output level |
| 1 | 1 | 0 | 1 | 0 | 0 | P |
| 1 | 0 | 1 | 0 | 0 | 1 | N |
| 0 | 1 | 1 | 0 | 1 | 0 | O2 |
The first m level topological structure of table 2 exports on off state during varying level under the second working method
| S1 | S2 | S3 | S4 | S5 | S6 | Output level |
| 1 | 1 | 0 | 1 | 0 | 0 | P |
| 1 | 0 | 1 | 0 | 0 | 1 | N |
| 1 | 0 | 0 | 0 | 1 | 0 | O1 |
Above concrete enforcement of the present utility model is described.It is to be appreciated that the utility model does not limit to and above-mentioned particular implementation, those skilled in the art can make various distortion or amendment in the scope with all strength required, this does not affect flesh and blood of the present utility model.
Claims (8)
1. the elementary cell for multi-level converter, it is characterized in that, this elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, between insulated gate bipolar transistor both sides and two diodes, draw three terminals.
2. one kind adopts the three-level topology structure of elementary cell according to claim 1, it is characterized in that, this topological structure comprises the first direct voltage source (11), bus capacitor assembly (12) and the first converter brachium pontis (13); Bus capacitor assembly (12) comprises the bus capacitor of two series connection, bus capacitor assembly (12) is parallel to the two ends of the first direct voltage source (11), first direct voltage source (11) separates P current potential, O current potential and N current potential three kinds of current potentials by bus capacitor assembly (12), wherein, O current potential is positioned at the centre of two bus capacitors, P current potential is positioned at the positive pole of direct voltage source (11), and N current potential is positioned at the negative pole of direct voltage source (12); Converter brachium pontis (13) comprises P level-cell (14), O level-cell (15) and N level-cell (16), described P level-cell (14), O level-cell (15) and N level-cell (16) adopt basic cell structure to form respectively, this elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, be provided with the first terminals and the second terminals in insulated gate bipolar transistor both sides, between two diodes, be provided with the 3rd terminals;
First terminals of O level-cell (15) are connected with the 3rd terminals of P level-cell (14), second terminals of O level-cell (15) are connected with the 3rd terminals of N level-cell (16), and the 3rd terminals of O level-cell (15) are connected with O current potential; First terminals of P level-cell (14) are connected with P current potential, second terminals of P level-cell (14) are connected with the first terminals of N level-cell (16), and the second terminals of N level-cell (16) are connected with N current potential; The output of the first converter brachium pontis (13) is drawn by the second terminals of P level-cell (14) and the first terminals junction of N level-cell (16).
3. according to three-level topology structure according to claim 2, it is characterized in that, described O level-cell (15) also comprises an insulated gate bipolar transistor; Two insulated gate bipolar transistor series connection, form the first insulated gate bipolar transistor assembly (17), the both sides of reverse parallel connection to the first insulated gate bipolar transistor assembly (17) after two Diode series in O level-cell (15), the first terminals and the second terminals are drawn in the first insulated gate bipolar transistor assembly (17) both sides, draw the 3rd terminals between two diodes, between two insulated gate bipolar transistors, draw the 4th terminals; 4th terminals of O level-cell (15) are connected with the output of the first converter brachium pontis (13).
4. according to three-level topology structure according to claim 2, it is characterized in that, described O level-cell (15) also comprises an insulated gate bipolar transistor; Two insulated gate bipolar transistor series connection, form the second insulated gate bipolar transistor assembly (18), the both sides of reverse parallel connection to the second insulated gate bipolar transistor assembly (18) after two Diode series in O level-cell (15), the first terminals and the second terminals are drawn in the second insulated gate bipolar transistor assembly (18) both sides, draw the 3rd terminals between two diodes, between two insulated gate bipolar transistors, draw the 4th terminals; 4th terminals of O level-cell (15) are connected with O current potential.
5. the m level topological structure containing elementary cell according to claim 1, it is characterized in that, this topological structure comprises the second converter brachium pontis (501), the second Diode series assembly (502), the second bus capacitor series component (503) and the second direct voltage source (504); Second bus capacitor series component (503) is composed in series by m-1 bus capacitor, second bus capacitor series component (503) is parallel to the two ends of the second direct voltage source (504), DC power supply is separated m kind potential nodes, 1 to m current potential is positioned at the tie point of the second bus capacitor series component (503), and the 1st current potential is positioned at the positive pole of the second direct voltage source (504), m current potential is positioned at the negative pole of the second direct voltage source (504); Second Diode series assembly (502) comprises 2m diode, and the odd node in the second Diode series assembly (502) is connected successively with 1st ~ m potential nodes of the second bus capacitor series component (503); Second converter brachium pontis (501) comprises m level layer, and the 1st level layer comprises an elementary cell, and m level layer comprises m elementary cell, and the elementary cell quantity comprised in each level layer increases by 1 gradually with number of plies increase;
Described elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, draw the first terminals and the second terminals in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes;
In each level layer, first terminals of elementary cell are connected with the 3rd terminals of the elementary cell being arranged in next level layer, second terminals of elementary cell are connected with the 3rd terminals of another elementary cell being arranged in next level layer, and the 3rd terminals of elementary cell are connected with the first terminals or the second terminals being arranged in a upper level layer elementary cell; The 3rd terminals being positioned at the elementary cell of the 1st level layer are connected with the output of the first converter brachium pontis (501); The first terminals being arranged in the elementary cell of m level layer are connected with the even number potential nodes of the second Diode series assembly (502) respectively with the second wiring; The span of m be greater than 2 integer.
6. the m level topological structure containing elementary cell according to claim 1, it is characterized in that, this topological structure comprises the 3rd converter brachium pontis (601), the 3rd Diode series assembly (602), triple bus-bar capacitances in series assembly (603) and the 3rd direct voltage source (604); Triple bus-bar capacitances in series assembly (603) is composed in series by m-1 bus capacitor, triple bus-bar capacitances in series assembly (603) is parallel to the two ends of the 3rd direct voltage source (604), DC power supply is separated m kind potential nodes, 1 to m current potential is positioned at the tie point of triple bus-bar capacitances in series assembly (603), and the 1st current potential is positioned at the positive pole of the 3rd direct voltage source (604), m current potential is positioned at the negative pole of the 3rd direct voltage source (604); 3rd Diode series assembly (602) comprises 2m-4 diode, and the odd node being arranged in the 3rd Diode series assembly (602) is connected successively with 2nd ~ m-1 potential nodes of triple bus-bar capacitances in series assembly (603);
3rd converter brachium pontis (601) comprises m level layer, and the 1st level layer comprises an elementary cell, and m level layer comprises m elementary cell, and the elementary cell quantity comprised in each level layer increases by 1 gradually with number of plies increase;
Described elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, draw the first terminals and the second terminals in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes;
In each level layer, first terminals of elementary cell are connected with the 3rd terminals of the elementary cell being arranged in next level layer, second terminals of elementary cell are connected with the 3rd terminals of another elementary cell being arranged in next level layer, and the 3rd terminals of elementary cell are connected with the first terminals or the second terminals being arranged in a upper level layer elementary cell; The 3rd terminals being positioned at the elementary cell of the 1st level layer are connected with the output of the 3rd converter brachium pontis (601); The first terminals being positioned at first elementary cell of m level layer are connected with the positive pole of the 3rd direct voltage source (604), the second terminals being positioned at m elementary cell of m level layer are connected with the negative pole of the 3rd direct voltage source (604), be positioned at the second terminals of first elementary cell of m level layer, the first terminals of a m elementary cell, and the first terminals of 2nd ~ m-1 elementary cell are connected with the even number potential nodes in the 3rd Diode series assembly (602) respectively with the second wiring; The span of m be greater than 2 integer.
7. the m level topological structure containing elementary cell according to claim 1, it is characterized in that, this topological structure comprises the 4th converter brachium pontis (701), the 4th Diode series assembly (702), the 4th bus capacitor series component (703) and the 4th direct voltage source (704); 4th bus capacitor series component (703) is composed in series by m-1 bus capacitor, 4th bus capacitor series component (703) is parallel to the two ends of the 4th direct voltage source (704), DC power supply is separated m kind potential nodes, 1 to m current potential is positioned at the tie point of the 4th bus capacitor series component (703), and the 1st current potential is positioned at the positive pole of the 4th direct voltage source (704), m current potential is positioned at the negative pole of the 4th direct voltage source (704); 4th Diode series assembly (702) comprises 2m diode, and the odd node in the 4th Diode series assembly (702) is connected successively with 1st ~ m potential nodes of the 4th bus capacitor series component (703); 4th converter brachium pontis (701) comprises m level layer, 1st level layer comprises an elementary cell, m level layer comprises m elementary cell, the elementary cell quantity comprised in each level layer increases by 1 gradually with number of plies increase, and the insulated gate bipolar transistor in the elementary cell of 2 to k-1 in 3 to m-1 level layer is removed, k represents the level number layer by layer at place;
Described elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, draw the first terminals and the second terminals in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes;
In each level layer, first terminals of elementary cell are connected with the 3rd terminals of the elementary cell being arranged in next level layer, second terminals of elementary cell are connected with the 3rd terminals of another elementary cell being arranged in next level layer, and the 3rd terminals of elementary cell are connected with the first terminals or the second terminals being arranged in a upper level layer elementary cell; The 3rd terminals being positioned at the elementary cell of the 1st level layer are connected with the output of the 4th converter brachium pontis (701); The first terminals being arranged in the elementary cell of m level layer are connected with the even number potential nodes of the 4th Diode series assembly (702) respectively with the second wiring; The span of m be greater than 2 integer.
8. the m level topological structure containing elementary cell according to claim 1, it is characterized in that, this topological structure comprises the 5th converter brachium pontis (801), the 5th Diode series assembly (802), the 5th bus capacitor series component (803) and the 5th direct voltage source (804); 5th bus capacitor series component (803) is composed in series by m-1 bus capacitor, 5th bus capacitor series component (803) is parallel to the two ends of the 5th direct voltage source (804), DC power supply is separated m kind potential nodes, 1 to m current potential is positioned at the tie point of the 5th bus capacitor series component (803), and the 1st current potential is positioned at the positive pole of the 5th direct voltage source (804), m current potential is positioned at the negative pole of the 5th direct voltage source (804); 5th Diode series assembly (802) comprises 2m diode, and the odd node in the 5th Diode series assembly (802) is connected successively with 1st ~ m potential nodes of the 5th bus capacitor series component (803); 5th converter brachium pontis (801) comprises m-1 level layer, 1st and 2 level layers be two level elementary cells (81), 3rd level layer comprises 3 elementary cells, m level layer comprises m elementary cell, from 4th ~ m level layer, the elementary cell quantity comprised in each level layer increases by 1 gradually with number of plies increase;
Described elementary cell comprises insulated gate bipolar transistor and two diodes, after two Diode series, reverse parallel connection is to insulated gate bipolar transistor both sides, draw the first terminals and the second terminals in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes;
Two described level elementary cells (81) comprise two insulated gate bipolar transistors and two diodes, the insulated gate bipolar transistor both sides of reverse parallel connection to two series connection after two Diode series, the first terminals and the second terminals are drawn in insulated gate bipolar transistor both sides, draw the 3rd terminals between the two diodes, and the intermediate connection point of the intermediate connection point of series diode with series connection insulated gate bipolar transistor is connected;
First terminals of two level elementary cells (81) are connected with the 3rd terminals of the 1st elementary cell of the 3rd level layer, second terminals of two level elementary cells (81) are connected with the 3rd terminals of the 2nd elementary cell of the 3rd level layer, and the 3rd terminals of two level elementary cells (81) are connected with the 3rd terminals of the 3rd elementary cell of the 3rd level layer; 3rd terminals of output two level elementary cell (81) of converter brachium pontis (801) are drawn;
In 4 to m level layer, first terminals of elementary cell are connected with the 3rd terminals of the elementary cell being arranged in next level layer, second terminals of elementary cell are connected with the 3rd terminals of another elementary cell being arranged in next level layer, and the 3rd terminals of elementary cell are connected with the first terminals or the second terminals being arranged in a upper level layer elementary cell; The first terminals being arranged in the elementary cell of m level layer are connected with the even number potential nodes of the 5th Diode series assembly (802) respectively with the second wiring; The span of m be greater than 2 integer.
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| CN104362878A (en) * | 2014-11-28 | 2015-02-18 | 东南大学 | Basic unit for multilevel converter, and three-level and m-level topological structures |
| CN109167526A (en) * | 2018-08-24 | 2019-01-08 | 成都麦隆电气有限公司 | A kind of highly reliable high frequency efficient NPC tri-level circuit |
| CN109378987A (en) * | 2018-12-30 | 2019-02-22 | 上能电气股份有限公司 | A kind of three-level topology circuit, single-phase inverter and three-phase inverter |
| CN112366971A (en) * | 2020-11-02 | 2021-02-12 | 深圳市英威腾电气股份有限公司 | Three-level inversion topological structure, control method thereof, single-phase and three-phase inversion circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104362878A (en) * | 2014-11-28 | 2015-02-18 | 东南大学 | Basic unit for multilevel converter, and three-level and m-level topological structures |
| CN104362878B (en) * | 2014-11-28 | 2017-07-21 | 东南大学 | Elementary cell, three level and m level topological structures for multi-level converter |
| CN109167526A (en) * | 2018-08-24 | 2019-01-08 | 成都麦隆电气有限公司 | A kind of highly reliable high frequency efficient NPC tri-level circuit |
| CN109378987A (en) * | 2018-12-30 | 2019-02-22 | 上能电气股份有限公司 | A kind of three-level topology circuit, single-phase inverter and three-phase inverter |
| CN112366971A (en) * | 2020-11-02 | 2021-02-12 | 深圳市英威腾电气股份有限公司 | Three-level inversion topological structure, control method thereof, single-phase and three-phase inversion circuit |
| CN112366971B (en) * | 2020-11-02 | 2022-04-19 | 深圳市英威腾电气股份有限公司 | Three-level inversion topological structure, control method thereof, single-phase and three-phase inversion circuit |
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