CN111464064B - Harmonic suppression method of multilevel DC link inverter - Google Patents
Harmonic suppression method of multilevel DC link inverter Download PDFInfo
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- CN111464064B CN111464064B CN202010388145.9A CN202010388145A CN111464064B CN 111464064 B CN111464064 B CN 111464064B CN 202010388145 A CN202010388145 A CN 202010388145A CN 111464064 B CN111464064 B CN 111464064B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
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Abstract
The invention provides a multi-level direct current link inverter and a harmonic suppression method thereof, wherein the method comprises the following steps: a first half-bridge module; a second half-bridge module having a first end electrically connected to the first end of the first half-bridge module; a third half-bridge module, a first end of the third half-bridge module electrically connected with a second end of the second half-bridge module; a fourth half-bridge module, a first end of the fourth half-bridge module being electrically connected with a second end of the third half-bridge module; and the first end of the H-bridge module is electrically connected with the second end of the first half-bridge module, and the second end of the H-bridge module is electrically connected with the second end of the fourth half-bridge module. The invention has flexible structure, strong operability and simple operation, can generate more levels under the condition of reducing the number of switches, reduces the harmonic distortion of output voltage and output current, increases the effective values of the output voltage and the output current and improves the output power.
Description
Technical Field
The invention relates to the technical field of power conversion devices and control methods, in particular to a harmonic suppression method of a multilevel direct-current link inverter.
Background
Multi-level dc-link inverter (MLI) is a combination of power semiconductor switches and a dc voltage source to generate an ac output voltage in the form of a staircase wave, the most common and most conventional multi-level dc-link inverter topologies are neutral point clamped inverter (NPC), capacitance clamped inverter (FC) and cascaded H-bridge inverter (CHB), and in recent years, many new topologies have been developed which can generate more levels with a reduced number of switches compared to the conventional inverter topology, modular multi-level converter (MMC), which is a variant of multi-level dc-link inverter (MLI) with a modular and reconfigurable structure, multi-level dc-link inverter (dlmli), which is a very important topology of the existing MMC, MLDCLI, which is a combination of a half-bridge cell and a full-bridge inverter, the cascaded half-bridge cell operating to increase the output level of MMC, the full-bridge inverter plays a role of generating an alternating current output negative polarity.
Despite the extensive research conducted by many experts and scholars on MLI topologies, the efficient operation of MLI depends on the manner in which the switches operate. Therefore, many modulation schemes are used and developed to make MLI operate efficiently. For simplicity, modulation schemes may be divided into High Switching Frequency (HSF) and Low Switching Frequency (LSF) modulation schemes. In the HSF scheme, the switches are operated at a frequency of several kHz to reduce harmonics of the output. The switches in the LSF modulation scheme operate at less than 1 kHz. The switching losses of power semiconductor switches are an important parameter in medium voltage high power applications. The manufacturing and operating costs of the converter are reduced while the switching losses are reduced. It also helps to improve equipment utilization, converter efficiency and reduce cooling requirements. Therefore, the LSF modulation scheme is generally more preferable than the HSF modulation scheme.
The isophase method (EPM) and the semi-isophase method (HEPM) have the same duty cycle, and therefore they generate very high voltage and current harmonic distortion. Since the harmonic distortion is high, the effective values of the output voltage and current are reduced, providing low power conversion efficiency. Selective harmonic cancellation (SHE) is an effective solution to eliminate lower order harmonics, but it comes at the cost of increasing higher order harmonics. Any improvement of the SHE scheme requires an increase in the switching frequency, which is not desirable. Meanwhile, the SHE scheme is also highly dependent on the modulation factor. The working principle of Spatial Vector Control (SVC) is almost the same for MLI with less Level levels, SVC and Nearest Level Modulation (NLM). However, SVC becomes more and more complex as the MLI level increases.
Disclosure of Invention
The invention provides a harmonic suppression method of a multi-level direct-current link inverter, and aims to solve the problems that the harmonic distortion of output voltage and output current is high and the effective values of the output voltage and the output current are reduced in the traditional control method.
In order to achieve the above object, an embodiment of the present invention provides a harmonic suppression method of a multilevel dc-link inverter, including:
a first half-bridge module;
a second half-bridge module, a first end of the second half-bridge module electrically connected with a second end of the first half-bridge module;
a third half-bridge module, a first end of the third half-bridge module electrically connected with a second end of the second half-bridge module;
a fourth half-bridge module, a first end of the fourth half-bridge module being electrically connected with a second end of the third half-bridge module;
and the first end of the H-bridge module is electrically connected with the first end of the first half-bridge module, and the second end of the H-bridge module is electrically connected with the second end of the fourth half-bridge module.
The first, second, third and fourth half-bridge modules each include:
a DC voltage source;
a first switch, a second end of the first switch being electrically connected to a first end of the DC voltage source;
and a first end of the second switch is electrically connected with the second end of the direct current voltage source, and a second end of the second switch is electrically connected with the first end of the first switch.
A first terminal of the first switch in the second half-bridge module is electrically connected with a second terminal of the first switch in the first half-bridge module, a first terminal of the first switch in the third half-bridge module is electrically connected with a second terminal of the first switch in the second half-bridge module, and a first terminal of the first switch in the fourth half-bridge module is electrically connected with a second terminal of the first switch in the third half-bridge module.
The H-bridge module includes:
a third switch having a first end electrically connected to the first end of the first switch in the first half-bridge module;
a fourth switch, a first end of the fourth switch being electrically connected to a second end of the third switch;
a fifth switch, a first end of the fifth switch being electrically connected to a first end of the third switch;
a sixth switch, a first terminal of the sixth switch being electrically connected to the second terminal of the fifth switch, a second terminal of the sixth switch being electrically connected to the second terminal of the first switch in the fourth half-bridge module, a second terminal of the sixth switch being electrically connected to the second terminal of the fourth switch;
a load, a first end of the load being electrically connected to a first end of the fourth switch, a second end of the load being electrically connected to a first end of the sixth switch.
The harmonic suppression method of the multilevel DC link inverter comprises the following steps:
and 7, reducing the angle values of the switching angles of all the half-bridge modules by 0.1 degree, and executing the step 5 and the step 6 until the minimum harmonic distortion content is obtained.
Wherein, the step 1 specifically comprises:
by increasing the number of dc voltage sources, the number of levels of the multilevel dc link inverter is increased, and the values of all dc voltage sources are the same, as follows:
Vdc,j＝Vdc j＝1,2,3,4… (1)
wherein, Vdc,jDenotes a dc voltage source with index j;
the number of levels and the number of switches of the output voltage of the multilevel DC link inverter are as follows:
Nlevel＝n-3 n＝6,8,10,12… (2)
wherein N islevelRepresents the number of levels of the output voltage, n represents the number of switches;
as the number of switches increases, the number of dc voltage sources also increases, as follows:
wherein N issourceRepresenting the number of dc voltage sources and n representing the number of switches.
Wherein, the step 3 specifically comprises:
when the number of half-bridge modules is 4, the value of the angle of the switching angle of the half-bridge modules is calculated by the following equation:
wherein alpha isiThe angle value representing the switching angle i of the half-bridge module, i ═ 1,2,3, 4.
Wherein, the step 4 specifically comprises:
the harmonic distortion content is calculated by the following equation:
where THD represents the harmonic distortion content.
Wherein, the step 5 and the step 6 specifically include:
by researching a nine-level structure provided by the multi-level direct-current link inverter, wherein the nine-level structure comprises four switching angles, the harmonic distortion content is calculated for an initial set of the four switching angles, and the angle value alpha of the first switching angle is iterated for the first time1Reduce by 1 degreeMaintaining the angle value alpha of the second switching angle2Angle value alpha of the third switching angle3And the angle value alpha of the fourth switching angle4Calculating the harmonic distortion content using the updated switching angle, comparing the newly calculated harmonic distortion content with the previously calculated harmonic distortion content, and when the newly calculated harmonic distortion content is less than the previously calculated harmonic distortion content, the angle value alpha of the first switching angle is1Reducing by 1 degree again, and repeating the first iteration process until the newly calculated harmonic distortion content is not further reduced compared with the previously calculated harmonic distortion content; when the newly calculated harmonic distortion content is larger than the previously calculated harmonic distortion content, reducing the angle value of the next switching angle by 1 degree, keeping other switching angles unchanged, and executing the iteration operation; when the angle value alpha is changed by changing the first switching angle1The angle value alpha of the second switching angle is implemented when the newly calculated harmonic distortion content obtained is not further reduced compared to the previously calculated harmonic distortion content2Reducing by 1 degree until a new calculated harmonic distortion content is obtained without further reduction compared to the previously calculated harmonic distortion content, and performing a third switching angle with an angle value alpha3Reducing by 1 degree until a new calculated harmonic distortion content is obtained without further reduction compared to the previously calculated harmonic distortion content, and performing an angle value alpha of a fourth switching angle4The 1 degree reduction operation is performed until a new calculated harmonic distortion content is obtained without further reduction from the previously calculated harmonic distortion content, forming a first loop.
Wherein, the step 7 specifically comprises:
when the angle value of the fourth switching angle is alpha4And when the newly calculated harmonic distortion content is obtained and is not further reduced compared with the previously calculated harmonic distortion content, reducing the angle values of all the switching angles by 0.1 degrees, and executing the angle value alpha from the first switching angle1The beginning whole process is repeated again for the same change of reducing 1 degree, and a second cycle is formed; repeating the above cycle until the minimum value is obtainedHarmonic distortion content.
The scheme of the invention has the following beneficial effects:
the harmonic suppression method for the multilevel dc link inverter according to the above embodiment of the present invention has the advantages of flexible structure, strong operability, and simple operation of the multilevel dc link inverter, and can generate more levels with reduced switching number, the harmonic suppression method is simple to execute, the switching angle can be calculated by a simple equation, so that the harmonic suppression method is easier to execute, the new switching angle is helpful to improve the performance parameters of the multilevel dc link inverter, reduce the harmonic distortion content of the output voltage and the output current, increase the effective values of the output voltage and the output current, improve the output power, expand the multilevel dc link inverter to any level, and have enough space to improve the harmonic suppression method without increasing the switching frequency.
Drawings
FIG. 1 is a flow chart of the present invention;
FIG. 2 is a schematic diagram comparing the output of a 7-level multilevel DC-link inverter of the present invention with a sinusoidal waveform;
FIG. 3 is a specific circuit diagram of the present invention.
[ description of reference ]
1-a first half-bridge module; 2-a second half-bridge module; 3-a third half-bridge module; 4-a fourth half-bridge module; 5-H bridge module; 6-direct voltage source 6; 7-a first switch; 8-a second switch; 9-a third switch; 10-a fourth switch; 11-a fifth switch; 12-a sixth switch; 13-load.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
The invention provides a harmonic suppression method of a multilevel direct current link inverter, aiming at the problems that the harmonic distortion of output voltage and output current is high and the effective values of the output voltage and the output current are reduced in the existing control method.
As shown in fig. 1 to 3, an embodiment of the present invention provides a harmonic suppression method of a multilevel dc-link inverter, the multilevel dc-link inverter including: a first half-bridge module 1; a second half-bridge module 2, a first end of the second half-bridge module 2 being electrically connected with a second end of the first half-bridge module 1; a third half-bridge module 3, a first end of the third half-bridge module 3 being electrically connected with a second end of the second half-bridge module 2; a fourth half-bridge module 4, a first end of the fourth half-bridge module 4 being electrically connected with a second end of the third half-bridge module 3; and the first end of the H-bridge module 5 is electrically connected with the first end of the first half-bridge module 1, and the second end of the H-bridge module 5 is electrically connected with the second end of the fourth half-bridge module 4.
The method for harmonic suppression of a multilevel dc-link inverter according to the above-mentioned embodiment of the present invention is composed of the first half-bridge module 1, the second half-bridge module 2, the third half-bridge module 3, the fourth half-bridge module 4 and the H-bridge module 5, wherein the first switch 7 and the second switch 8 are disposed in each of the first half-bridge module 1, the second half-bridge module 2, the third half-bridge module 3 and the fourth half-bridge module 4, and the operation of the first switch 7 and the second switch 8 in the first half-bridge module 1, the second half-bridge module 2, the third half-bridge module 3 and the fourth half-bridge module 4 determines whether the relevant dc voltage source 6 should be added to the circuit or not by cascading the first half-bridge module 1, the second half-bridge module 2, the third half-bridge module 3 and the fourth half-bridge module 4 to generate different levels, the first switch 7 and the second switch 8 in the first half-bridge module 1, the second half-bridge module 2, the third half-bridge module 3 and the fourth half-bridge module 4 operate in a switched manner.
The first half-bridge module 1, the second half-bridge module 2, the third half-bridge module 3 and the fourth half-bridge module 4 each include: a direct current voltage source 6; a first switch 7, a second end of the first switch 7 being electrically connected to a first end of the dc voltage source 6; a second switch 8, a first terminal of the second switch 8 is electrically connected to the second terminal of the dc voltage source 6, and a second terminal of the second switch 8 is electrically connected to the first terminal of the first switch 7.
A first terminal of the first switch 7 in the second half-bridge module 2 is electrically connected to a second terminal of the first switch 7 in the first half-bridge module 1, a first terminal of the first switch 7 in the third half-bridge module 3 is electrically connected to a second terminal of the first switch 7 in the second half-bridge module 2, and a first terminal of the first switch 7 in the fourth half-bridge module 4 is electrically connected to a second terminal of the first switch 7 in the third half-bridge module 3.
The H-bridge module 5 includes: a third switch 9, a first end of the third switch 9 being electrically connected with a first end of the first switch 7 in the first half-bridge module 1; a fourth switch 10, wherein a first end of the fourth switch 10 is electrically connected with a second end of the third switch 9; a fifth switch 11, wherein a first end of the fifth switch 11 is electrically connected with a first end of the third switch 9; a sixth switch 12, a first terminal of the sixth switch 12 is electrically connected to the second terminal of the fifth switch 11, a second terminal of the sixth switch 12 is electrically connected to the second terminal of the first switch 7 in the fourth half-bridge module 4, and a second terminal of the sixth switch 12 is electrically connected to the second terminal of the fourth switch 10; a load 13, wherein a first terminal of the load 13 is electrically connected to a first terminal of the fourth switch 10, and a second terminal of the load 13 is electrically connected to a first terminal of the sixth switch 12.
The harmonic suppression method of the multilevel dc link inverter according to the above embodiment of the present invention is considered when considering the first switch S in the fourth half-bridge module 41And the second switch S in the fourth half-bridge module 42While, the switch S is turned on2And closing the switch S1Providing a current path connecting a DC voltage source V in said fourth half-bridge module 4dc1Added to the main circuit, but opening the switch S1And closing the switch S2Will release Vdc1The association of (a); when considering the first switch S in the third half-bridge module 33And the second switch S in the third half-bridge module 34While, the switch S is turned on4And closing the switch S3Providing a current path connecting a DC voltage source V in said third half-bridge module 3dc2Added to the main circuit, but opening the switch S3And closing the switch S4Will release Vdc2The association of (a); when considering the first switch S in the second half-bridge module 25And the second switch S in the second half-bridge module 26While, the switch S is turned on6And closing the switch S5Providing a current path connecting a DC voltage source V in said second half-bridge module 2dc3Added to the main circuit, but opening the switch S5And closing the switch S6Will release Vdc3The association of (a); when considering the first switch 7S in the first half-bridge module 17And said second switch 8S in said first half-bridge module 18While, the switch S is turned on8And closing the switch S7Providing a current path connecting a DC voltage source 6V in said first half-bridge module 1dc4Added to the main circuit, but opening the switch S7And closing the switch S8Will release Vdc4The association of (a); the third switch 9S in the H-bridge module 59And said sixth switch 12S in said H-bridge module 510The switch-on operation will provide a positive half cycle of the AC output, the negative half of which is provided by the fifth switch 11S in the H-bridge module 511And the fourth switch 10S in the H-bridge module 512It is provided that, for a single cycle, the switching frequency of each half-bridge module is twice the switching frequency of the H-bridge module 5, the H-bridge module 5 operating at a switching frequency of 50Hz to produce a 50Hz ac output.
The harmonic suppression method of the multilevel DC link inverter comprises the following steps: step 1, increasing the number of half-bridge modules of a plurality of half-bridge modules provided by a multi-level direct-current link inverter to realize level expansion; step 2, according to the number of the plurality of half-bridge modules, different voltage distribution and proportion are carried out on the direct-current voltage sources in the plurality of half-bridge modules, and various outputs with different levels are obtained; step 3, determining the number of the selected cascaded half-bridge modules and the number of the switching angles, and calculating the angle value of the switching angle of each half-bridge module; step 4, calculating harmonic distortion content according to the angle value of the switching angle of each half-bridge module; step 5, reducing the angle value of the switching angle of the first half-bridge module by 1 degree and calculating the harmonic distortion content; step 6, judging whether the newly calculated harmonic distortion content is less than the previous harmonic distortion content, executing the step 5, if the newly calculated harmonic distortion content is not less than the previous harmonic distortion content, executing the step 5 for the switching angles of other half-bridge modules, and executing the step 7 until the newly calculated harmonic distortion content of the switching angle of the last half-bridge module is not less than the previous calculated harmonic distortion content; and 7, reducing the angle values of the switching angles of all the half-bridge modules by 0.1 degree, and executing the step 5 and the step 6 until the minimum harmonic distortion content is obtained.
Wherein, the step 1 specifically comprises: by increasing the number of dc voltage sources, the number of levels of the multilevel dc link inverter is increased, and the values of all dc voltage sources are the same, as follows:
Vdc,j＝Vdc j＝1,2,3,4… (1)
wherein, Vdc,jDenotes a dc voltage source with index j;
the number of levels and the number of switches of the output voltage of the multilevel DC link inverter are as follows:
Nlevel＝n-3 n＝6,8,10,12… (2)
wherein N islevelRepresents the number of levels of the output voltage, n represents the number of switches;
as the number of switches increases, the number of dc voltage sources also increases, as follows:
wherein N issourceRepresenting the number of dc voltage sources and n representing the number of switches.
The above embodiments of the present inventionAccording to the harmonic suppression method of the multilevel dc link inverter, the dc voltage sources in the multilevel dc link inverter can be classified into two categories according to their symmetry, namely, the multilevel dc link inverter with a symmetrical structure and the multilevel dc link inverter with an asymmetrical structure, the multilevel dc link inverter with the constant-amplitude dc voltage source is classified as a symmetrical multilevel dc link inverter, whereas an asymmetrical multilevel dc link inverter has an unequal dc power amount, and in the symmetrical structure, the voltage amplitudes of all the dc voltage sources are equal, and four possible voltage levels, namely, V, appeardc1、Vdc1+Vdc2、Vdc1+Vdc2+Vdc3And Vdc1+Vdc2+Vdc3+Vdc4Thus, a 9-level output is generated, which is the first of twelve possible configurations provided by the multi-level dc-link inverter, and this symmetrical configuration can be extended to any number of levels using equations (1) -3, where Vdc1Is a DC voltage source, V, in the fourth half-bridge module 4dc2Is a DC voltage source, V, in the third half-bridge module 3dc3Is a DC voltage source, V, in the second half-bridge module 2dc4Is the dc voltage source 6 in said first half-bridge module 1.
In an asymmetric configuration, the dc voltage sources are not equally sized, which produces more levels than a symmetric configuration, which helps to improve the ac output voltage waveform quality and associated harmonic distortion. However, as the multi-level dc-link inverter level, in which 11 asymmetrical structures are considered to produce outputs from 11 levels to 31 levels, increases, the number of operating modes of the multi-level dc-link inverter increases within a single cycle, resulting in an increase in switching frequency, with higher multi-level dc-link inverter levels always being preferred.
As shown in table 1, the voltage of each first dc voltage source is different, and in configuration 2, the voltage of the fourth dc voltage source is twice as large as that of the other three dc voltage sources, so that 11-level output is generated; structure 3 carries a dc voltage source ratio of 1:1:2:2 and produces a 13 level output; selecting a second DC voltage source, a third DC voltage source and a fourth DC voltage source twice as large as the first DC voltage source to generate a 15-level output; the 17 level output and the 19 level output are generated by DC voltage source ratios of 1:2:2:3 and 1:2:2:4 respectively; a direct current voltage source is connected behind a natural number sequence to generate 21-level output; to produce a 23 level output, a dc voltage source ratio of 1:2:3:5 was used, similar to the Fibonacci sequence; when the ratio of the direct current voltage source is 1:2:3:6, 25-level output is generated; outputs of 27 level and 29 level are generated with dc voltage source ratios of 1:2:4:6 and 1:2:4:7, respectively; a binary sequence dc voltage source ratio is used to generate 31 levels. Table 1 shows the combined operation mode of all the structures provided by the harmonic suppression method of the multi-level dc link inverter.
TABLE 1
Wherein, the step 3 specifically comprises: when the number of half-bridge modules is 4, the value of the angle of the switching angle of the half-bridge modules is calculated by the following equation:
wherein alpha isiThe angle value representing the switching angle i of the half-bridge module, i ═ 1,2,3, 4.
The harmonic suppression method of the multilevel dc link inverter according to the above embodiment of the present invention is shown in fig. 2, which shows a single cycle of 7-level multilevel dc link inverter (MLI) output compared to a sinusoidal waveform and also shows a quarter cycle, which is an operation of the conventional schemeProviding an insight. For ease of understanding, the sinusoidal waveform cutting the rising edge of the multilevel dc link inverter level can be divided into two parts, the upper part being called the Upper Segment (USL) and the lower part being called the Lower Segment (LSL), the sizes of USL and LSL being the same for the harmonic suppression method. This applies to all rising edges of the multilevel dc-link inverter level, the angle value α of the switching angle being calculated by means of equation (4)i。
Wherein, the step 4 specifically comprises: the harmonic distortion content is calculated by the following equation:
where THD represents the harmonic distortion content.
The harmonic suppression method for the multilevel dc link inverter according to the above embodiment of the present invention needs to correctly calculate the harmonic distortion, and replace the switching angle in the harmonic distortion equation (5) to determine whether the new set of switching angles increases or decreases the harmonic distortion.
Wherein, the step 5 and the step 6 specifically include: by researching a nine-level structure provided by the multi-level direct-current link inverter, wherein the nine-level structure comprises four switching angles, the harmonic distortion content is calculated for an initial set of the four switching angles, and the angle value alpha of the first switching angle is iterated for the first time1Reducing by 1 degree and maintaining the angle value alpha of the second switching angle2Angle value alpha of the third switching angle3And the angle value alpha of the fourth switching angle4Calculating the harmonic distortion content using the updated switching angle, comparing the newly calculated harmonic distortion content with the previously calculated harmonic distortion content, and when the newly calculated harmonic distortion content is less than the previously calculated harmonic distortion content, the angle value alpha of the first switching angle is1Reducing by 1 degree again, and repeating the first iteration process until the newly calculated harmonic distortion content is not further reduced compared with the previously calculated harmonic distortion content; when the newly calculated harmonic distortion content is greater than the previously calculated harmonic distortion contentWhen the harmonic distortion content exists, reducing the angle value of the next switching angle by 1 degree, keeping other switching angles unchanged, and executing the iteration operation; when the angle value alpha is changed by changing the first switching angle1The angle value alpha of the second switching angle is implemented when the newly calculated harmonic distortion content obtained is not further reduced compared to the previously calculated harmonic distortion content2Reducing by 1 degree until a new calculated harmonic distortion content is obtained without further reduction compared to the previously calculated harmonic distortion content, and performing a third switching angle with an angle value alpha3Reducing by 1 degree until a new calculated harmonic distortion content is obtained without further reduction compared to the previously calculated harmonic distortion content, and performing an angle value alpha of a fourth switching angle4The 1 degree reduction operation is performed until a new calculated harmonic distortion content is obtained without further reduction from the previously calculated harmonic distortion content, forming a first loop.
Wherein, the step 7 specifically comprises: when the angle value of the fourth switching angle is alpha4And when the newly calculated harmonic distortion content is obtained and is not further reduced compared with the previously calculated harmonic distortion content, reducing the angle values of all the switching angles by 0.1 degrees, and executing the angle value alpha from the first switching angle1The beginning whole process is repeated again for the same change of reducing 1 degree, and a second cycle is formed; the above cycle is repeated until a minimum harmonic distortion content is obtained.
The harmonic suppression method for the multilevel dc link inverter according to the above embodiment of the present invention performs a nine-level structure research provided by the multilevel dc link inverter, where the nine-level structure has four switching angles, the harmonic suppression method first calculates a harmonic distortion content by using an initial set of switching angles, and iterates for the first time, where an angle value α of the first switching angle is1Reducing by 1 degree and maintaining the angle value alpha of the second switching angle2Angle value alpha of the third switching angle3And the angle value alpha of the fourth switching angle4Unchanged, with the angle value alpha of the updated first switching angle1Calculating harmonic distortion content and calculating new harmonic distortionComparing the true content with the previously calculated harmonic distortion content, and when the newly calculated harmonic distortion content is less than the previously calculated harmonic distortion content, the angle value alpha of the first switching angle1Further reducing by 1 degree, and carrying out second iteration until the newly calculated harmonic distortion content is not further reduced compared with the previously calculated harmonic distortion content; the angle value alpha of the second switching angle is greater when the newly calculated harmonic distortion content is greater than the previously calculated harmonic distortion content2Reducing by 1 degree and maintaining the angle value alpha of the first switching angle1Angle value alpha of the third switching angle3And the angle value alpha of the fourth switching angle4With unchanged angle value alpha of the updated second switching angle2Calculating the harmonic distortion content, comparing the newly calculated harmonic distortion content with the previously calculated harmonic distortion content, and when the newly calculated harmonic distortion content is less than the previously calculated harmonic distortion content, the angle value alpha of the second switching angle2Further reducing by 1 degree, and continuing iteration until the newly calculated harmonic distortion content is not further reduced compared with the previously calculated harmonic distortion content; the angle value alpha of the third switching angle is greater when the newly calculated harmonic distortion content is greater than the previously calculated harmonic distortion content3Reducing by 1 degree and maintaining the angle value alpha of the first switching angle1Angle value alpha of the second switching angle2And the angle value alpha of the fourth switching angle4Unchanged, with the angle value alpha of the updated third switching angle3Calculating the harmonic distortion content, comparing the newly calculated harmonic distortion content with the previously calculated harmonic distortion content, and when the newly calculated harmonic distortion content is less than the previously calculated harmonic distortion content, the angle value alpha of the third switching angle3Further reducing by 1 degree, and continuing iteration until the newly calculated harmonic distortion content is not further reduced compared with the previously calculated harmonic distortion content; the angle value alpha of the fourth switching angle is greater when the newly calculated harmonic distortion content is greater than the previously calculated harmonic distortion content4Reduce by 1 degree and maintain a first switch angleAngle value alpha of1Angle value alpha of the second switching angle2And the angle value alpha of the third switching angle3Unchanged, with the angle value alpha of the updated fourth switching angle4Calculating the harmonic distortion content, comparing the newly calculated harmonic distortion content with the previously calculated harmonic distortion content, and when the newly calculated harmonic distortion content is less than the previously calculated harmonic distortion content, the angle value alpha of the fourth switching angle4Further reducing by 1 degree, and continuing iteration until the newly calculated harmonic distortion content is not further reduced compared with the previously calculated harmonic distortion content; when the angle value alpha is changed by changing the first switching angle1The angle value alpha of the second switching angle is implemented when the newly calculated harmonic distortion content obtained is not further reduced compared to the previously calculated harmonic distortion content2Reducing by 1 degree until a new calculated harmonic distortion content is obtained without further reduction compared to the previously calculated harmonic distortion content, and performing a third switching angle with an angle value alpha3Reducing by 1 degree until a new calculated harmonic distortion content is obtained without further reduction compared to the previously calculated harmonic distortion content, and performing an angle value alpha of a fourth switching angle4The 1 degree reduction operation is performed until a new calculated harmonic distortion content is obtained without further reduction compared to the previously calculated harmonic distortion content, which is the first cycle. When the angle value of the fourth switching angle is alpha4When the newly calculated harmonic distortion content is not further reduced compared with the previously calculated harmonic distortion content, the angle values of all the switching angles are reduced by 0.1 degree from the angle value alpha of the first switching angle1The whole process starting with a decrease of 1 degree repeats again the same change of angle value by 1 degree, which forms a second cycle. These cycles are repeated until a minimum harmonic distortion content is obtained. To change alpha1、α2、α3And alpha4Again repeating the process as experienced, helps to adjust the angle.
According to the number of the switch angles i, the cycle required for completing the harmonic suppression methodThe number of phases is different and the number of cycles required to complete the harmonic suppression method increases with increasing switching angle, table 2 shows the important results for a nine-level configuration, and the difference in harmonic distortion content between the different iterations can be seen from the number of iterations 1, 10, 16, 25, 37 and 42. The difference in harmonic distortion content for the nine-level configuration is due to equation (5) taking into account the sinusoidal nature of the output of the multilevel dc-link inverter, and it can be seen from table 2 that the value of the angle α at the first switching angle is α1The harmonic distortion content is not reduced any further after the reduction and therefore remains at the same level between iterations 1 and 10. However, the angle value α with the second switching angle2The harmonic distortion content is reduced. Angle value alpha of the second switching angle after the 10 th iteration2After continuing to decrease to the 25 th iteration, the harmonic distortion content is not further decreased, and therefore, the angle value alpha of the third switching angle is decreased3So as to observe the variation of the harmonic distortion content and then reduce the angle value alpha of the fourth switching angle4The variation of the harmonic distortion content is continuously observed.
TABLE 2
The result that can be derived from table 2 is the angle value α of the fourth switching angle4The variation in (c) will have a significant effect on the harmonic distortion content. Therefore, the iteration between the fourth switching angles shows a significant change. Angle value alpha of first switch angle1The impact on harmonic distortion content is minimal and table 2 gives an inference of 42 iterations to reach a minimum harmonic distortion content of 8.9025%, which provides the final switching angle. The accuracy of iterations 1, 10 and 16 was 1 degree, while the accuracy of iterations 25, 37 and 42 was 0.10 degree. Similar attempts can be made for the above process for other asymmetric structures. While implementing the method for all symmetric and asymmetric structures, the number of levels and the number of switching angles for each structure need to be re-determined. This is because the number of layers per structure is different, and the number of switching angles is also different. Thus, an overlapThe number of generations increases with the number of switching angles. The harmonic suppression method is then repeated from start to finish. The entire process is a flexible implementation using equations (4) and (5) in the form of simple MATLAB code. Before the multi-level direct current link inverter is operated, the switching angle is modified to obtain a final switching angle and the final switching angle is programmed into a microcontroller, a multi-level direct current link inverter (MLDCLI) circuit is operated on a pre-programmed microcontroller program, no further monitoring is needed, harmonic distortion is controlled through a harmonic suppression method of the multi-level direct current link inverter, the harmonic distortion content of output voltage and output current is reduced, the effective value of the output voltage and the output current is increased, and the output power is improved.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (6)
1. A method of harmonic suppression for a multilevel dc link inverter, the multilevel dc link inverter comprising:
a first half-bridge module;
a second half-bridge module, a first end of the second half-bridge module electrically connected with a second end of the first half-bridge module;
a third half-bridge module, a first end of the third half-bridge module electrically connected with a second end of the second half-bridge module;
a fourth half-bridge module, a first end of the fourth half-bridge module being electrically connected with a second end of the third half-bridge module;
a first end of the H-bridge module is electrically connected with a first end of the first half-bridge module, and a second end of the H-bridge module is electrically connected with a second end of the fourth half-bridge module;
the first, second, third and fourth half-bridge modules each include:
a DC voltage source;
a first switch, a second end of the first switch being electrically connected to a first end of the DC voltage source;
a second switch, a first end of the second switch being electrically connected to the second end of the DC voltage source, a second end of the second switch being electrically connected to the first end of the first switch;
a first terminal of the first switch in the second half-bridge module is electrically connected to a second terminal of the first switch in the first half-bridge module, a first terminal of the first switch in the third half-bridge module is electrically connected to a second terminal of the first switch in the second half-bridge module, a first terminal of the first switch in the fourth half-bridge module is electrically connected to a second terminal of the first switch in the third half-bridge module;
the H-bridge module includes:
a third switch having a first end electrically connected to the first end of the first switch in the first half-bridge module;
a fourth switch, a first end of the fourth switch being electrically connected to a second end of the third switch;
a fifth switch, a first end of the fifth switch being electrically connected to a first end of the third switch;
a sixth switch, a first terminal of the sixth switch being electrically connected to the second terminal of the fifth switch, a second terminal of the sixth switch being electrically connected to the second terminal of the first switch in the fourth half-bridge module, a second terminal of the sixth switch being electrically connected to the second terminal of the fourth switch;
a first end of the load is electrically connected with the first end of the fourth switch, and a second end of the load is electrically connected with the first end of the sixth switch;
the harmonic suppression method of the multilevel DC link inverter comprises the following steps:
step 1, increasing the number of half-bridge modules of a plurality of half-bridge modules provided by a multi-level direct-current link inverter to realize level expansion;
step 2, according to the number of the plurality of half-bridge modules, different voltage distribution and proportion are carried out on the direct-current voltage sources in the plurality of half-bridge modules, and various outputs with different levels are obtained;
step 3, determining the number of the selected cascaded half-bridge modules and the number of the switching angles, and calculating the angle value of the switching angle of each half-bridge module;
step 4, calculating harmonic distortion content according to the angle value of the switching angle of each half-bridge module;
step 5, reducing the angle value of the switching angle of the first half-bridge module by 1 degree and calculating the harmonic distortion content;
step 6, judging whether the newly calculated harmonic distortion content is less than the previous harmonic distortion content, executing the step 5, if the newly calculated harmonic distortion content is not less than the previous harmonic distortion content, executing the step 5 for the switching angles of other half-bridge modules, and executing the step 7 until the newly calculated harmonic distortion content of the switching angle of the last half-bridge module is not less than the previous calculated harmonic distortion content;
and 7, reducing the angle values of the switching angles of all the half-bridge modules by 0.1 degree, and executing the step 5 and the step 6 until the minimum harmonic distortion content is obtained.
2. The method according to claim 1, wherein the step 1 specifically comprises:
by increasing the number of dc voltage sources, the number of levels of the multilevel dc link inverter is increased, and the values of all dc voltage sources are the same, as follows:
Vdc,j＝Vdc j＝1,2,3,4… (1)
wherein, Vdc,jDenotes a dc voltage source with index j;
the number of levels and the number of switches of the output voltage of the multilevel DC link inverter are as follows:
Nlevel＝n-3 n＝6,8,10,12… (2)
wherein N islevelTo representThe number of levels of the output voltage, n representing the number of switches;
as the number of switches increases, the number of dc voltage sources also increases, as follows:
wherein N issourceRepresenting the number of dc voltage sources and n representing the number of switches.
3. The method according to claim 2, wherein the step 3 specifically comprises:
when the number of half-bridge modules is 4, the value of the angle of the switching angle of the half-bridge modules is calculated by the following equation:
wherein alpha isiThe angle value representing the switching angle i of the half-bridge module, i ═ 1,2,3, 4.
4. The harmonic suppression method of the multilevel dc link inverter according to claim 3, wherein the step 4 specifically comprises:
the harmonic distortion content is calculated by the following equation:
where THD represents the harmonic distortion content.
5. The harmonic suppression method of the multilevel dc link inverter according to claim 4, wherein the steps 5 and 6 specifically include:
by applying a voltage to the multi-level DC link inverterThe provided nine-level structure is researched, the nine-level structure comprises four switching angles, harmonic distortion content is calculated for an initial set of the four switching angles, and the angle value alpha of the first switching angle is iterated for the first time1Reducing by 1 degree and maintaining the angle value alpha of the second switching angle2Angle value alpha of the third switching angle3And the angle value alpha of the fourth switching angle4Calculating the harmonic distortion content using the updated switching angle, comparing the newly calculated harmonic distortion content with the previously calculated harmonic distortion content, and when the newly calculated harmonic distortion content is less than the previously calculated harmonic distortion content, the angle value alpha of the first switching angle is1Reducing by 1 degree again, and repeating the first iteration process until the newly calculated harmonic distortion content is not further reduced compared with the previously calculated harmonic distortion content; when the newly calculated harmonic distortion content is larger than the previously calculated harmonic distortion content, reducing the angle value of the next switching angle by 1 degree, keeping other switching angles unchanged, and executing the iteration operation; when the angle value alpha is changed by changing the first switching angle1The angle value alpha of the second switching angle is implemented when the newly calculated harmonic distortion content obtained is not further reduced compared to the previously calculated harmonic distortion content2Reducing by 1 degree until a new calculated harmonic distortion content is obtained without further reduction compared to the previously calculated harmonic distortion content, and performing a third switching angle with an angle value alpha3Reducing by 1 degree until a new calculated harmonic distortion content is obtained without further reduction compared to the previously calculated harmonic distortion content, and performing an angle value alpha of a fourth switching angle4The 1 degree reduction operation is performed until a new calculated harmonic distortion content is obtained without further reduction from the previously calculated harmonic distortion content, forming a first loop.
6. The harmonic suppression method of a multilevel dc link inverter according to claim 5, wherein the step 7 specifically comprises:
when the angle value of the fourth switching angle is alpha4And when the newly calculated harmonic distortion content is obtained and is not further reduced compared with the previously calculated harmonic distortion content, reducing the angle values of all the switching angles by 0.1 degrees, and executing the angle value alpha from the first switching angle1The beginning whole process is repeated again for the same change of reducing 1 degree, and a second cycle is formed; the above cycle is repeated until a minimum harmonic distortion content is obtained.
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